JPS60163295A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To detect the change of a sense line rapidly and to increase the speed and capacity of a ROM by inputting different voltages to a differential amplifier in a sense circuit. CONSTITUTION:MOSFETs 40-48 constitute the sense circuit and the FETs 40- 46 constitute a DC differential amplifier. The drain current of the FETs 42, 43 is changed in accordance with the differential voltage between the voltage of the sense line 1 and the terminal voltage of a capacitor 25 and the changed value is read out as the drain voltage of the FETs 42, 43. The line and the capacitor 25 are charged at the same potential by a precharge circuit, and after completing the precharge operation, the terminal voltage of the capacitor 25 is turned to a voltage slightly lower than the voltage of the line 1 by feed-through operation. Inverters 47, 48 shape the waveform of an output signal from the differential amplifier and the status of the line 1 is detected as a ''H'' or ''L'' level at an output terminal 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory sensing method, and particularly to a semiconductor memory device suitable for increasing the speed of reading information.

[Background of the invention]

IC (integr) including microprograms
ated circuit), LSI (la
rgescale integrated circuit
LOM (R
eadOnlyMemory).

However, as the speed of each LSI increases with the miniaturization of elements, the read speed of the ROM is also required to increase. A ROM usually has a configuration as shown in Figure 1. When an n-bit digital signal, which is an address signal, is applied, a decoder D selects one of 211 word lines and writes the m-bit memory pattern on that word line. is detected by the sense circuit So"5--t. In the figure, the ○ marks at the intersections of the word line and the m sense lines (tI to t, ,) indicate the presence or absence of a coupling element, 'H#, "'L" This indicates that information corresponding to the information is created.

For the sense circuit 8 g ''' = S + m-1, a voltage detection method is often used from the viewpoint of power consumption, etc. Also, as a sense method to reduce the size of the memory, the sense line is usually connected to 211 word lines. In other words, the sense line is first connected to a precharge circuit (
P6-P-+) to pre-charge to an arbitrary voltage level. (Precharge) Next, the precharge voltage of the sense line is discharged or maintained as it is depending on the memory pattern of the word line selected manually by the address. The state of this sense line is detected by a sense circuit S such as a sense amplifier.

~Detected at Sm-1.

In such a configuration, as the speed of peripheral circuits increases, the RO
When increasing the speed of M, problems arise with the precharge circuit for charging the sense line and the sense circuit used for reading.

From the viewpoint of high integration, it is effective to configure the memory with MOS transistors. However, g of the MOS transistor,
Since the on-resistance is small, the on-resistance is large, and it takes time to charge the load capacitance and parasitic capacitance.

Therefore, in order to increase the speed of the precharge circuit that charges the sense line, it is necessary to increase the size of the charging MOS transistor or to devise a gate control method. However, these countermeasures are downsized.

This goes against the trend of high integration.

Also, Damane Sen aims to speed up the sense amplifier.

The difference between the comparison voltage of the sense amplifier and the charging voltage of the sense line is expressed by the number 10.
Conventionally, this method uses a sense amplifier with a voltage clamp or feedback configuration to reduce the voltage amplitude, or uses a dummy cell as a comparison voltage source to create a slight voltage difference. . Therefore, the sense amplifier has a relatively large circuit configuration, and the influence of processing precision on the comparison voltage cannot be avoided.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor memory device that can detect changes in a sense line at high speed.

[Summary of the invention]

The present invention is characterized in that, in a semiconductor memory device equipped with a sense circuit having a differential amplifier, a control circuit that generates from one voltage a voltage lower than the other voltage is provided. The one voltage and the other voltage are input to the differential amplifier.

In a preferred embodiment of the present invention, the one voltage is a precharge voltage sb, and the control circuit that generates the other voltage lower than the one voltage from the one voltage,
Utilizes the field through of MOS transistors.

Furthermore, in a preferred embodiment of the present invention, the sense circuit is configured with a DC differential amplifier and an AC amplifier, and a high gain,
Get a high speed sense amplifier.

Furthermore, in a preferred embodiment of the present invention, the comparison voltages of the high-speed precharge circuit and the sense amplifier can be realized in the same configuration by using an amplifier that combines bipolar transistors and MOS transistors.

Furthermore, in a preferred embodiment of the present invention, the signal applied to the output of the AC amplifier from the output of the DC differential amplifier of the sense circuit is taken from the differential input terminal not connected to the sense line. High-speed detection is possible without being affected by capacity, and a high-speed, large-capacity ROM is realized.

[Embodiments of the invention]

FIG. 2 is a diagram showing the basic configuration of the first embodiment of the present invention.
1 is a sense line, 2 is a precharge circuit for precharging the sense line, 3 is a control circuit that creates a voltage slightly lower than the output voltage of the precharge circuit, 4 is a sense circuit that detects the state of the sense line 1, 5 is an output signal corresponding to the state of sense line 1. The coupling element shown in FIG. 1 is not shown in FIG.

In this configuration, the voltage generating means is placed only in the precharge circuit 2, and based on this precharge voltage, the voltage generation means is placed in the sense circuit 4.
Two input terminals (the precharge voltage of the sense line 1 and the output voltage of the control circuit 3) are determined. Therefore, since the voltage relationship between each part is determined from one voltage source, the configuration is such that operational problems are unlikely to occur.

FIG. 3 shows the configuration of the precharge circuit.

In FIG. 3(a), 100 is a power supply anode, and 20 is a p-channel MOS whose source end is connected to the power supply anode 100.
A transistor (hereinafter referred to as pMO8), 21 has its collector connected to the power supply anode end 100, and its base end connected to 9MO820.
npn) transistor 22 has its drain end connected to the drain end of I)MO820, and its gate end is connected to the gate end of 9MO820 and npn) transistor 2.
Connect the emitter end of 1 and the source end to the power supply cathode 1o1
An 11-channel MOS transistor (hereinafter referred to as nM) connected to
23 is an n-channel MOS transistor whose drain end is nprl and is connected to the emitter end of the transistor 21. 24 is an input terminal that provides a signal to the 0MO823 (D gate end), and 25 is one end connected to the source end of the 0MO823. , a capacitor whose other end is connected to the power supply cathode 101,
26 is an output terminal connected to the source end of 0MO823, c
, is a capacitance attached to the emitter end of the npn transistor 21, and has a different value depending on the size of the storage capacitance.

The operation of this configuration is as follows.

Now, if the terminal voltage of the capacitor 25 is at the power supply cathode terminal voltage and the terminal 24 is at the "to H" level, the point a becomes the "'L" level, and the current I flowing through the 9MO820 at this time is expressed as: , βOp+β, are each 1) M
represents the channel conductance frequency and channel dimension ratio (channel width/channel length) of O820, Va is the gate voltage, Vcci'tili source anode voltage 100 voltage, vt
Yesterday is the threshold voltage.

The current in formula (1) is npn) Since it becomes the base current of the transistor 21, the emitter current of the npn transistor 21 is 1
．． is I, = (1+ hrw)I, = LrtIp
−・−(z). Here, hl' is the DC amplification factor of the pn transistor 21.

(The current of the foundation formula is 9MO820, nMOS22
(Since the D gate has high impedance, the capacitor C
2 and charges the capacitor 25 through the 0MO823 (precharge). The charging voltage of the two capacitors is 9
When the voltage exceeds the logic threshold voltage of the inverter consisting of MO820 and 1MO822, the gate-source voltage of 9MO820 becomes small, and 9MO820 turns off. Therefore, since the base current of the pn transistor 21 is no longer supplied, the npn transistor 21 is cut off.

At this time, the pace voltage is lower than the voltage at point a by the forward voltage between the base and emitter of the npro transistor 21 (Vgg
) is in a high state.

In a normal inverter configuration, the transfer characteristic is as shown in FIG. 3(b). In this figure, β1 to β3 are 9MO820 and r1M
As the size ratio with O822 ((nMOS channel width/channel length)/(pMos channel width/channel length)) becomes smaller, the transfer characteristic changes from β1 to β3.

When the input and output terminals of the inverter are short-circuited, the input and output voltage becomes the voltage at the intersection of the transfer characteristic and the straight line of V l a = V * w t, but the inverter output voltage of this configuration is ■1 = V
This is the intersection of the transfer characteristic and a straight line shifted by the forward voltage from the straight line of e w t.

A method of creating a voltage slightly lower than V after the voltage at point a has been charged (precharged) to V in the configuration shown in FIG. 3 will be explained. The function of creating a slightly low voltage in this way is performed by the control circuit 3 shown in FIG. 2, and is for detecting voltage changes on the sense line 1 at high speed.

FIG. 4 shows a configuration in which the input terminal V'+a is transmitted to the output side using an n-channel MO8) transistor Sw as a switching element. Here, C0 is the capacitance attached to the output terminal, C
is the overlap capacitance formed between the gate electrode and the drain/(or source) diffusion layer in the MOS transistor Sv, φ
is a control input applied to the gate electrode.

Now, when the control signal "H" is manually applied to φ, the output terminal V ea
Input terminal v-1 is transmitted to t. V+ is charged to the load capacitance C0, but when the control signal becomes "L", the charge charged to C0 is distributed due to the overlapping capacitance C, and the output voltage becomes smaller by ΔV from V rat. This ΔV is expressed as ΔV=□ΔVφ (3) C, +C, where ΔVφ is the amount of voltage change from the ``H'' level to the ``L'' level at the terminal φ.

ΔV in equation (3) is generally called a feed-through error voltage, and is considered a problem as an error that occurs during switching of a Mo8 transistor. This ΔV is determined by the values of C and C as in the (3) equation, so it is a value that determines the dimensions, and Δ■φ can also be determined at the logical level, so ΔV in equation (3) is determined by design. This is a value that can be controlled with a certain amount of perspective.

This function is achieved by the voltage v1.0MO8 at point a in Figure 3.
23, can be realized by capacitor 25, mouth MO823
By turning off the voltage V, which was charged in the capacitor 25, changes to V, -ΔV.

This voltage at point a is divided by the capacitor voltage v, -.

, FIG. 5 shows a precharge circuit and a control circuit of the present invention that are effective for a plurality of sense lines.

In the figure, 100.20 to 26 and C2 indicate the same configuration as in FIG. 3. 27 is an n-channel MOS transistor whose drain end is connected to the base end of the l1pn transistor 21 and whose source end is connected to the power supply cathode end; 28 is 0;
This is the gate signal input terminal of MO827. 211 connects the collector end to the power anode end 100, and the base end to the 9MO
npnl-transistor connected to the drain end of 820,
tl is a sense line connected to the emitter end of the npro transistor 211, CLI is a load capacitance attached to the sense line 21,
Similarly, 212. 2ij are npn) transistors whose collector ends are connected to the power supply anode end and base ends are connected to the drain end of 9MO820, respectively, Z2 + 11 are the second and jth sense lines, respectively, C1, z, Ct, J are respectively This is the load capacitance attached to the second and jth sense lines.

When 0MO823 is on and r1MO827 is off, the capacitor 25, C, is charged to the voltage V at point a mentioned above, and the base voltage of the transistor 21 is V.
The voltage becomes −+ V mm.

Also npn) transistors 21, 211, 212゜211
Since the bases of the transistors are connected to each other, the base voltage of each transistor is also V − + V B v. Therefore, each sense line t1-1. Load capacity CLI.

Cbj will be charged to V.

The gate MO 827 applies a 1H'' level signal to the gate 28 to cut off the npn transistors 21, 211, 212, and 21j when stopping the precharge operation, and also to reduce the accumulation time of each transistor when off. Acts as a resistance.

When one pit of H and OM in FIG. 2 is configured using the precharge circuit and control circuit described above, the result is as shown in FIG. 6.

Here, the same parts as those described in FIGS. 2 to 5 are designated by the same reference numerals.

31 is an input terminal, 32 is a p-channel MOS transistor whose drain end is connected to the input terminal 31, and whose source end is connected to the power anode 100;
The drain end is connected to the gate end of 0MO823, the gate end is connected to the input terminal 31, and the source end is connected to the power supply cathode terminal 1.
It is an n-channel Mo8) transistor connected to 01.

The configurations 31 to 33 use inverters to provide gate signals for the MO 823, but may be omitted if there is no problem in terms of characteristics.

40 to 48 constitute a sense circuit.

In the figure, 40 indicates the source end and the power supply anode end 1o.

41 is a p-channel MOS transistor whose source end is connected to the power source anode 100, and whose gate and drain ends are connected to the gate end of 9MO840. 42 is a p-channel transistor whose drain end is connected to the drain end of 9MO840. , an n-channel MoS transistor whose gate end is connected to sense line 1, 43 has a drain end connected to 9MO84
1, the source end to the source end of 0MO842, and the gate end to one end of capacitor 25. 45 has its drain end connected to the source end of 0MO842, An n-channel MOS transistor whose source end is connected to the power supply cathode end 101, 46 is a terminal that provides the gate voltage of 0MO845, 4
7 is a p-channel MO whose drain end is connected to the power supply anode end 100 and whose gate end is connected to the drain end of the mouth MO 842;
8) The transistor 48 is an n-channel MO transistor whose drain end is connected to the source end of 9MO847, whose gate end is connected to the drain end of 0MO842, and whose source end is connected to the power supply cathode 101.

40 to 46 constitute a DC differential amplifier. That is, the drain currents of the 0MOs 842 and 43 change in response to the difference voltage between the voltage of the sense line 1 and the terminal voltage of the capacitor 25, and the amount of change is read out as the drain voltage of the 0MOs 842 and 43.

0MO845 is a constant current circuit of a differential amplifier, and the voltage V46 at terminal 46 causes a constant current circuit of the following formula. flows.

1, =-19m"β-(V46 Vth-)"・'・
(4) Here, β0. β is the channel conductance constant and size ratio (channel width/channel length) of 0MO845, respectively, and Vths is the threshold voltage.

The drain currents of 0MO842 and 43 are InH and
If Io<3, then 1 of equation (4). ■. = I 0
42-)-I D43-(5).

Moreover, Io4□ and Io4B are expressed as. Here, β, 2. β43 is 0M each
Dimensional ratio of O842 and 43 (channel width/channel length),
Vr is the voltage of the sense line, V25 is the charging voltage of capacitor 25
! Tortoise pressure, V, is the voltage at the source end of finMO842 and 0MO843 and the drain end voltage at mouth MO845.

From equations (6) and (7), the difference between the sense line voltage and the capacitor terminal voltage is expressed as: Here, V7 and Vβ0.・β is a constant.

The difference voltage V+Vzs between the sense line voltage and the terminal voltage of the capacitor according to equation (8) changes as shown in FIG. 7, and operates as a linear amplifier in a signal range where there is a difference voltage. The output voltage in this signal region (the drain voltage of the MOs 842 and 43) is determined according to the differential voltage and its gain.

Next, the voltage gain G in this configuration is as follows. Now, for the sake of simplicity, calculate the gain using 9MO841 and 9MO843. When both 9MO841 and 0MO843 are in the saturation region, the currents I, , 1. becomes as follows.

Here, βOPsβ, t/′i, respectively, p M O
Channel conductance constant and dimension ratio (channel width/channel length) of S, drain end voltage of Vo fd pMOS 41, V2. is the terminal voltage of capacitor 25, Vcc
is the power supply anode terminal voltage, V is the source terminal voltage of 0MO843, and Vthp is the threshold voltage of 2MO8.

(9) and α [from the formula βop'βp (Vo Vcc Vtbp)2-βOR
・β. (V25 V-Vth-F...aυ...α is obtained, and the voltage gain G7 is stopped.

By using the above differential amplifier, 0MO8 corresponds to the difference voltage (Vr Vzs) between the terminal voltage of the sense line 1 and the capacitor 25.
The drain currents of 42 and 43 change [formula (8)], I)
The change in the drain terminal voltage of MO841 is the voltage gain [(2)
It is obtained by the formula].

The operation after the precharge operation up to the differential amplifier is as follows.

First, the sense line 1 and the capacitor 25 are charged to the same potential by the precharge circuit. After the precharge operation is completed, the terminal voltage of the capacitor 25 becomes a voltage slightly lower than the voltage of the sense line 1 by Δ■ due to the feed-through operation.

When such a potential relationship exists, the difference in voltage between the voltage of the sense line 1 and the capacitor 25 is small, so the operating point of the differential amplifier can be placed in the linear region of FIG. 7 and near V8 where the highest gain can be obtained. can.

47 and 48 constitute an inverter, which shapes the waveform of the output signal of the differential amplifier for transmission to the next stage. Therefore, at the output terminal 5, the state of the sense line can be detected at the 'H' and 'L' levels.

2' is the first word line selected by the decoder,
60 is an n-channel M whose drain end is connected to the sense line 1, whose gate end is connected to the word line 2I, and whose north end is grounded.
This is the coupling element explained in FIG.

The operation shown in FIG. 6 will be explained in detail.

When the terminal 28 goes to the "L" level, the precharge circuit operates and the sense line 1 is charged by the npn transistor.At this time, the terminal 31 is also at the "L" level and the nMO
Since S23 is also turned on, the capacitor 25 is also charged to a voltage equal to the charging voltage of the sense line 1.

When the voltage of the sense line increases and I) MOS20 turns off, n
pn) The transistors 21 and 211 are also turned off, and the precharge circuit becomes inoperable. Next, when the terminal 31 becomes H" level, the nMOS 23 is turned off, and the charging voltage of the capacitor 25 becomes as high as the precharging voltage due to feed-through. ) The voltage is lower by ΔV of the equation.In this state, the operating point of the DC differential amplifier is in the linear region, and high gain detection is possible.

In this state, when the word line 2' is selected and becomes "H" level, the 1MO 860 is turned on and the precharge voltage of the sense line 1 is discharged. This discharge voltage change is caused by the capacitor 25
When the voltage at the output terminal 5 also decreases, the output voltage of the DC differential amplifier (voltage at the point shown in FIG. 6) increases and the signal at the output terminal 5 changes from 'H' to 'L'.

If the 1MO 860 is not present, even if the word line 2I is selected, the precharge voltage of the sense line will not be discharged and the signal at the output terminal 5 will remain at the "H#" level.

According to the first embodiment of the present invention, (1) By utilizing the feed-through error voltage that occurs during switching of a MOS transistor, a voltage that is slightly lower than the voltage before switching can be created, so a sense circuit using this can be used. This makes it possible to speed up reading from the ROM.

(2) A precharge circuit that combines a MOS inverter and an Ibora transistor.The high-speed precharge circuit is self-biased by connecting the emitter of the bipolar transistor connected to the sense line and the gate of the MOS inverter. A charge circuit is created.

(3) Since the comparison voltage of the sense circuit is generated based on the voltage of the precharge circuit, the magnitude relationship of the potentials is uniformly determined.

A second embodiment of the invention is shown in FIG.

In Fig. 8, the feed-through error voltage is further reduced, and the voltage difference with the sense line is made very small.The difference from Fig. 6 is that one end of the capacitor 25 is equipped with an nMO323 and a MOS transistor 230 with anti-phase operation. It is located where the . As mentioned above, the feedthrough error voltage is unavoidable when using a MOS transistor, but it can be foreseen from the design standpoint.

When the terminal 31 changes from the +LII level to the ``''H17 level, Δ■ in equation (3) becomes.Here, C230 is the overlapping capacitance between the gate, drain, and source of 0MO8230.

Journal of 5solid 5tate C1
rcuits vol.

8C-10All-M2S Charge i(,e
distril)utionAnalog to Di
Digital Conversion Technique
According to epart [, it is reported that the value of equation 0 is about iomv, and a very small difference voltage can be created compared to the precharge voltage. Therefore, according to this embodiment, the voltage difference between the DC differential amplifiers of the sense circuit can be reduced, resulting in an effect that the speed can be further increased.

A third embodiment of the invention is shown in FIG.

FIG. 9 shows a plurality of sense lines 1. -1. In contrast, a configuration in which the MOS inverter of the precharge circuit and the sense circuit are used in common is shown.

This configuration has the configuration shown in FIG. 6 with switching MO8 transistors 400 to 40j between the sense line and the sense circuit, and switching MO8 transistors between the sense line and the precharge circuit.
) transistors 200 to 20j are provided.

In the figure, lθ to 1j are input terminals.

400 to 40j are switches provided between the sense line and the sense circuit.

400 is an n-channel MOS transistor whose drain end is connected to the sense line to, whose gate end is connected to the input terminal 10, and whose source end is connected to the drain end of 0MO823 and the gate end of nMO842 of the DC differential amplifier; 401 is the drain end is connected to the sense line t1, and the gate end is connected to the input terminal 11.
It is an n-channel MO8) transistor whose source end is connected to the drain end of the 0MO823 and the gate end of the nMO842 of the DC differential amplifier.

The following connections 402 to 40j are similar.

200 to 20j are switches provided between the sense line 1o-1 and the precharge circuit.

200 is an n-channel MOS transistor whose drain end is connected to the sense line TO, whose gate end is connected to the input terminal IO, and whose source end is connected to the gate end of 0MO822;
1 is an n-channel transistor whose drain end is connected to the sense line tI, whose gate end is connected to the input terminal 11, and whose source end is connected to the gate end of 0MO822.

The following lines 202 to 20 have the same structure. To explain the operation of this configuration regarding OK, first, when the input terminal 10 goes to H'' level, nMO820Q 11 to 1j are at L'' level.

400 is turned on and the sense line 1. Precharge.

At this time, 1MO827 is in the off state, and 1M
O8402-40j are in the off state, but each sense line 1.
-1. The load capacitance attached to the battery is also precharged.

Of course, at this time, the capacitor 25 is also precharged to the same voltage as the sense line.

The following operation is similar to the operation explained in Fig. 9, and the 2M
When O820 is turned off, the npn) transistor is also turned off and the operation of the precharge circuit is stopped.

Next, when the terminal 31 becomes 1H" level, 0MO823
is turned off, and the charging voltage of the capacitor 25 becomes a voltage lower than the precharge voltage by ΔV of equation (3) due to feedthrough. In this state, the operating point of the DC differential amplifier is in the linear region and high gain detection is possible.

In this state, when the word line 2' is selected and reaches the 1H# level, the nMO 860 is turned on and the precharge voltage of the sense line 1 is discharged. This discharge voltage change is the capacitor 2
5, the output voltage of the DC differential amplifier increases and the signal at the output terminal 25 changes from H'' to L''.

This configuration has the advantage that a precharge circuit, a control circuit that generates a voltage slightly lower than the precharge voltage, and a sense circuit can be used in common for a plurality of sense lines.

Figure 10 is a diagram showing the basic configuration of the 'jj44 embodiment of the present invention, in which 1 is a sense line, 2 is a precharge circuit for precharging the sense line, and 3 is a voltage slightly different from the output voltage of the precharge circuit. A control circuit that generates a low voltage a, 4 a sense circuit that detects the state of the sense line 1, and 5 a control signal input terminal that determines the timing to stop precharging or latch the output signal of the sense circuit 4. , 6 is a control circuit that generates a signal to stop precharging from the output signal of the sense circuit 4 and the control signal from the terminal 5.

In this configuration as well, the voltage generating means is provided only in the precharge circuit 2, and the two input voltages (a and the voltage of the sense line 1) of the sense circuit 40 are determined based on this output voltage. Therefore, since the voltage relationship (size relationship) of each part is determined from one voltage source, the configuration is such that operational problems are unlikely to occur. .

FIG. 11 shows the configuration of the precharge circuit.

In FIG. 11(a), 100 is a power supply anode, and 20 is a p-channel MO whose source end is connected to the power supply anode 100.
S transistor, 21 connects the collector to the power supply anode end 100, and the paste end to the drain end of 9MO820 npn) transistor, 522 connects the drain/end to npn)
Connect to the emitter end of transistor 21, and connect the gate end to 9M
Connect the gate end of O820 and the source end to the power supply cathode end 1.
n-channel h connected to 01, 10S) transistor, 2
3- is a transistor whose drain end is connected to the drain end of the mouth MO822, and the source end is connected to the gate end of the 0MO822 → (n channel MO8) transistor, 24 is a signal input end connected to the gate end of the nMO823, and 25 is one end connected to the gate end of the MO822. Mouth MO852
26 is an output terminal connected to the drain end of the MO 822.

The operation of this configuration is as follows.

The current I flowing through the 9MO820 is expressed as. Here, βOprβ, are each 9MO
represents the channel conductance constant and dimension ratio (channel width/channel length) of 820, where Va is the gate voltage and V
* b p is the threshold voltage.

(Since the current of 1-type becomes the base current of the pn transistor, the emitter current 1. is L*=(1+hrg)Ip=hyclp-(2).Here, hrffi is the DC amplification factor of the npro transistor It is.

On the other hand, the current flowing through 0MO8522 is 1. It is expressed as d. Here, βo, , β represent the channel conductance constant and size ratio of 0MO8522, respectively, and Vtha
is the threshold voltage.

Now, when @H# level is applied to terminal 24 (the current of 2-pin type is divided into 0MO8522 and 1MO824,
The current flowing through MO824 is 9MO820, 0MO85
Since the gate of 22 has high impedance, capacitor 25
and charges the capacitor 25. At this time mouth MO8
When the MO824 is turned off when the voltage at the drain and source ends of the 24 is equal, the current in equation (2) becomes 0M.
Flows only into O8522.

In this state, equation (2) and αω equation are equal, so Jlr
z·Ip=−βQa′β. (Vo Vth-)""'
Q61hF11'βop'βp (Va Vcc V-
hp)”=βo, Hβ−(Vo Vth, )”・
... (Iη ...α樟) Here, if it is set, Vs++++=Vlbp. Vo at this time is the charging voltage of the capacitor 25 and is equal to the terminal voltage of the output terminal 26.

Therefore, the configuration of FIG. 11(a) can create the vl,=V0wtO point with the inverted transfer characteristic shown in FIG. 11(b). 20 in Figure 11(a). 21.52
2 constitutes an inverting amplifier circuit, and by turning on nMO824, the highest gain point of the inverting amplifier circuit;
That is, the point V 1m =Lwt 0 can be easily created.

In the precharge circuit with the configuration shown in FIG. 11(a), the output voltage is one half of the power supply voltage, so if the output terminal 26 is connected to the sense line, the sense line can be precharged to one half of the power supply voltage. Become.

Furthermore, the configuration shown in FIG. 11(a) is effective when simultaneously precharging a plurality of sense lines to one half of the power supply voltage with one configuration. FIG. 12 shows an example of its configuration.

In Figure 12, 100.20 to 25,522 are the first
1 shows a configuration similar to that shown in FIG. 1(a). 526 is an n-channel MOS transistor whose drain end is connected to the drain end of I) MO820 and whose source end is connected to the power supply cathode end 101, and 527 is a control signal input terminal connected to the gate end of 0MO8526. 211 is an npn) transistor whose collector end is connected to the power source anode 100 and whose base end is connected to the drain end of 9MO820; tI is a sense line connected to the emitter end of the npn) transistor 211; C;
+4 is the load capacitance attached to the sense line, similarly, 212.21
j respectively connect the collector end to the power supply anode end 100,
npn connecting the base end to the drain end of 9MO820
) transistors, t2゜1, are the second and jth sense lines, Ct2, respectively.

CLJ is the load capacitance attached to the second and jth sense lines, respectively.

When 1MO823 is on and 1MO826 is off (7),
The capacitor 25 is charged to a voltage determined by equations 01 and 9. At this time, n p n ) is at a voltage higher than the base voltage Vg of the transistor 21 by VBE.

VB =Vo+Vag --@ npn transistor 21, 211, 212. ...21
Since the bases of npn transistors 211, 212, and 21j are connected to each other, the base voltages of the npn transistors 211, 212, and 21j are also expressed by the Q equation. Therefore, each sense line t, -t, 0 load capacitance CLl''-Ct, j'b (Equation 11, Qv expression) will be charged to the voltage expressed.

The opening MO8526 is np when stopping the precharge operation.
Transistor 21, 211. . . 21j is cut off, and the storage time of each transistor during off-time is reduced.

By precharging with the configuration shown in FIG. 12, variations in the precharge voltage of each sense line are small, and a high-speed precharge circuit is possible.

FIG. 13 shows the sense circuit 4 of this embodiment.

In the figure, 1 is the sense line, 100 is the power supply anode, 40
is a p-channel M whose north end connects to the power supply anode end 100
O8I - transistor, 41 connects the source end to the power anode end 10
p-channel MO8) transistor with its gate end and drain end connected to pMO8400 gate end, 42
Connect the drain end to the drain end of 1) MO840,
An n-channel MOS transistor whose gate end is connected to the sense line 1, 43 is an n-channel MOS transistor whose drain end is connected to the drain end of 9MO841, and whose source end is connected to the source end of 0MO842, and 44 is an n-channel MOS transistor whose drain end is connected to the drain end of 9MO841.
Terminal 3 gives the gate voltage, 45 connects the drain end to 0M
An n-channel MOS transistor connected to the source end of O842 and the source end connected to the power supply cathode end, 46 is 0MO
This is the terminal for applying the gate voltage of the 845, which constitutes a DC differential amplifier. That is, the drain voltages of the 0MOs 842 and 43 change in response to the differential voltage between the sense line 1 and the terminal 44, and the drain voltages of the 0MOs 842 and 43 change.

0MO845 is a constant current circuit of a differential amplifier, and a constant current I0 of the following formula flows depending on the voltage at the terminal 46.

Here, β. 1. β is the channel conductance constant and size ratio (channel width/channel length) of 0MO845, V46 is the voltage at the terminal 46, and V Iha is the threshold voltage.

As shown in the figure, if the drain currents of <0 MO842 and 43 are I oB and I O43, respectively, 1° in equation (4) is ■. = IO42+IO43 (5).

Also) I D421 I oss is expressed as. Here, βOa + β4Z + β43 are the channel conductance constant of 1MO8 and 1MO8, respectively.
Dimension ratio of 842 (channel width/channel length), 0MO8
43 dimension ratio (channel width/channel length), V+ is the voltage of the sense line, v44 is the voltage of terminal 44, ■, is 1MO8
The voltages at the source terminals of 42 and 0 MO843 and the drain terminal of 1 MO845, V tha are threshold voltages.

Generally speaking, when configuring a differential amplifier stage from equation (6), 4, 1MO842 and 0M
Since the size ratio of O843 is the same, in the ae formula, β42
=β43=β, the equation (C) becomes as follows. Here, VT/
V7 true ΣF is a constant.

Therefore, the difference voltage between the sense line voltage and the voltage at the terminal 44 changes in the same manner as shown in FIG. 7, and in a signal range where there is a difference voltage, it operates as a linear amplifier. The output voltage in this signal range (
The drain voltage of 1MO842, 43 varies depending on the differential voltage and its gain.

Next, the voltage gain G in this configuration is as follows.

Now calculate the gain using simple 9MO841 and 0MO843.

When the current (2) flowing through pM0841 and the current (2) flowing through nA40s43 are in the saturation region, they are as follows.

1, =-βop'βp (Vo Vcc V Ibp
)2-(9)1, =-βQ++'β. (V+-V-Vt
h-)2-Q1 Here, βOp+β, and βo,,β, are each 9MO8,! : Channel conductance constant and dimension ratio (channel width/channel length) of nMO8, Vo is drain end voltage of pMO841, vl is 0MO843
The gate voltage of , Vcc is the power supply anode terminal voltage, ■.

is the source end voltage of 0MO843, and VthplVsba is the threshold voltage of 9MO8 and 1MO8, respectively.

Assuming that equation (9) and equation 4 are equal, βop'βp (Vo −Vce−V tbp )”=
βoa'β-(VlaV-Vtha)'...αυ...The voltage gain Gv of a is dVo/dV+, so normally G is about 3 to 10 times smaller than that of a bipolar circuit. .

From the above, the drain current changes in accordance with the voltage difference between the sense line 1 and the terminal 44 [formula (A)], and the change in the drain end voltage of 9MO8 is obtained by the voltage gain G, Cm formula]. For example, when the voltage at the terminal 44 is set to a fixed voltage 44, the operation is as follows.

When the voltage of sense line 1 is slightly lower than V44, it becomes 1M.
The drain current I D42 of O842 decreases and becomes 1MO84
The drain voltage of 2 increases. On the other hand, since the drain current of 0MO843 increases by the difference in equation (5) as ID42 decreases, the drain voltage of 0MO843 decreases.

In order to speed up this operation, it is effective to place the operating point in the linear region of FIG. 7 and near vII where the highest gain can be obtained. Furthermore, it is effective to increase the speed by narrowing the width of the DC region and making the gradient steeper (increasing the gain) so that the difference voltage changes from the DC region to the saturation region with only a small amount.

However, as mentioned above, it is difficult to increase the gain of a differential amplifier configured with MOS transistors (to easily obtain G = 50 to 60 like a bipolar amplifier). Therefore,
Furthermore, it is used in conjunction with an AC amplifier to configure a sense circuit.

In FIG. 13, 547 is a capacitor whose one end is connected to the drain end of the 0MO843, 548 is a p-channel MOS transistor whose source end is connected to the power supply anode 100, and whose gate i is connected to the other end of the capacitor 547;
Connect the drain end to the drain end of 1) M08548, connect the gate end to the gate end of I) M08548,
n-channel MO whose source end is connected to the power supply cathode end 101
S transistor, 550, connects the drain end to 1MO8549
An n-channel MOS transistor 55 whose source end is connected to the gate end of the 1MO8549 and whose source end is connected to the drain end of the 1MO8549.
1 is a terminal that provides a control signal to the gate of 0MO8550,
552 is a p-channel MOS transistor whose source end is connected to the power source anode 100 and whose gate end is connected to the drain end of 1MO8549; 553 is a p-channel MOS transistor whose drain end is connected to 9MO85
Connect to the drain end of 52, and connect the gate end to 9MO8552.
8) An n-channel MO transistor whose source end is connected to the gate end of the transistor and whose source end is connected to the power supply cathode end 101;
This is an output terminal connected to the drain end of the 8553.

547 to 554 constitute AC amplifiers.

Capacitor 547 is a coupling capacitor that functions to remove direct current coupling.548 to 551 are circuits that apply self-bias to the 0MO8 inverter configuration, and feedback is applied by the on-resistance of 0MO8550, resulting in V 1a as shown in Figure 14.
== Self-bias is applied to the N'aatO point. V+ゎ=■ obtained by self-bias. The point (2) is one half of the power supply voltage and is the point with the highest gain in terms of configuration. Therefore, the output line width on the output side (drain end of 1MO8549) is
The logic amplitude is just enough to change the state of the inverter (made by the inverter). Moreover, the self-bias switch (nM
QS550) is off, once the direction of the human force amplitude is determined with respect to the operating point (■ (or [F] in Figure 8))
Since the output amplitude is amplified in the opposite direction, malfunctions and hunting are less likely to occur.

The gain in this configuration is also determined by the size ratio of 1MO8549 and I)MO8548, as in equation (7). That is, the gain is expressed as . β. 49. β948 is 1 each
Dimensional ratio of MO8549 and pMO854s (channel width/
channel length).

552 and 553 constitute an inverter, and the 9MO8552 and nMo555a of this inverter also have a certain gain. In other words, the transfer characteristic of the inverter is
This is because it has a voltage gain as an amplifier as shown in Figure 4. However, the gate voltage of the inverter is 0MO85
When the output terminal 50 is on, it is approximately Vcc/2, so the output terminal 54 must be able to obtain the logic amplitude to the next stage. In other words, the voltage gain (specifically, the dimensions of 0MO8553 and 9MO8552) is adjusted so that when the gate voltage is at Vcc/2, the output terminal changes to "H" level, and when it becomes even slightly higher than Vcc/2, it changes to "L" level. ratio) must be selected.

In the sense circuit having the above configuration, the overall voltage gain is G=G-.G&v-OB-Qij. GII indicates the gain of the inverter serving as a buffer.

If the configuration described above is used to configure one bit of the ROM of FIG. 10, the result will be as shown in FIG. 15.

Here, the same parts as those described in FIGS. 10 to 14 are designated by the same reference numerals.

The gate end of the 1MO843 of the sense circuit is connected to one end of the capacitor 25 of the precharge circuit. Further, the coupling capacitor 547 of the sense circuit is formed between the gate end of the MOS transistor and the diffusion layer connecting the drain end and the source end to utilize the gate capacitance of the MOS transistor. This is an effective method for improving area efficiency with respect to capacitance. Furthermore, two inverters 548, 549 and 552°5 constitute the AC amplifier of the sense circuit.
53 is a logic symbol and is abbreviated as inverter 400.
,500.

Reference numerals 60 to 63 constitute a control circuit for stopping precharging based on the output signal of the sense circuit and the control signal of the terminal 24. The function of this configuration is that the state change of sense line 1 is detected at high speed by the sense circuit, and the time required for precharging is reduced by precharging again before the voltage precharged to sense line 1 is not completely discharged. The goal is to shorten the time.

60 is a latch circuit connected to the output terminal of the inverter 500, 61 is an input terminal that provides a latch signal to the latch circuit 60, 62 is an output terminal of the latch circuit 60, and 63 is a pre-amplifier from the signal from the latch circuit and the signal from the terminal 24. This is a control circuit that controls whether to operate or stop the charge circuit.

The operation of the configurations 60 to 63 is such that when the terminal 24 is at the %%H" level, the control circuit uses this signal to set the b signal to the 'L" level and turns off the precharge circuit 0M08526. In this case, the precharge circuit performs a precharge operation. Next, when the terminal 24 changes to the ``L#'' level, this signal change causes the control circuit to change the b signal to the ``H'' level, turning on the f1MO826. This stops the shi recharge operation.

When this change is established in the latch circuit 60, the control circuit sets the b signal to the "L" level and performs the precharging operation again before the voltage precharged to the sense line l is completely discharged. Operation speed can be increased.

2I is the decoder (the i-th word line selected by
30 is an n-channel MO8) transistor whose drain end is connected to the sense line 1, whose gate end is connected to the word #J 21 , and whose source end is grounded, and is the coupling element described in FIG. 1.

The operation shown in FIG. 15 will be explained in detail.

When the terminal 24 becomes H" level, the precharge circuit operates, and the sense line 1 is activated by the npn transistors 21 and 211.
is charged. At this time, the capacitor 25 is also connected to the sense line 1.
is charged to a voltage equal to the charging voltage of . On the other hand, the sense circuit nhioss.

In the ON state, the operating point is self-biased to 1/2 of the power supply voltage.

Next, when the terminal 24 becomes "L" level, the precharging operation is stopped and at the same time, the charging voltage of the capacitor 25 becomes a voltage lower than the precharging voltage by ΔV of equation (3) due to feedthrough. In this state, word line 2I
is selected and attains the ``H'' level, the gate MOf 930 is turned on and the precharge voltage of the sense line 1 is discharged.

When the voltage becomes lower than the voltage of this discharge ML voltage change capacitor 25, the voltage at the 0 point of the DC differential amplifier decreases and the inverter 5
The output voltage of 00 also decreases. This voltage change is latched by the latch circuit 60 with the signal at the terminal 61, and at the same time the control circuit 60
Precharging is started again by the b signal of 3.

If there is no 0MO 830, the precharge voltage of the sense line 1 will not be discharged even if the word line 2I is selected, and the output signal of the inverter 500 will not change. The latch circuit latches information whose state does not change, but the control circuit 63
The b signal remains at the @-LH level. When the signal at terminal 24 becomes ``H'' level again, the precharge circuit enters the precharge operation, but since the precharge voltage on sense line 1 has not been discharged, the time to precharge to 1/2 of the power supply voltage is short. .

According to the fourth embodiment of the present invention, it is possible to create a voltage slightly lower than the voltage before switching by using the feed-through error voltage that occurs during switching of (1) MOS transistors, so a sense circuit using this can be used. ) The speed of reading the LOM can be increased.

(2) A high-speed precharge circuit is created by self-biasing an inverter that combines bipolar transistors and MOS transistors. (3) A comparison voltage for the sense circuit is created based on the voltage of the precharge circuit. Therefore, the magnitude relationship of potentials is uniformly determined.

(4) High gain is achieved by configuring the sense circuit with a DC differential amplifier and a current amplifier to increase the voltage gain.

A high-speed sense circuit can be constructed.

A fifth embodiment of the present invention is shown in FIG.

In Fig. 16, the feedthrough error blood pressure is further reduced, and the voltage difference with the sense line is made very small. It's where it's set up. As mentioned earlier, the feedthrough error voltage is MO
Although this is unavoidable when using an s transistor, it can be foreseen in terms of design. By changing ΔV from toLw to 1H# level, ΔV in equation (3) can be obtained. Here, C230fd n MO
This is the overlap capacitance between the gate, drain, and source of 5230. Journal of 5solid 5tate
According to circujts, it has been reported that the voltage of equation (2) is about 10 mV, and a very small differential voltage can be created compared to the precharge voltage.

Therefore, according to this embodiment, the voltage difference between the DC differential amplifiers of the sense circuit can be reduced, resulting in an effect that the speed can be further increased.

FIG. 17 shows a sixth embodiment of the present invention, which differs from FIG. 15 in that the bipolar transistors of the precharge circuit are Darlington-connected. According to this embodiment, the performance of precharging the sense line is affected by the square of hFE, so there is an effect that it is possible to cope with further speeding up of the precharging operation and larger capacity.

Incidentally, the present invention is applicable to ILs such as the above-mentioned first to sixth embodiments.
Not limited to OM, 1i1. It can also be applied to AM.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a semiconductor memory device that can detect changes in a sense line at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of the ROM, and FIG. 2 is a diagram showing the configuration of the ROM.
3 is an example of the precharge circuit used in the first embodiment of the present invention, FIG. 4 is a diagram explaining the feed-through operation, and FIG. 5 is a block diagram showing the configuration of the first embodiment of the present invention. FIG. 6 is a diagram showing the configuration of a ROM for one bit of the sense line according to the first embodiment of the present invention, and FIG. 7 is a diagram showing the transfer characteristics of a DC differential amplifier. The figure shown in FIG. 8 is a second embodiment of the present invention.
(, OM fJ configuration, FIG. 9 is a diagram showing a configuration in which a precharge circuit, a control circuit, and a sense circuit are commonly used for a plurality of sense lines according to the third embodiment of the present invention.
FIG. 0 is a block diagram showing the configuration of the fourth embodiment of the present invention,
FIG. 11 is an example of a precharge circuit used in the fourth embodiment of the present invention, FIG. 12 is a diagram showing a configuration for precharging a plurality of sense lines, and FIG. 13 is a diagram showing a configuration for precharging a plurality of sense lines. FIG. 14 is a diagram showing the configuration of an example sense circuit. FIG. 14 is a diagram for explaining the amplification characteristics of an AC amplifier. FIG. 15 is a diagram showing the configuration for one bit of a sense line of a ROM according to a fourth embodiment of the present invention. 16 is a diagram showing the ROM configuration of a method for further reducing the feed-through error voltage according to the fifth embodiment of the present invention, and FIG. 17 is a diagram showing the precharge speed according to the sixth embodiment of the present invention. It is a figure which shows the structure which further speeds up. 2... Precharge circuit, 3... Control circuit, 4...
・Sen 10 Y20 131 fu #L) ¥l-7-DI S+w V 75m 40 Y7 Tsuri 1 force heka ton tile (Vt -V25) Figure Y/Ro diagram

Claims (1)

[Claims] 1. A semiconductor memory device equipped with a sense circuit having a differential amplifier, comprising a control circuit that generates from one voltage another voltage lower than the one voltage, A semiconductor memory device characterized in that the voltage and the other voltage are input to the differential amplifier. 2. The semiconductor memory device according to claim 1, wherein the one voltage is a precharge voltage. 3. The semiconductor memory device according to claim 1, wherein the control circuit that generates the other voltage lower than the one voltage from the one voltage utilizes field-through of a MOS transistor. .