JPS6016143B2 - Method for determining signal transmission status in mobile communications - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for reliably determining a signal transmission state in mobile communication such as a car telephone.

In the automobile radio system, which is a type of mobile communication, digital signals for control are sent out as necessary to communication channels for voice transmission.

In this case, during the transmission of control digital signals, it is necessary to close the communication path to the caller to avoid malfunctions or interference with the caller due to voice. Assume now that the control digital signal consists of a single block code as shown in FIG.

In this case, the block code length is predetermined, and therefore, when the start code preceding the block code is detected, it can be determined that a digital signal equal to the block code length continues. However, when the same start code and block code are sent out consecutively to improve transmission reliability as shown in Figure 2, the number of subsequent digital signals varies depending on the position of the received block code, so it cannot be determined uniquely. . For example, when a start code is received at A in Figure 2, the number of subsequent signals is (2 10 circles) (enemy: start code length, n: pu.tsuku code length), and when a start code is received at B. In this case, it becomes (Kijuyo). As a countermeasure for this,
One possible method is to add a stop code after the last block code.

However, in that case, if the detection of the stop code fails, it may become impossible to restore the communication path. In particular, in mobile communications such as car telephone systems, it is necessary to take into account that there is a high rate of failure in stop code detection in environments where deep and severe fading occurs as the car travels. The present invention has been made in view of the problems of the conventional methods described above, and its purpose is to provide a method that can reliably determine the signal transmission state even under the severe fading environment unique to mobile communications. There is a particular thing.

The details of the present invention will be explained below with reference to Examples.

FIG. 3 is a block diagram of the apparatus used to carry out the method of the invention, in which 1 is an input terminal, 2 is a receiver, 3 is a low-pass filter, 4 is a clock circuit, and 5 is a full-wave rectifier circuit. ,
6 is a comparison circuit, 7 is a delay flip/flop, 8 is an AND gate, 9 is a count/determination circuit, and 10 is a determination result output terminal. FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, in which a shows a state in which a control digital signal is being sent out, and b shows a state in which this control digital signal is not sent out.

The operation of the apparatus shown in FIG. 3 will be described below with reference to the waveform diagram shown in FIG. 4. Input terminal 1' in FIG. 3 receives a radio frequency signal, for example, a signal obtained by frequency-shifting a carrier of about 80 NM with a control digital signal of about several hundred Hz, from an antenna (not shown). This is detected by the receiver 2.

This detected output is supplied to a clock circuit 4 and a full-wave rectifier circuit 5 via a low-pass filter 3. Assuming that the control digital signal is currently being sent, the output of the low-pass filter 5 will have a waveform as illustrated by 1 in FIG. 4a. That is, as an example, when the digital signal is "1", it is 10 V volts, and when the digital signal is "0", it is -V volts. This signal is full-wave rectified by the full-wave rectifier circuit 5, resulting in a waveform as illustrated in FIG. , is supplied to the input terminal of the flop 7. On the other hand, the output of the low-pass filter 3 is also supplied to a clock circuit 4, and a clock synchronized with the digital signal is regenerated as shown in FIG. Ru.

As a result, the delay flip-flop 7 outputs a signal with a waveform as illustrated in FIG.
is supplied to one input terminal of the On the other hand, the other input terminal of the AND gate 8 is supplied with a clock signal from the clock circuit 4 . As a result, AND gate 8 generates an AND output pulse illustrated in FIG. 4 a6. In an ideal noise-free environment, this band output pulse would be equal to the number of clock pulses, which is equal to the number of clock pulses.
The determination circuit 9 counts mT time (m: positive integer value, 1/T: frequency of clock pulse). If this count value is a predetermined value, for example, 1 to 2 mT or more, a determination that the sending of the control digital signal is continuing is outputted to the determination result output terminal 10. As a specific example, if the signal transmission speed ratio is 300 b/s and the total bit length of the control signal is 40 bits, it is sufficient to set 1/T; 60 m x 1, m = 10. Increasing m increases accuracy, but has the drawback of increasing the determination time. Also, if m is reduced by 4, the judgment time will be shortened, but there is a possibility that a judgment error will occur.
It is appropriate that m be approximately the length of the start bit of the control signal. On the other hand, when the transmission of the control digital signal is stopped, the output waveform of the low-pass filter 3 becomes only a low-level noise component as illustrated in FIG. The rectified waveform becomes a low-level noise output as illustrated in b2 of the same figure, and the output waveform of the comparator circuit 6, which is further shaped, becomes an extremely discrete waveform as shown in b3 of the same figure.

This results in a delay flip-flop 7 and an AND gate 8
The output waveforms of are extremely sparse pulse waveforms as illustrated by b5 and b6 in the figure, respectively. Note that b4 in FIG. 4 shows the output waveform of the clock circuit 4. Therefore, the count value in the counting/determination circuit 9 does not reach the predetermined value, and a determination result indicating that the transmission of the control digital signal has been stopped is outputted to the output terminal 1. The case where the clock frequency of the clock circuit 4 is equal to the clock frequency of the control digital signal has been described above.

Although this makes it possible to detect digital signals even at low levels, this is undesirable in terms of accuracy. If there are no hardware restrictions, it is desirable for the clock frequency of the clock circuit 4 to be as high as possible from the viewpoint of improving accuracy, and preferably at least the clock frequency of the digital signal. A part of the configuration of a normal Enoki device can be used as is as the receiver 2, low-pass filter 3, and clock circuit 4 shown in FIG.

That is, in FIG. 3, the receiver 2, the low-pass filter 3, the clock circuit 4, and the comparison circuit 1 indicated by dots
1. A delay flip-flop 12 and a digital signal output terminal 13 constitute a decoder. Figure 5 is the third
This circuit is a more detailed example of the full-wave rectifier circuit 5, comparator circuit 6, delay flip-flop circuit 7, and AND gate 8 shown in the figure.

A comparison voltage input terminal 61 of the comparison circuit 6 is connected to a power source 63 via a variable resistor 62, and can be varied from 0.5 volts to 0.1 volts in 0.1 volt increments. Comparison circuit 6 and delay flip-flop circuit 7 are connected via impedance conversion circuit 14. As the three OP amplifiers 51, 64, and 71 in the figure, French PC151A was used. Further, a Zener diode 72 is connected to the input terminal of the delay flip-flop 7 for surge prevention. Figure 6 shows transmission speed = 300b
/s, clock pulse frequency 1/T=60 seconds, m=1
This is an example of actual measurement results for the circuits in FIGS. 3 and 5 in the case of
The vertical axis is the count, the normalized count counted by the judgment circuit 9, and the parameter is the comparison level of the wave shark circuit 6 (
0.1V to 0.5V). As is clear from FIG. 6, according to the present invention, the presence or absence of a digital signal can be accurately determined even when the received input is considerably small. In the embodiment described above, the output of the comparator circuit 6 is not directly supplied to one input terminal of the AND gate 8, but the delay flip-flop 7 is used. It is clear from FIG. 4 that V may be supplied to the input terminal of the .

Further, although a comparator circuit is used as the waveform shaping means, an amplifier or other waveform shaping circuit having an amplitude limiting function may be used.

As explained in detail above, the present invention performs level judgment on the shaped waveform of the detected output of a control digital signal using a clock faster than the transmission speed of the digital signal, and transmits the digital signal based on the count of the number of judgments. Since it is configured to determine the presence or absence of a

[Brief explanation of the drawing]

1 and 2 are configuration examples of digital signals for control, FIG. 3 is a block diagram of a device used to demonstrate the present invention, and FIG.
The figure is a waveform diagram for explaining the operation of Fig. 3, Fig. 5 is a diagram illustrating a part of Fig. 3 in more detail, and Fig. 6 shows the actual measurement results for the circuits of Figs. This is an example. 1...Input terminal, 2...Receiver, 3...Low pass filter, 4...K. 5... Full-wave rectifier circuit, 6... Comparison circuit,
7... Delay flip-flop, 8... Band gate, 9... Count/judgment circuit, 10... Judgment result output terminal. Figure 1 Figure 2 Figure 3 Figure 5 and 4 Figure 5

Claims (1)

[Claims] 1. In mobile communications where bipolar digital signals for control are sent as necessary to communication channels for voice transmission, the waveform after the detected output of the digital signal for control is passed through a resistance pass filter and a full-wave rectifier. The shaped waveform is subjected to a level determination of "1" or "0" using a clock having a transmission speed higher than the transmission speed of the control digital signal, and the number of determinations of the level "1" is counted over a predetermined period of time. A method for determining a signal transmission state in mobile communication, characterized in that the transmission of the control digital signal is determined to have been stopped by detecting that the count value is less than or equal to a predetermined value.