JPS6130821A - Squelch device - Google Patents

Abstract

PURPOSE:To prevent decoding of a interference wave signal by providing a noise squelch circuit operated while detecting an out-band component of a demodulation signal and a digitial squelch circuit operated while detecting a digital signal of a demodulation signal. CONSTITUTION:A radio wave from a transmitter 3 is received by a receiver 4 and a demodulated signal (a) from a demodulator 5 and a bit synchronizing signal formed automatically from the signal (a) are transmitted to a squelch device 12. A noise squelch circuit 8 extracts the out-band component in the signal (a) and when the level is higher than a reference value, the circuit outputs ON and when lower, the circuit outputs OFF. On the other hand, a digital squelch circuit 13 detects whether or not a digital signal is a correct form from a bit synchronizing signal (b) and the signal (a) from the demodulator 5. Then an output of the circuits 8 and 13 is inputted to an accessory circuit 14 to control a squelch gate 22.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a squelch device used to demodulate radio waves obtained by modulating digital signals.

The configuration of a conventional example and its problems Figure 1 shows the F of a digital signal including a conventional squelch device.
FIG. 2 is a block diagram of an M transmitter/receiver. In Figure 1, 1
is an encoder, and the encoder 1 converts an analog input signal such as voice into a digital signal such as PCM or delta modulation. A modulator 2 modulates a carrier signal with the digital signal. This modulated signal is sent out as a radio wave via the transmitter 3. The transmitted radio wave is received by a receiver 4, demodulated by a demodulator 5, converted into an analog signal by a decoder 6, and outputted via an amplifier 7.

Furthermore, when the reproduction quality deteriorates, the squelch circuit 8 is configured to cut off the reproduction signal and remove unnecessary noise. Note that, in addition to the demodulated signal a, the demodulator 5 sends out a bit synchronization signal S which serves as a clock signal. The squelch circuit 8 includes a high-pass filter 9. Amplitude detection circuit 10.
The comparator circuit 11 is composed of three parts.

Next, the operation of the above conventional squelch device will be explained.

In FIG. 1, when the condition of the wireless line deteriorates and the electric field strength at the input end of the wireless device becomes weak, the input end of the squelch circuit 8, that is, the out-of-band component (for example, ~20 K I-Iz ) increases. Therefore, the output of the high-pass filter 9 increases, and the output of the amplitude detection circuit 10 that detects it also increases. That's no good,
When the above value becomes larger than one reference value of the comparison circuit 11 (which is determined by the squelch level setting volume 12), the output of the comparison circuit 11 changes from the original OFF state to the ON state. The poor audio signal reproduced by the output (squelch output signal) of the comparison circuit 11 is cut off.

However, in the above conventional example, the electric field detection time constant is determined by the amplitude detection circuit 10, and the time constant is QdBμ■
It is very fast at 10 to 20m5 with input of
PK: It will become. Therefore, in the squelch circuit shown in Figure 1, ON or OFF of the squelch output signal is determined simply based on the amount of out-of-band components of the detected signal, so the radio waves generated from other general FM transmitters are If there is interference, the decoder detects it as a digital signal, and even though the input signal level is sufficient, there is a problem in that a noise-like signal is output as an analog output signal.

Purpose of the Invention The present invention solves the problems of the above-mentioned conventional example.
To provide an excellent squelch device that applies squelch if a predetermined digital signal format is not satisfied even if a radio wave generated from an M transmitter is input.

Structure of the Invention As is clear from the description of the above embodiments, the present invention consists of a noise squelch circuit that extracts out-of-band components of a demodulated signal and cancels the squelch when the out-of-band components are below a reference value, and a bit synchronization signal. A digital squelch circuit detects whether the digital signal of the demodulated signal is in the correct format using a window signal, and when the outputs of the noise squelch circuit and the digital squelch circuit meet predetermined conditions, the demodulated signal and bit synchronization signal are It is composed of an attached circuit that sends out the signal to the decoder, and if the radio waves generated from a general FM transmitter are input but do not satisfy the specified digital signal format, a digital squelch is applied. It has the advantage of being effective.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a digital signal FM transmitter/receiver including a squelch device according to an embodiment of the present invention, and FIG. 3 is a signal waveform diagram of the digital squelch circuit.

In FIG. 2, the same numbers 1 to 11 as in the conventional example are the same in the embodiment. The squelch device 12 according to one embodiment of the present invention is constructed using a conventional noise squelch circuit 8. Digital squelch circuit 13. and other auxiliary circuits 14.

In the digital squelch circuit 13, 15 is a transient detection circuit that extracts and outputs only the change points that change from "0→]" and "1→0" from the demodulated signal a, and 16 is a transient detection circuit that inputs a bit synchronization signal S. This is a window circuit that obtains a pulse C with a predetermined duty ratio.

17 passes the output signal of the transient detection circuit 15;
This gate circuit 17 disconnects the window circuit 1 by the signal of the up/down counter 18.
The output signal of the transient detection circuit 15 is allowed to pass only during the time period τ2 of 6. The amplifier down count circuit 18 counts the pulse of the gate circuit 17 a predetermined number of times for each "0" or "]" of the output signal of the window circuit 16, and when the pulse is equal to or greater than a predetermined value, it counts up and counts up a predetermined value. When it is less than the value, it counts down.

Then, once this up/down count circuit]8 has counted and amplified more than a predetermined number of stages, it stops counting at τ1 of the gate circuit 17, stops counting up any further, and instead uses the window circuit]6 to 12. The up/down counter 18 only counts down.

Attached circuit] 4, 19 is an up/down count circuit 18. and an AN inputting the output signal of the comparison circuit 11.
D circuit, 20 is a monostable multi which outputs a constant width pulse (approximately 250 msec) according to the output signal of the comparator circuit 11, 21 is an AND circuit 19. and an OR circuit that inputs the output signal of the monostable multi 2o. A squelch gate 22 receives the demodulated signal a and the bit synchronization signal from the demodulator 5, and controls the output signal of the OR circuit 21.

The decoder 6 inputs the demodulated signal a from the squelch gate 22 and the bit synchronization signal S and decodes it into an analog signal. The amplifier 7 amplifies this analog signal and outputs an analog output signal.

Next, the operation of the first embodiment described above will be explained. FIG. 4 is a diagram showing the determination time of the digital squelch circuit of this embodiment,
FIG. 5 is a signal waveform diagram of the squelch device of this embodiment.

2 to 5, in the transmitter, an analog input signal is converted into a digital signal by an encoder 1, modulated by a modulator 2, and sent out as a radio wave by a transmitter 3, as in the conventional example.

In the receiving device, this radio wave is received by a receiver 4 and demodulated by a demodulator 5. This demodulator 5 sends a digital demodulated signal a and a bit synchronization signal automatically created from this demodulated signal a to a squelch device 12.

The noise squelch circuit 8 extracts out-of-band components (for example, 5 to 20 KHz) in the demodulated signal a with a high-pass filter 9, detects its level with an amplitude detection circuit 0, and a comparison circuit 11 sets the squelch level setting polyme 12. By comparing with the reference value set by K, squelch is turned on, 01”
Output. Here, if the input electric field of the receiver 4 is weak, noise components increase, so more signals pass through the high-pass filter 9, and the squelch becomes 0N (rlJ). Also,
On the other hand, when the input electric field of the receiver 4 is strong, the noise component is small and the squelch becomes 0FF ([OJ).

On the other hand, in the digital squelch circuit 13, the duty ratio of the bit synchronization signal of the demodulator 5 is changed by the window circuit 16 as shown in FIG. and sends it to the gate circuit 17. Further, the demodulated signal a of the demodulator 5 is sent to the transient circuit 15 for a plurality of periods (
7 times in Figure 3) and the change point ("0 → 1")
”.

"1→0") is extracted and sent as a transient signal d or e. Note that this transient signal d
is a case where the input level is above a predetermined value and a predetermined signal format, and the transient signal e is a case where the input level is below a predetermined value or a signal format other than the predetermined one.

The transient signal d first passes through the gate circuit 17 as it is, and since all the pulses of the transient signal d are included in τ1 of the window signal C in the up-down circuit 18, all seven pulses are amplified and counted.

Here, since the up/down count circuit 18 reaches the upper limit of counting, it sends a signal of "1" to the AND circuit 19. The up/down count circuit 18 also sends a transient signal d of τ1 of the window signal C to the gate circuit 17.
The passage of the transient signal d is prohibited, and the transient signal d is allowed to pass only for the time τ2, which is an element of the countdown. In this way, when the up/down count circuit 18 reaches the lower limit of counting, the output of the up/down circuit 8 becomes 10.
”, and the count is restarted from the beginning.

When the gate circuit 17 receives a transient signal e generated due to weak electric field input or interference, the amplifier down count circuit 18 counts up the noise ζ at the time τ1 of the window signal C. , τ2
Since the tsks and responses are counted down at the time of , the count does not reach the upper limit and the output remains ``0''.

Note that the determination time of this digital filter 13 depends on the input electric field to the receiver 4, and changes as shown in FIG.

In this way, the outputs of the digital squelch circuit 13 and the noise squelch circuit 8 are input to the attached circuit 14. Here, the operation of the attached circuit 14 when an interference wave and a desired wave are input to the receiver 4 as shown in FIG. 4 will be explained.

Here, when a radio wave with a reception input electric field strength of a certain value or more is received, the output of the noise squelch 8 becomes "1", and the output of the mono-staple multi-circuit 20 is controlled for the time required for digital squelch determination (approximately 2soms). ) rlJ state, and the output of the OR circuit 21 also becomes a "1" state, and is connected to the squelch gate 22. During this time, the digital squelch circuit 13 judges whether it is a desired wave or not. If the input signal is an interference wave at this time, the output f of the digital squelch circuit 13 is in the state of "0", and the AND circuit 19
Output 1 becomes rOJ, and monostable multi-circuit 2
At the same time that the output of 0 becomes rOJ, the output J of the OR circuit 21 becomes "0", and the squelch gate 22 is cut off.

Next, when the input wave is a desired radio wave (desired wave), the output f of the digital squelch circuit 13 becomes "-1",
Since the output g of the noise squelch circuit 8 is also [1], A
Even if the output 1 of the ND circuit 19 becomes "1" and the output 1 of the monostable multi-circuit 20 becomes "0", the output J of the OR circuit 21 continues to maintain the state of "1", and the squelch gate circuit 22 The demodulated signal a and the bit synchronization signal can continue to be sent to the decoder 6 by remaining connected.

When the reception input decreases, the output g of the noise squelch circuit 8
quickly becomes 10, and the output 1 of the AND circuit 19 becomes 0.
”. In addition, since the output of the monostable multi-circuit 20 is also "0", the squelch gate circuit 22
The demodulated signal a and the bit synchronization signal are cut off.

In this embodiment, the squelch gates 1 and 22 are controlled by a noise squelch circuit 8 that can quickly respond to changes in the received input.
Since the signal is connected and disconnected, it is possible to quickly cut off the noise caused by cutting off the beginning of the voice or a drop in reception input, and the digital squelch circuit 13 distinguishes between interference waves and desired waves.
This has the advantage of preventing decoding of interference signals.

In this embodiment, bit reproduction quality is used as a means for determining the reproduction quality of a digital signal, but by inserting a specific pattern signal into the tintal signal width and measuring the reproduction probability of the specific pattern signal, It may also be used as means for determining the reproduction quality of a digital signal, and such means is also a type of digital squelch.

Effects of the Invention As is clear from the description of the above embodiments, the present invention is made from a noise squelch circuit that extracts out-of-band components of a demodulated signal and cancels the squelch when the out-of-band components are below a reference value, and a bit synchronization signal. A digital squelch circuit detects whether the digital signal of the demodulated signal is in the correct format using a window signal, and when the outputs of the noise squelch circuit and the squelch circuit meet predetermined conditions, the demodulated signal and bit synchronization signal are decoded. Since it is constructed with an auxiliary circuit that sends out signals to the receiver, it has the effect of applying squelch even if the radio waves generated from a general FM transmitter are input but do not satisfy a predetermined digital signal format.

[Brief explanation of the drawing]

Figure 1 shows the F of a digital signal including a conventional squelch device.
FIG. 2 is a block diagram of an FM transmitting/receiving device for digital signals including a squelch device according to an embodiment of the present invention. FIG. 3 is a signal waveform diagram of the digital squelch circuit of this embodiment. The figure shows the determination time of the digital squelch circuit of this embodiment, and FIG. 5 is a signal waveform diagram of the squelch device of this embodiment. 8...Noise squelch circuit, 9.High-pass filter, 10
Amplitude detection circuit, 11. Comparison circuit, 13... Digital squelch circuit, 14. Attached circuit, 15. Transient detection circuit, 16. Window circuit, 17. Gate circuit, 18 Up-down/count circuit, 19-AND circuit, 20 Mono staple. Multi, 210R circuit, 22
Squelch gate, a. demodulation signal, l). bit synchronization signal.

Claims (1)

[Claims] A noise squelch circuit extracts out-of-band components of the demodulated signal and cancels the squelch when the content is below a reference value, and a window signal created from the bit synchronization signal is used to check whether the digital signal of the demodulated signal is in the correct format. A squelch device comprising a digital squelch circuit for detection and an auxiliary circuit for sending a demodulation signal and a bit synchronization signal to a decoder when the outputs of the noise squelch circuit and the digital squelch circuit satisfy predetermined conditions.