JPS60160659A - Solid-state image pickup device - Google Patents
Solid-state image pickup deviceInfo
- Publication number
- JPS60160659A JPS60160659A JP59015186A JP1518684A JPS60160659A JP S60160659 A JPS60160659 A JP S60160659A JP 59015186 A JP59015186 A JP 59015186A JP 1518684 A JP1518684 A JP 1518684A JP S60160659 A JPS60160659 A JP S60160659A
- Authority
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- Japan
- Prior art keywords
- base body
- output circuit
- signal output
- substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000003384 imaging method Methods 0.000 claims description 15
- 230000003287 optical effect Effects 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76816—Output structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は・固体撮像装置に関し、特に光゛１換素子と光
信号電荷を転送するための電荷結合素子（以下ＣＯＤと
記す）からなる電荷結合型固体撮像装置の信号出力回路
に関するものである◎〔発明の背景〕
電、荷拮合型固体撮像装置は、例えば垂直方向に５００
１１、！ｉｔ、水平方向に８００〜１０００ｉ１１ｉ１
を配列した光電変換素子のマトリックスと７それらの光
電変換素子に蓄積された光信号電荷を信号出力回路に増
出すだめの垂直ＣＯＤシフトレジスタ群と水平ＣＣＤシ
フトレジスタ群から構成される。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a solid-state imaging device, and in particular, a charge-coupled device consisting of a photoconverter and a charge-coupled device (hereinafter referred to as COD) for transferring optical signal charges. This relates to a signal output circuit for a type solid-state imaging device. [Background of the Invention] A charge-balanced solid-state imaging device has, for example, 500 pixels in the vertical direction.
11,! it, horizontally 800-1000i11i1
It consists of a matrix of photoelectric conversion elements arranged in a matrix, and a group of vertical COD shift registers and a group of horizontal CCD shift registers for increasing the optical signal charges accumulated in these photoelectric conversion elements to a signal output circuit.
第１図は、従来の電荷結合型固体撮像装置の出力回路の
断面構造図である。FIG. 1 is a cross-sectional structural diagram of an output circuit of a conventional charge-coupled solid-state imaging device.
第１図において、１はｎ型の第１基体２２は第１基体１
内に形成されたｐ型の第２基体、３はｎ型半導体のＣＯ
Ｄ転送チャネル、４はｎ型半導体のＣＣＤＣＤ刃出カド
レインる。破、線で示す５は！般像素子の信号出力回路
を構成するＭＯＳＦＥＴであり、そのゲート６は上記Ｃ
ＣＤＣＤ刃出カドレイン接続されている。また２このＭ
ＯＳＦＥＴ５のドレイン７は電源１ｏに、ソース８は負
荷抵抗９の一端に接続されている。なお、１１は、第１
基体ｌにバイアス尾圧を加えるための電源である。In FIG. 1, 1 is an n-type first substrate 22 is a first substrate 1.
3 is an n-type semiconductor CO
D transfer channel, 4, is a CCDCD blade drain of an n-type semiconductor. Broken, the 5 indicated by the line is! This is a MOSFET that constitutes the signal output circuit of the general image element, and its gate 6 is connected to the above C
CDCD blade drain is connected. Also 2 this M
The drain 7 of the OSFET 5 is connected to a power supply 1o, and the source 8 is connected to one end of a load resistor 9. Note that 11 is the first
This is a power source for applying bias tail pressure to the substrate l.
第２図は、第１図を回路図に表したものであり・第２図
中の１２．１３，１４，１５．１６はそれぞれ第１図に
おけるＭＯＳ Ｆ ＥＴ ５のゲート６゜ソース８．ド
レイン７、ドレイン７に電圧を加えるための電源１０．
負荷抵抗９に相当する。１７は・第２基体２に相当する
。信号はこの負荷抵抗９の両端子間の電圧として出力さ
れる。ところで。FIG. 2 is a circuit diagram of FIG. 1. 12.13, 14, 15.16 in FIG. 2 are the gate 6° source 8. Drain 7, power supply 10 for applying voltage to the drain 7.
Corresponds to load resistance 9. 17 corresponds to the second base body 2. A signal is output as a voltage between both terminals of this load resistor 9. by the way.
第２図に示す回路は・いわゆるソース・フォロア回路で
あり、そのゲインは、第１図に示す第２基体２に対する
ソース電圧Ｖｓの変化による閾値■ｔｈの変化（基板効
果）が十分に小さくて無視できるときには、近似的に次
式で表わされる。The circuit shown in FIG. 2 is a so-called source follower circuit, and its gain is such that the change in the threshold th (substrate effect) due to the change in the source voltage Vs with respect to the second substrate 2 shown in FIG. 1 is sufficiently small. When it can be ignored, it can be approximately expressed by the following equation.
几 Ｇ＝ □ （１） １／ｇｍ＋Ｒ ただし、ｇＩＩＩはＭＯＳＦＥＴのｇｍであり。几 G= □ (1) 1/gm+R However, gIII is the gm of MOSFET.
Ｒｔｌ負荷抵抗１６の抵抗値である。This is the resistance value of the Rtl load resistor 16.
上式（１）において・特にＲが十分に大きいとき（Ｒ＞
＞ １／ｇ、１１）・ゲインＧはほぼ１になる。In the above formula (1), especially when R is sufficiently large (R>
> 1/g, 11) - Gain G is approximately 1.
しかし・実際のＭＯＳＦＥＴでは、上記基板効果は大き
くこれを無視することはできない。一般に基板効果は、
基板効果定数をＫ（通常Ｋ＞Ｏ）とするとき、閾値Ｖｔ
ｈの第２゛基体を基準とするソース電位Ｖ８の依存性は
次式で表わされる０Ｖｔｈ（Ｖｓ）＝Ｖｔｈｏ＋Ｋ（ハ
τ「Ｙｈ−４２石’）・・・・・・（２）
ただし、ＶｔｂｏはＶｓ＝０のときの閾値でありφＦは
フェルミレベル電位中０．６Ｖ
である。However, in an actual MOSFET, the substrate effect is large and cannot be ignored. Generally, the substrate effect is
When the substrate effect constant is K (usually K>O), the threshold value Vt
The dependence of the source potential V8 with respect to the second substrate of h is expressed by the following formula: 0Vth (Vs) = Vtho + K (τ ``Yh - 42 stones'') (2) However, Vtbo is the threshold value when Vs=0, and φF is 0.6V in the Fermi level potential.
このように・基板効果があると、閾値ｖｔｈの大きさは
、出力信号によりソース電位Ｖｓの変化に伴って変化し
・ソースフォロアのゲインＧの低下の原因となる。実際
に、この基板効果がある場合、第２図のソースフォロア
のゲインＧは＋１）式と異なり・次の式によって決まる
。In this way, when the substrate effect exists, the magnitude of the threshold value vth changes with the change in the source potential Vs due to the output signal, causing a decrease in the gain G of the source follower. Actually, when this substrate effect exists, the gain G of the source follower shown in FIG. 2 is determined by the following equation, which is different from the equation +1).
Ｇ″″ＧｏＸ□ ・・・・・・ （３）几＋Ｇ ｏ ／
ｇ ｍ
しかし、基板効果が大きいと（Ｋが大きい）、たとえＲ
を十分に大きくしても、ゲインＧは次式したがって・利
得は１以下の小さな値になる。G″″GoX□ ・・・・・・ (3) 几＋G o /
g m However, if the substrate effect is large (K is large), even R
Even if G is made sufficiently large, the gain G will be a small value of 1 or less.
例えば、ＭＯＳＦＥＴをデプレッション屋のＭＯ８で構
成したとき、基板効果定数には１〜２になるが、このと
きソース電圧Ｖｓを１■に設定すると。For example, when the MOSFET is configured with MO8 of a depression shop, the substrate effect constant will be 1 to 2, but if the source voltage Vs is set to 1.
ゲインＧは基板効果がない場合の約半分となり、出力電
圧が低下する。このため、後段回路の雑音によって、Ｓ
Ｎ比の劣化を招く。The gain G is approximately half of that without the substrate effect, and the output voltage decreases. Therefore, due to noise in the subsequent circuit, S
This causes deterioration of the N ratio.
本発明の目的は・このような従来の欠点を除去するため
、信号出力回路の利得を上げて、後段回路の雑音に対す
るＳＮ比の劣化が少ない固体撮像装置を提供することに
ある。An object of the present invention is to provide a solid-state imaging device in which the gain of the signal output circuit is increased and the S/N ratio is less degraded by noise in the subsequent circuit, in order to eliminate such conventional drawbacks.
上記目的を達成するために・本発明の固体撮像装置は、
第１の基体と、該第１の基体中に形成され、第１の基体
と異なる導電型を有する第２の基体を備え、該第２の基
体中に走査用シフトレジスタ群および該シフトレジスタ
群で読み出された光信号電荷を検出し、増幅するＭｏｓ
型トランジスタからなる信号出方回路を集積化した固体
撮像素子において、上記ＭＯ８型トランジスタを形成す
るための第２の基体を・上記走査用シフトレジスタ群等
を形成するための第２の基体と分離し・がり上記ＭＯ８
型トランジスタを形成テる第２の基体に・該トランジス
タのソース電極を接続することに特徴がある。In order to achieve the above object, the solid-state imaging device of the present invention includes:
a first base; a second base formed in the first base and having a conductivity type different from that of the first base; a scanning shift register group and a shift register group in the second base; Mos detects and amplifies the optical signal charge read out by
In a solid-state imaging device that integrates a signal output circuit consisting of MO8 type transistors, the second base body for forming the MO8 type transistors is separated from the second base body for forming the scanning shift register group, etc. MO8 above
The method is characterized in that the source electrode of the transistor is connected to the second substrate on which the transistor is formed.
以下・本発明の実施例を２図面により説明する・ｍ３図
は１本発明による固体撮像装置の信号出力回路部の断面
構造図であり、第４図は第３図を回路図に書き表わした
ものである。Embodiments of the present invention will be explained below with reference to two drawings. Figure 1 is a cross-sectional structural diagram of the signal output circuit section of the solid-state imaging device according to the present invention, and Figure 4 is a circuit diagram of Figure 3. It is something.
第３図において・２ｏと２１は、第１図のＣＯＤ転送チ
ャンネル３とＣＣＤ部出方ドレイン４と同一の構造を備
え九ものである。また・２３，２４゜２５は、それぞれ
ＭＯ８ＦＥＴ２２のゲート、ドレイン、ソースである０
第３図の構造が、第１図の従来の構造と異なる点は２ｎ
型の第１基体１８内に形成されたｐ型の第２基体（第１
図の第２基体２に相当する）を・ＣＣＤ部の第２基体１
９と、信号出力回路部の第２基体２６に分離したこと、
およびＭＯ８ＦＥＴ２２のソース２５を信号出力回路部
の第２基体２６に接続したことである。この違いを回路
図で示すと、第２図の第２基体１７がアース電位に設定
されているのに対して、第４図の第２基体２７はソース
２８に接続されていることで表わされている。In FIG. 3, 2o and 21 have the same structure as the COD transfer channel 3 and the CCD section output drain 4 in FIG.・23, 24° 25 are the gate, drain, and source of the MO8FET 22, respectively. The difference between the structure in FIG. 3 and the conventional structure in FIG. 1 is 2n.
A p-type second substrate (first
・Second base 1 of the CCD section (corresponding to the second base 2 in the figure)
9, and separation into the second base 26 of the signal output circuit section;
and that the source 25 of the MO8FET 22 is connected to the second base 26 of the signal output circuit section. This difference is shown in a circuit diagram by the fact that the second base 17 in FIG. 2 is set to the ground potential, whereas the second base 27 in FIG. 4 is connected to the source 28. has been done.
本実施例の信号出力回路では、第２図の従来の回路と異
なり、ソース２８の電位の変化に伴なって第２基体２７
も同時に変化するため、ソース２８と第２基体２７０間
の電圧■８は常に一定（Ｖｓ＝０）になる。In the signal output circuit of this embodiment, unlike the conventional circuit shown in FIG.
2 also changes at the same time, so the voltage (2)8 between the source 28 and the second substrate 270 is always constant (Vs=0).
したがって・画成（２）において、Ｖ！＋＝０を代入す
ると、閾１直ｖｔｈは常に一定となり、ＭＯ８ＦＥＴ２
２はあたかも基板効果のないＭＯＳＦＥＴとして動作す
るため、画成（りでめられる理想的なゲインＧを得るこ
とができる。Therefore, in definition (2), V! If +=0 is substituted, the threshold 1 voltage vth will always be constant, and MO8FET2
2 operates as if it were a MOSFET with no substrate effect, so it is possible to obtain an ideal gain G that can be defined.
ｍ５図は、第３図において第１基体をｐ型にした場合の
信号出力回路部の断面構造図である。Figure m5 is a cross-sectional structural diagram of the signal output circuit section in the case where the first substrate in Figure 3 is made of p-type.
すなわち、第５図に示すように、第１基体１８′がｐ型
半導体、第２基体１９’、２６’がｎ型半導体、ＣＯＤ
転送チャンネル２０′とＣＣＤ部出カ出力イン２１′が
ｐ型半導体−ＭＯ８ＦＥＴ２２′のドレイン２４′とソ
ース２５′がｐ型半導体である場合にも、その動作は第
３図の場合と全く同じである。ＭＯ８ＦＥＴ２２’がｐ
ｎｐ）ランジスタとして動作し、ドレイン２４′に接続
される電源電圧の極性が逆向きになる点が異なるだけで
ある。That is, as shown in FIG. 5, the first substrate 18' is a p-type semiconductor, the second substrates 19' and 26' are n-type semiconductors, and COD
Even when the transfer channel 20' and the CCD output output input 21' are p-type semiconductors and the drain 24' and source 25' of the MO8FET 22' are p-type semiconductors, the operation is exactly the same as in the case of FIG. be. MO8FET22' is p
np) operates as a transistor, and the only difference is that the polarity of the power supply voltage connected to the drain 24' is reversed.
なお、第３図、第５図の実施例では、電荷結合型固体撮
像装置の信号出力回路部に適用される場合を述べたが・
光信号電荷を読み出す走査回路部の形式はＣＣＤ型に限
定されることなく・固体撮像装置の信号出力回路がＭＯ
ＳＦＥＴで構成されるソースフォロアであれば、すべて
のものに適用することができる。例えば・垂直読出し部
にＭＯ８型トランジスタスイッチを・また水平読出し部
にもＭＯＢ型トランジスタスイッチをそれぞれ用い。Although the embodiments shown in FIGS. 3 and 5 are applied to a signal output circuit section of a charge-coupled solid-state imaging device,
The format of the scanning circuit section that reads out the optical signal charge is not limited to the CCD type; the signal output circuit of the solid-state imaging device is MO.
It can be applied to any source follower made of SFET. For example, an MO8 type transistor switch is used in the vertical readout section, and an MOB type transistor switch is used in the horizontal readout section.
光電変換素子の光信号電荷を垂直読出し部のＭＯ８型ト
ランジスタスイッチにより垂直信号線に読出し、この垂
直出力線の光信号電荷を水平読出し部のＭＯ８型トラン
ジスタスイッチにより出力するような固体撮像装置にも
適用できる。It is also applicable to a solid-state imaging device in which the optical signal charge of the photoelectric conversion element is read out to a vertical signal line by an MO8 type transistor switch in a vertical readout section, and the optical signal charge on this vertical output line is outputted by an MO8 type transistor switch in a horizontal readout section. Applicable.
以上説明したように５本発明によれば、固体撮像装置の
信号出力回路部の第２基体をＣＣＤ部第２基体と分離し
・信号出力回路部第２基体とＭＯＳＦＥＴのソースを接
続したので、信号出力回路部の利得を大幅に向上させる
ことができ、外部回路の雑音に対するＳＮ比劣化の少な
い映像信号を得ることができる。As explained above, according to the present invention, the second base of the signal output circuit section of the solid-state imaging device is separated from the second base of the CCD section, and the second base of the signal output circuit section and the source of the MOSFET are connected. The gain of the signal output circuit section can be significantly improved, and a video signal with little deterioration in SN ratio due to external circuit noise can be obtained.
第１図は従来の電荷結合型固体撮像装置の出力回路部の
断面構造図・第２図は第１図の構造の等価回路図、第３
図は本発明の一実施例を示す電荷結合型固体撮像装置の
出力回路部の断面構造図。
第４図は第３図の構造の等価回路図・第５図は第３図の
構造における第１基体をｐ型半導体にした場合の変形例
断面図である。
１．１８．１８’・・・第１基体・２，１９．１９’。
２６．２６’・・・第２基体、３，２０．２０’・・・
ＣＯＤ転送チャンネル、４，２１．２１’・・・ＣＣＤ
ＣＤ刃出カドレイン、２２．２２’・・・Ｍ ０８ Ｆ
ＥＴのゲート、７，２４．２４’・・・ＭＯＳＦＥＴの
ドレイン、８，２５．２５’・・・ＭＯＳＦＥＴのソー
ス、１０．１０’・・・ＭＯＳＦＥＴのドレインに接続
する電源〇
ｆＪ １ ｍ
第 ３ ｎ
■ ４ 図Figure 1 is a cross-sectional structural diagram of the output circuit section of a conventional charge-coupled solid-state imaging device. Figure 2 is an equivalent circuit diagram of the structure in Figure 1.
The figure is a cross-sectional structural diagram of an output circuit section of a charge-coupled solid-state imaging device showing an embodiment of the present invention. 4 is an equivalent circuit diagram of the structure shown in FIG. 3, and FIG. 5 is a sectional view of a modification of the structure shown in FIG. 3 in which the first substrate is made of a p-type semiconductor. 1.18.18'...first base 2,19.19'. 26.26'...second base, 3,20.20'...
COD transfer channel, 4, 21.21'...CCD
CD blade length, 22.22'...M 08 F
Gate of ET, 7, 24.24'... Drain of MOSFET, 8, 25.25'... Source of MOSFET, 10.10'... Power supply connected to drain of MOSFET 〇fJ 1 m 3rd n ■ 4 Figure
Claims (1)
該第２の基体中に走査用回路および該走査用回路により
読み出された光信号電荷を増幅するＭＯ８型トランジス
タからなる信号出力回路を集積化した固体撮像素子にお
いて、上記ＭＯ８型トランジスタを形成するだめの第２
の基体を、上記走査用回路を形成するための第２の基体
と分離し、かつ上記ＭＯ８型トランジスタを形成する第
２の基体に、該ＭＯ８型トランジスタのソース電極を接
続することを特徴とする固体撮像素子。[Scope of Claims] 1. A first substrate; and a device formed in the first substrate. a second base having a conductivity type different from that of the first base;
In a solid-state imaging device in which a scanning circuit and a signal output circuit consisting of an MO8 transistor that amplifies optical signal charges read out by the scanning circuit are integrated in the second substrate, the MO8 transistor is formed. No. 2
The substrate is separated from the second substrate for forming the scanning circuit, and the source electrode of the MO8 transistor is connected to the second substrate for forming the MO8 transistor. Solid-state image sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59015186A JPS60160659A (en) | 1984-02-01 | 1984-02-01 | Solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59015186A JPS60160659A (en) | 1984-02-01 | 1984-02-01 | Solid-state image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60160659A true JPS60160659A (en) | 1985-08-22 |
Family
ID=11881798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59015186A Pending JPS60160659A (en) | 1984-02-01 | 1984-02-01 | Solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160659A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0605958A1 (en) * | 1992-12-28 | 1994-07-13 | Sharp Kabushiki Kaisha | Solid state imaging device having high-sensitivity and low-noise characteristics by reducing electrostatic capacity of interconnection |
-
1984
- 1984-02-01 JP JP59015186A patent/JPS60160659A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0605958A1 (en) * | 1992-12-28 | 1994-07-13 | Sharp Kabushiki Kaisha | Solid state imaging device having high-sensitivity and low-noise characteristics by reducing electrostatic capacity of interconnection |
| JPH06252374A (en) * | 1992-12-28 | 1994-09-09 | Sharp Corp | Solid-state image pickup device |
| US5357129A (en) * | 1992-12-28 | 1994-10-18 | Sharp Kabushiki Kaisha | Solid state imaging device having high-sensitivity and low-noise characteristics by reducing electrostatic capacity of interconnection |
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