JPS6015569A - Logical package diagnostic system - Google Patents

Abstract

PURPOSE:To make it possible to diagnose a logical package by dividing the titled diagnostic system into the diagnosis between parts and the diagnosis of parts alone, by adding scanning-in and scanning-out enabling logic to the pin of the parts of the logical package. CONSTITUTION:LSI31 is provided with a receiving FF36 freely performing scanning-in and a transmitting FF37 freely performing scanning-out other than a logical circuit part 32 and a scan control circuit 33. After ''1'' is scanned in all of FF36, 37, and the diagnosis of the circuit part 32 is performed by scanning out all of ''1'' or scanning out all of ''0'' after ''0'' is scanned in. In addition, when a test pattern is inputted to FF36, the circuit 33 is diagnosed by the comparison of the output of FF37 and an expected value. Further, the diagnosis between LSIs can be performed by the comparison of the scanning-out content of the receiving FF of the other LSI to which output for detecting the connection inferiority of FF37 is inputted through a connection IC and an expected value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Invention Lamp for Rio U] The present invention relates to a diagnostic method for a logic package composed of parts including large-scale logic.

[Background of the invention]

As the logical scale of a logic package increases due to the conversion of logic to LSI, it becomes difficult to create diagnostic data that covers the entire package logic, and it becomes difficult to create diagnostic data for the entire package logic. l
A method that performs logical division and diagnoses each division is widely talked about.

l, - Method of logically dividing and diagnosing all C flippuffs It is not easy to apply to general logic because of m1j reduction.

2. Physically dividing and diagnosing method P3+3 is a tester device that has a blow-pink function for all parts bins. This method uses blow pink to diagnose poor connections between parts and defective parts annual salary, but as the logical scale of the parts increases, there are problems with parts diagnosis 7JS and problems with the 10-pink technology.

[Purpose of the invention]

An object of the present invention is to provide a method for diagnosing a logical package by adding scan-in, scan-out + IJ ia Fa & JM to the component bin of a logical package, and dividing the diagnosis between parts and the diagnosis for each component.

[Summary of the invention]

By attaching flip-flop logic that can be scanned in and out of the above component bin inside or outside of the large-scale logic components that make up the logic package, constraints on the logic structure and the use of special tester equipment can be avoided. It is possible to perform a split diagnosis without any problems.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a logic schematic diagram of a logic module according to one embodiment of the present invention. In the figure, 1 is a logic blockage bin, 2 is an LSI including large-scale logic, 3 is an LSI bin, 4 is a reception flip-flop block corresponding to the input bin of the LSI, and 5 is a flip-flop block corresponding to the input bin of the LSI. The transmission flip-flop 6 is a flip-flop corresponding to the output bin of the LSI, the reception clock ζ 6 is a clock for the reception flip-flop 4, and the transmission clock 7 is a clock for the transmission flip-flop 5. The scan control signal 8, the package scan control circuit 9, the scan out signal 10, and the LSI scan control circuit 11 are as follows:
It performs writing (scan-in) and reading (scan-out) to the reception flip-flop and transmission flip-flop corresponding to the input and output bins of the LSI.

FIG. 2 is a gated version of the receive and transmit flip-flops and a symbolic diagram of the flip-flops.

FIG. 3 shows the peripheral logic and scan logic of the LSI input bin and output bin within the LSI.

There are 5 transmit flip-flops corresponding to the output bin 13 of the LSL, and 6 receive flip-flops corresponding to the input bin 15, and 6 receive clocks store information from the input bin 15 in the receive flip-flop 4. The transmission clock number 7 is for storing information from the transmission gate 14 in the transmission flip-flop. 20
Write (scan-in) to the transmitting flip-flop 5 and receiving flip-flop 4 by the address decoding circuit 21 and the scan-in control circuit 21 is to output the scan clock 18 after specifying the scan address 19 and the scan data 17. This is possible. Readout (scan out) by the address decoding circuit 20 and the scan out control circuit 22 is enabled by specifying the scan address 19.

A method for diagnosing SI is shown in FIG.

The LSIs 24, 25, and 26 are equipped with the transmitting and receiving flip-flops shown in FIG.
27 IC has a small logical scale and does not have transmitting and receiving flip-flops. 27 IC and 24 + 25
The diagnostic procedure between LSIs at t26 is shown below.

■) Turn off the transmit clock 7 and turn on the receive clock 6.

■) IC27 and LS for the transmitting flip-flop
Scan in data that allows detection of connection failures of I 24, 25, and 26.

III) Scan out the receiving flip-flop 30i and compare it with the expected value.

A method of diagnosing an LSI will be described using FIG.

The No. 31 LSI is equipped with the transmitting and receiving flipflops shown in FIG. Create test data for diagnosing the LSI31 at the unit level so that it satisfies the following conditions.

■) Diagnosis of logic circuit fI532 and scan circuit section 33
Create test data for each diagnosis.

■) The test data of the logic circuit section 32 is the reception clock 6.
, so that the test butter 7f is fed from the input bin of the LSI with the transmission clock 7 turned on.

■) Create a test pattern so that the input bin changes by only one bin when switching from test to test.

a) Diagnosis method of scan circuit section 33 ■) Turn off receive clock 6 and transmit clock.

(2) After performing an IK scan in all receiving flip-flops and transmitting flip-flops, scan out the flip-flops and test whether they are all 1s.

After scanning in 94 flip-flops of 1lI)ll), scan out and test whether they are all 0.

b) - Diagnosis method for the logic circuit section 32 ■) Turn off the reception clock 6 and turn on the transmission clock 7.

II) Scan in the logic value of the first test pattern of the test data for diagnosing the logic circuit unit 33 at the unit level of i, 5I32 into all the receiving flip-flops corresponding to the input bin of the LSI. 11) Into the LSI output bin All corresponding transmit flip-flops are scanned out and compared with the expected LSI output bin value of the test data.

II/) After the second test pattern, the logical value after the change is scanned into the receiving flip-flop corresponding only to the LSI manual bin that changed due to the switching of the test pattern.

v) Same as ni).

Vl) B) and V) are repeated at the final test turn-off T0 By implementing the present invention, r! Diagnosis of the a management package can be divided into diagnosis between the LSI and IC and diagnosis inside the LSI.

[The baby of invention]

According to the present invention, package diagnosis can be performed separately into diagnosis of large-scale cooking components and diagnosis of large-scale logic components. It is possible to use test data for diagnosis performed in 5J functions, and the creation of test data for diagnosing large-scale logic components does not require the logic inside the large-scale logic components, making test data creation easy. From the above, it can be seen that the computer processing time for creating test data for a logic package can be reduced to 115 times or less, and that test data of straw quality can be easily created.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention. Figure 2 is a schematic diagram of the logical logic of a flip-flop; Figure 3 is a schematic diagram of the circuit added to the input and output bins of the LSI; Figure 4 is a diagram of the logic of the LSI and IC. The connection relationship diagram, FIG. 5, is a diagram of the LSI bottom, embedment M, and chest. 1°...Logic package 2...LSI3...LS
I-bin 4...Reception flip-flop 5...Transmission flip-flop 6...Reception clock 7...Transmission clock 8...
Scan control signal 9... Packages control signal FAI circuit 10...
Scan out (i+9 11...LSI scan control circuit 12...flip flow rough" symbol diagram 13...L
SI output bin 14...Transmission gate 15...LSI
Manual power bin 16...Reception gate F...Scan data 18...Scan clock 19...Scan address 20...Address decode circuit 21...Scan-in immediate control circuit 22...Scan-out NIJ control (9) Route 1 Figure 2 jvJ2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A logical 7-dimensional cage consisting of one or more parts, with a flip-flop corresponding to each bin of parts;
6^ By combining the logic 115 of a specific plug-in bin of the management package, the contents of the above 71 node block are rewritten, the contents of the flip-flop are output to the logic package plug-in bin, and the logic value of the component bin is matched. A function is provided to output the contents of the flip-flop to the corresponding parts bin, and diagnosis of logical logic is performed by separating diagnosis between parts and diagnosis of annual salary of parts. Features a logical cage diagnosis method.