JPS60154360A - Device for compensating variance of time base - Google Patents

Abstract

PURPOSE:To lower the clock frequency of a CCD to reduce the CCD driving power for correction of a time base by lowering the frequency of an sound FM signal by a frequency converting circuit and a filter circuit and inputting this signal to the CCD. CONSTITUTION:The sound FM signal reproduced simultaneously with a video FM signal has the frequency lowered by a local oscillation frequency oscillating circuit 16, a frequency converting circuit 17 such as a mixing circuit or the like, an LPE18, etc. and is supplied to a CCD15. Because of input of this low frequency, clock pulses having a low frequency obtained by dividing the frequency of time base correcting clock pulses (c), which are supplied from a voltage control oscillator on a basis of comparison between a horizontal synchronizing signal separated from the video FM reproduced signal and a standard horizontal synchronizing signal, by a frequency divider 14 can be used as clock pulses which drive the CCD15 for correction of the time base, and the CCD driving power for correction of the time base is reduced because clock pulses having the low frequency are used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a time axis fluctuation correction device for a video disc player or the like.

[Background of the invention]

In players of video discs that contain audio information (without a reference signal) and video information (with a reference signal), the time axes of the reproduced audio FM signal and the reproduced video FM signal fluctuate, causing wow and flutter to occur in the demodulated audio. This may cause image shaking, etc. to the video signal. Therefore, it is necessary to detect the time axis fluctuations of the reference signal of this video signal and correct the time axis fluctuations so that these fall within tolerance values.

FIG. 1 is a block diagram for explaining the principle of such a conventional time axis fluctuation correction device. In the same figure, 1
is a variable delay element (hereinafter abbreviated as COD) that controls the amount of delay of the reproduced video signal a; 2) is a horizontal synchronizing signal separation circuit that separates the synchronizing signal MY from the video signal output from the CCD 1 and outputs a reproduced horizontal synchronizing signal . 3 is a phase detection circuit for detecting the phase difference between the reproduced horizontal synchronizing signal and the reference horizontal synchronizing signal R;
4 is a phase compensation circuit that makes the servo system work stably; 5 is a
A variable frequency oscillator C (hereinafter abbreviated as vCO) changes the clock frequency of the CCD 1 according to the output DC level of the phase compensation circuit 4, and 6 is a clock pulse VCCDI' of the VCO 5.
7 is a clock drive circuit that supplies the
M d k input Y le CCD, s H, VCO5 (7”
) A clock drive circuit that supplies clock pulses to the CCD 7; 9 is a band-pass filter for the first channel of the audio FM signal; 10 is a clock drive circuit that supplies clock pulses to the CCD 7; 10 is a clock drive circuit that supplies clock pulses to the CCD 7;
A first demodulation circuit demodulates the M signal and outputs audio; 11 is a band pass filter for the audio FM signal second channel; 1;
2 is a second demodulation circuit that demodulates the audio FM signal that has passed through the band-pass filter 11 and outputs audio.

Next, the operation will be explained. Playback video signal a from the disc
is input to the CCD 1 and output after being delayed by the CCD 1. The CCD output video signal is input to the horizontal synchronization separation circuit 2 and a video amplifier (not shown), and the output of the video amplifier becomes the monitor TV input. A reproduced horizontal synchronization signal is obtained by the horizontal synchronization separation circuit 2, inputted to the reproduced horizontal synchronization signal 7 phase detection circuit 3, and compared in phase with the reference horizontal synchronization signal to obtain a voltage corresponding to the amount of time axis variation. Pressure t
Input to VCO5 via 5-phase compensation circuit 4,
Control the frequency of clock pulses. Clock pulses from the VCO 5 are supplied to the CCD 1 via a clock drive circuit 6 to control the amount of delay of the CCD 1 and suppress the amount of time axis variation in the output video signal of the CCD 1. From the above, when the reproduced video signal a is input to the CCD 1, it is delayed so as to suppress the time axis fluctuation of the Deba signal (video signal b), and then output, and the time axis fluctuation of the reproduced video signal is corrected. will be carried out.

By the way, since the reproduced FM signal and the reproduced video signal have the same time axis recorded on the disk, the amount of time axis variation and its appearance are also the same during reproduction. Therefore, as shown in FIG. 1, the time axis of the reproduced F'M signal is corrected using the time axis variation correction signal of the reproduced video signal and the COD having the same number of bits as the reproduced video signal.
It is easily conceivable from the prior art that this will happen. In this method, the clock frequency for the audio FM signal is used at a frequency lower than the required value, so the power consumption for driving the clock is large. There was a disadvantage (disadvantage).

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an audio FM signal time axis fluctuation correction device that saves CCD clock driving power.

[Summary of the invention]

In order to achieve the above object, the present invention lowers the clock frequency of the CCD by passing the audio FM signal through a frequency conversion circuit and a filter circuit and inputting it to the CCD.
D drive power is saved.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, C is the clock pulse of the VCO 5 explained in FIG. 13 is the frequency Y1/m' of clock pulse C
A frequency divider 14 converts the output signal of the frequency divider 13 into a CCD 15.
clock drive circuit that supplies the Reference numeral 15 denotes an oscillation circuit that generates a frequency-converted reproduced FM signal d''7 and performs time axis fluctuation correction of the reproduced FM signal d''.16 denotes an oscillation circuit that generates a local oscillation frequency for frequency conversion. A mixing circuit that mixes the reproduced FM signal frequency d from the disk and the local oscillation frequency of the oscillation circuit 170; 18 is a mixing circuit 17;
The difference frequency component (lower frequency component) of the output signal d' of
19 is a low-pass filter that passes the left channel frequency (0.2 Mt-
2o is a left demodulation circuit that demodulates the audio FM signal left channel signal into an audio signal, and 21 is a left band pass filter that only passes the audio FM signal right channel frequency (0.7 MHz) output from the CCD 15. The right bandpass filter 22 is a right demodulation circuit that demodulates the right channel signal of the audio FM signal into audio.

Next, the operation will be explained. The clock pulse C from the video signal correction VCO 5 explained in FIG. 1 is input to the frequency divider and divided into 1/fn. The clock pulse output from the frequency divider is supplied to the CCD 15 via the clock drive circuit 14, and the delay amount of the CCD 15 is controlled by the following equation (1), thereby suppressing the amount of time axis variation of the reproduced audio FM signal.

Here, Δτ; variable delay time amount n'; CCD14M') Number of humans.

(n'=n/m...(2))(n;CCL)
10-bit number) m: Dividing number of the frequency divider.

fc, ; Minimum frequency of clock pulse C.

fc2; highest frequency of clock pulse C;

On the other hand, the frequencies of the reproduced audio FM signal d of the original video disc are 2.3 MHz and 28 MHz, as shown in Figure 3.
It is. The mixing circuit 17 performs frequency conversion between the local oscillation frequency 2.1 MHz of the oscillator 16 and the reproduced audio F'M signal, and the low-pass filter 18 converts the difference frequency component (02
CC
D15 outputs a signal in which the time axis fluctuation amount of this difference frequency component is corrected. The left bandpass filter 19 passes only the lower frequency (0, 2 MHz) of the difference frequency components, inputs it to the left demodulation circuit 20, and converts it into an audio signal. On the other hand, the cloth band filter 21 passes only the high frequency (0,7M)lz) of this difference frequency component, and converts it into an audio signal through the right demodulation circuit.

Incidentally, regarding the clock frequency fc of the CCD and the power consumption with respect to the clock frequency, as shown in FIG. 4, the power consumption generally decreases as the clock frequency decreases.

And the clock frequency f. and the input signal f of CCD17
According to the sampling theorem, the following equation (3) is required for s.

fs (2fc −= (31) Therefore, when the input signal frequency of the CCD 17 becomes lower, the clock frequency can also be reduced accordingly, and the power consumption for the clock of the COD can be reduced.

In addition, the number of bits of the CCD is also as shown in equation (2) above.
It can be reduced by the frequency division ratio. I. [Effects of the Invention] According to the present invention, COD can be reduced by lowering the audio FM signal frequency.
, the clock frequency of COD can be lowered.
Power consumption for CCD clock can be reduced. Furthermore, C
This has the effect of reducing the number of bits on a CD.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional audio FM signal time axis fluctuation correction device, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram of frequency conversion of the reproduced audio FM signal of FIG. An explanatory diagram of the situation, FIG. 4, is a diagram showing the consumption force characteristic for the clock against the clock frequency of the COD. 13... Frequency divider, 14... Clock drive circuit, 1
5... Variable delay element, 17... Mixing circuit, 18...
-Low pass filter, 19...Left band pass filter, 20...Left demodulation circuit, 21...Right band pass filter 22...Right demodulation circuit. Figure / Figure / Figure 2 Figure 3 Sound % fM signal failure [js (t4Hz> Figure 4)

Claims (1)

[Claims] 1. A first variable delay element that delays and outputs a signal that includes an input reference signal; a second variable delay element that delays and outputs a signal that does not include the input reference signal;
means for controlling the amount of delay in the variable delay element;
- means for controlling the delay amount in the second variable delay element by the delay amount control signal of the ee1 variable delay element;
A time axis fluctuation correction device characterized in that a signal that does not include the reference signal is inputted to the 20T variable delay element through a frequency conversion circuit and a filter circuit.