JPS60153137A - Dimension measurement for semiconductor device - Google Patents

Abstract

PURPOSE:To enable the determination of the effective channel length and the easy inspection by means of an inspection instrument such as a tester by measuring dimensions from the measurement result of layer resistance value of a test pattern section, the length of a diffused resistance layer, and the resistance value. CONSTITUTION:The titled device is made of the section of Van der pauw pattern to obtain the layer resistance Rs of a diffused layer and the bridge section to obtain the length of the diffused layer. Van der pauw pattern electrodes 11, 12, 13, and 14 are connected to the diffused layer 16 each through a contact part 15. The voltage Vs generating between the electrodes 11 and 14 is measured by passing a current Is between the electrodes 12 and 13. The electrodes 14, 17, 18, and 19 are bridge circuit electrodes to measure the diffusion length GD of the diffused layer 22 formed in a semiconductor substrate part sandwiched between gate materials 20 and 21. The voltage VB between the electrodes 17 and 18 is measured by passing a current IB between the electrode 14 and 19. The effective length LFE is obtained by subtracting Gd from the constant.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is for evaluating the characteristics of MOS transistors formed as individual semiconductor elements or MOS transistors built into MO8 type large-scale integrated circuits (LSI). This relates to a method for measuring the dimensions required for.

Conventional Structure and Problems Large-scale integrated circuits have become increasingly finer, and MOS transistors with gate lengths of 2 to 3 μm or less have been integrated. As the gate length becomes shorter, a short channel effect occurs, making it difficult to set the threshold voltage. In order to maintain high manufacturing yields in such large-scale integrated circuits, it is necessary to know not only the gate length dimension but also the effective channel length, which is obtained by subtracting the lateral diffusion spread of the source and drain diffusion layers. There is.

FIG. 1 shows the principle of a conventional example in which the effective channel length is determined from the characteristics of a MOS transistor.

The explanation of Figure 1 is based on the literature by J, G, T, CHERN et al.
TTER8VOL, EDL-1, A9.1980)
Now follow the line.

From the IV characteristic in the linear region of a MOS transistor, the drain current becomes s and the drain resistance becomes the RCh score.

Here, s Ni-drain source current vDs Ni-drain source voltage vGs : Gate-source voltage vT : Gate threshold voltage μ8 : Mobility of carriers in the channel Cox : Gate oxide film capacitance Leff "Effective channel length Woll : Effective channel width Rchan” channel resistance.

Furthermore, We f f”WMA S K−ΔWLeff”LM
The drain resistance Rrn measured from ASK - ΔL % = R@xt + Rchan is... Formula (1) where WMASK: Channel width on mask LMAS
K: Channel length on the mask ΔW: WMASK−WeffΔ”−LMASKoff Rm: Drain resistance to be measured Rext” External resistance.

Effective channel length. In order to calculate ff, the relationship in equation (1) is used. The relationship between the measured drain resistance and the channel length on the mask is linear. FIG. 1 illustrates the relationship expressed by equation (1), where the horizontal axis represents the channel length on the mask and the vertical axis represents the measured drain resistance. The slopes a, b, and c of the straight lines are the gate-source voltage v in equation (1).
It can be changed arbitrarily by changing Gs. The slope is a, b.

When the drain voltage vDs is changed as shown in C, the point (ΔL, Rext) is the intersection point when the drain voltage vDs is constant.

When ΔL is rounded, the effective channel length Loff is - on the mask.
From the dimension LMASK, it can be determined as eff - MASK - ΔL.

According to the conventional method as shown below, the effective channel length L
eff includes several types of transistor characteristics and must be indirectly estimated from these characteristics. Therefore, it is not easy to automate measurements using a tester or the like during the manufacturing process.

Further, as a more direct measurement method than this method, there is a method using scanning electron microscopy.

With this method, the diffusion layer and gate length dimensions can be directly and accurately measured, but the sample must be destroyed for measurement1.
゜Also, prior to measurement, a specific location on the sample must be precisely etched between bones, and this area must be etched, making it possible to perform a large number of inspections and evaluations automatically and in a short period of time during the manufacturing process. It is difficult to do. As described above, the conventional measurement method has a problem that makes it difficult to adopt it in the production of semiconductor devices.

OBJECTS OF THE INVENTION It is an object of the present invention to be able to determine the effective channel length from the resistance of a diffusion layer sandwiched between two gate materials, and to
The object of the present invention is to provide a dimension measurement method that allows easy inspection using an inspection device such as a tester.

Structure of the Invention The dimension measuring method of the present invention is based on the Van der Pouw (Van der Pouw) structure, which is designed to measure the layer resistance of the source and drain diffusion layers that determine the effective channel length.
auw) A positional relationship is established in which the test pattern formation portion (referred to as a pattern) is separated by a distance GM based on a predetermined design rule. In addition, these shapes are set to be the same, and impurities are diffused into the semiconductor substrate region located between them using these as a mask to form a diffused resistor having a length and width based on predetermined design rules. A layer is formed, a current source terminal and a voltage measurement terminal are attached to measure the resistance value of the diffused resistance layer, and the layer resistance value of the test pattern portion is measured using the electrodes associated with the test pattern described above. This method measures dimensions from the measurement results and the length, width, and resistance value of the diffused resistance layer.

Which dimension measurement method to adopt, it is important to measure not only the effective channel length when impurity introduction such as ion implantation is self-aligned (self-aligned) to form source and drain diffusion layers only at the gate electrode, but also the effective channel length of the gate electrode. This is a diagram in which it is possible to measure the effective channel length when impurity introduction such as ion implantation is carried out in a self-contained 7-line manner using the mask material formed on the surface of the semiconductor substrate 1. Gate 2 and Gate 3 are selected to have equal values.
are arranged with a spacing G, and mask layers 4 and 6 made of a resist film or an oxide film are formed on the gates 2 and 3 to form these by etching. Both of these lengths are LR, and the spacing is GR9. In the figure, 6 and 7 schematically indicate patterns on the mask for forming the patterns of the mask layers 4 and 6, and the lengths are LR. It has a distance LM and a distance GM. Further, 8 is a gate insulating film, and 9 is a diffusion layer formed in the semiconductor substrate 1. Incidentally, the diffusion layer 8 is self-fabricated using the mask layers 4 and 5 or the gates 2 and 3 made of resist or oxide film, and is formed by, for example, ion implantation and subsequent heat treatment. The length of the diffusion layer 9 is GD and the interval is LEF. This LEF is the effective channel length.

10 is the lateral extent of the diffusion layer 8 from the edge of the gate, and its length is Δl.

Based on the drawings explained above, the effective channel length LEF formed under the gates 2 and 3 can be determined as follows. Since the sum of the effective channel length LEF and the lateral spread of the diffusion layer 8 directly below the gate, 2Δl, is expressed by the formula LEF-L-2Δ1 2Δd-GD-G, the effective channel length LEF
is LEF-L-(GD-G) = L+G-GD = cone t -GD -- (2).

Here, L + G = cons t'...---(
3) That is, L+G in equation (3) is the total pitch of the line length and line spacing at the time of mask design, and is a constant value regardless of pattern transfer, etching, or diffusion.

Note that equation (2) can be derived without using the lateral diffusion layer length Δl. As shown in equation (3) above, the sum of the line length and interval is established for each of the mask, resist, gate, and diffusion layer, so LM+GM=LR+GR=L+G=LEF+GD==aonet.

The formula holds true. From this relational expression, the effective channel length LE
F is LEF=const, -GD- (4). This equation (4) is equivalent to equation (2).

As described above, the effective channel length LEF is determined by the length GD of the diffusion layer 8 formed in the semiconductor substrate located between the two gate materials or the mask layer made of resist or oxide film thereon. It can be accurately calculated from the design rule value.

FIG. 3 shows the pattern structure and electrode configuration for actually determining the effective channel length LEF according to the dimension measuring method of the invention described above.

This pattern structure and electrode configuration are functionally composed of a van de Bouw pattern part that accommodates the layer resistance R8 of the diffusion layer, and a bridge part that accommodates the length of the diffusion layer. .

In the figure, reference numerals 11, 12, 13 and 14 are van de Bouw pattern electrodes, each of which is connected to the diffusion layer 16 through a contact portion 16.

Then, a current is passed between electrodes 12 and 13, and electrode 1
Measure the voltage 6 generated between 1 and 14. Electrode 14
, 17, 18 and 19 are the diffusion lengths GD of the diffusion layer 22 formed in the semiconductor substrate portion sandwiched between the gate materials 2o and 21.
This is the electrode of a bridge circuit for measuring . Diffusion layer 2
2 is connected to the diffusion layer 16, and each electrode 14.1 is still connected to the diffusion layer 16.
7 to 19 are connected to the diffusion layer through the contact portion 16. Note that the electrode 14 serves both as an electrode for the Van de Bouw pattern and as an electrode for the bridge circuit. By the way, in the principle explanatory diagram of FIG. 2, the cross-sectional structure of the illustrated pattern along the x-
This corresponds to the structure when only one is formed. That is, gate material 2.3 in FIG. 2 corresponds to gates 20 and 21 in FIG. 3.

Gate materials 20 and 21 are separated by a distance G,
Moreover, it has a length W that is sufficiently larger than this interval G.

A current IB is passed between electrodes 14 and 19, and electrodes 17 and 18
Measure the voltage VB between 3 and the effective channel length LEF can be calculated from the following formula.

GD = RXWXIB/VB --... (5) formula % formula % R8: Resistance of diffusion layer 16 v8: Measured voltage between electrodes 11 and 14 I8: Current flowing between electrodes 12 and 13 - 〇D: Diffusion layer Length W of 22: Gate material 20. Length 21 1B = Current flowing between electrodes 14 and 19 B: Measured voltage between electrodes 17 and 19 C: Constant determined by column rule C = G + L G : Distance between the gate materials 2o and 21 on the mask L: This is the mask dimension of the gate length of the effective channel length to be measured. Incidentally, the MOS transistor in the LSI to be measured and the van de pouno turn are usually formed at close positions within the circuit board.

Therefore, various conditions such as impurity diffusion conditions can be considered to be almost the same, and the diffusion length G'D in equation (5) is expressed as (4
) can be regarded as the same value for the diffusion length GD in the equation. Moreover, even if there is an error, it is a small error that can be ignored. Therefore, the effective channel length of the MOS transistor can be calculated more accurately than the diffusion length GD and the mask design value. Incidentally, the gate dimension on the mask is 6.8μ
m, and the resist dimension on the gate was 4.22±0.15 μm, and an effective channel length of 3.07±0.05 μm was obtained. The lateral depth of diffusion is calculated to be approximately 0.5 μm.

The resulting diffusion depth was actually measured and found to be 0.69 μm. From this, it became clear that the dimension measurement according to the present invention was carried out correctly.

Note that although the diagram shown in FIG. 3 shows a structure in which the diffusion layers 16 and 22 are connected and the electrode 14 is used as a common electrode in order to reduce the number of electrodes, it is possible to connect the diffusion layers 16 and 22 independently. You can also do so. In this case, it is only necessary to add one more electrode.3 The important thing is to make the formation positions of the diffusion layers 16 and 22 as close as possible to avoid variations caused by the positions between them. It means paying the utmost consideration.

As described in detail, the method for measuring the effective channel length of the present invention allows the effective channel length of a miniaturized 1viO8) transistor to be determined from electrical measurement results and a simple relational expression compared to the conventional method. can also be measured directly.

Therefore, it is possible to carry out inspections of semiconductor manufacturing process conditions automatically and in large quantities. That is, the effective gate length can be determined by a simple method without preparing a number of mask design values as in the conventional equation (1). Furthermore, since this method is a non-destructive method, it has the advantage that no restrictions are imposed on the measurement sample.

[Brief explanation of the drawing]

Figure 1 shows the effective channel length of a MOS transistor.
FIG. 2 is a schematic sectional view of a MOS transistor structure shown to explain the principle of the dimension measurement method of the present invention, and FIG. 3 is a diagram for explaining the conventional measurement method using a transistor. FIG. 2 is a plan view showing a pattern structure and an electrode structure that enable the dimension measurement method of the present invention. 1...Semiconductor substrate, 2, 3, 20.21...
・Game 14L 415...Mask ML6.7・
...Butter on mask/, 8...Gate insulating film, 9.22...Diffusion layer, 10...Transverse flow part of diffusion layer, 11-14...Van de... Bow pattern electrode, 16 - Contact portion, 16- - Diffusion layer for Rs measurement, 17 to 19... Electrode for measurement of diffusion length GD of diffusion layer 22. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Channel 7 on the figure mask and length 4 LMLsk 2 figure

Claims (2)

[Claims] (1) Gate material or masking of the same shape facing at a predetermined distance near a test pattern formed in a semiconductor wafer and having a first diffusion region for measuring the layer resistance of the drain and source regions. Arrange the material,
A second diffusion region is formed in the semiconductor substrate between the gate material interlayer or the masking material, and a current-carrying electrode and a voltage-measuring electrode are provided at both ends of the second diffusion layer. Dimensional measurement of a semiconductor device, characterized in that an effective ion length is calculated from the layer resistance of the diffusion region, the measured value of the resistance value of the second diffusion region, and the set length of the second diffusion region. Method. (2) The method for measuring dimensions of a semiconductor device according to claim 1, wherein the first diffusion region and the second diffusion region are connected to each other.