JPS60149278A - Digital picture processing circuit - Google Patents

Abstract

PURPOSE:To reproduce correctly the gradation of pictures by digitizing a picture signal and other information after superposing them and detecting the maximum or mininum level of the picture signal only to clamp the picture signal. CONSTITUTION:A multiplex information signal obtained by multiplexing a picture signal and other information is supplied to an input terminal 4 and converted into a digital signal by an A/D converter 1. This digital signal is supplied to a pedestal control circuit 2. The circuit 2 detects the minimum level of the picture signal only and clamps the picture signal. A signal (b) clamped at said minimum level is converted into an analog signal by a D/A converter 3 to obtain a multiplex picture signal containing the picture signal clamped at the minimum level. Thus the gradation of pictures can be reproduced correctly. The same effect is secured also by detecting the maximum level in place of the minimum level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital image processing circuit that digitally processes image signals such as television images.

Conventional configurations and their problems In recent years, television images have increasingly been digitized, transmitted, and computer-processed. in this case,
Other related reference information may be superimposed on the digitally processed image.

At this time, it is necessary to clamp the lowest level value in one screen in order to maintain the correct gradation of the image.

In conventional digital image processing, reference information such as character multiplexing is usually added to the digital image after D/A conversion at the receiving end.

Therefore, it is sufficient to perform minimum level detection on the entire digitized image. However, if another information is multiplexed onto an image and transmitted digitally, if the other information has a level value that is lower than the lowest level of image information, this other information level value may be erroneously detected as the lowest level of image information. This creates a problem that conventional clamp circuits cannot deal with.

OBJECTS OF THE INVENTION An object of the present invention is to provide an image digital processing circuit that automatically and correctly reproduces the gradation of an image of a signal in which other information is multiplexed with an image signal.

Structure of the Invention The present invention digitizes a multiplexed image information signal in which other information signals or noise signals related to the image information signal are superimposed, and clamps the image information by detecting the maximum or minimum level only for the image signal. This is a digital image processing circuit.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram in an embodiment of the present invention. In the figure, 1 is an A/D conversion circuit 2 is an image pedestal control circuit that detects the lowest level of the signal over one screen for video information that maintains gradation among input signals, and 3 is a D/A conversion circuit.
It is a conversion circuit. A multiple information signal in which an image signal and other information are multiplexed is input to the input terminal 4. 5 and 6 are input/output terminals of the pedestal control circuit 2, and 7 is an output terminal of the D/A converter.

The image pedestal control circuit 2 includes a clock pulse input terminal 82 for detecting the lowest level; an input terminal 9 for a signal corresponding to a period in which no other information signal related to the image signal exists; Mask signal input terminal 10 for setting the detection range. A BL signal input terminal 11 is provided for setting an image blanking period. Reference numeral 12 denotes a noise extraction circuit which extracts a noise component contained in the signal applied to the input terminal 4 and applies it to the pedestal control circuit 2.

FIG. 2 shows a specific circuit configuration of the pedestal control circuit 2 shown in the image of FIG.

In the figure, 5 is the output terminal of the A/D converter 1, and the 6-bit digital signal a is sent to the subtraction circuit 1 through the latch circuits 14 and 15.
Join 6. The latch circuit 14 stores the lowest level of the image signal latched up to the previous field. 13
A comparison circuit compares the input signal a applied to the input terminal 6 with the lowest level signal from the launch circuit 14. If input signal a is at a lower level, A
The output signal is sent to the ND circuit 18, and when the input signal a is at a higher level, the OR circuit 17 does not output. The AND circuit 18 receives a clock signal 8. in addition to the output of the OR circuit 17.
Low when there is another information signal.

Signal 9 and AND circuit 19 which become High when there is no
The output of is added. The AND circuit 19 takes the logical sum of the mask signal 10 for setting the detection area and the blanking signal 11, generates a detection range command signal, and inputs it to the AND circuit 18. Therefore, from the AND circuit 18, when the level of the input signal a is lower than the level stored in the latch circuit 14, the latch command signal is synchronized with the clock pulse and there is no other information signal within a predetermined detection range. When the input signal a is applied to the latch circuit 14, the content of the latch circuit 14 is updated to the level of the input signal a at that time, and at other times, that is, when the input level is higher than the level stored in the latch circuit 14, or at other times. When the information signal is present, the level of the latch circuit 14 is not updated regardless of the clock pulse or detection range command signal. In this way, the latch circuit 14 always stores the lowest level of the image signal.

The output of the latch circuit 14 is subtracted by the subtraction circuit 16 from the input signal stored in the latch circuit 16, so that the output terminal 6 receives the signal clamped at the lowest level stored in the latch circuit 14. Output. If this signal is converted into an analog signal by the D/A converter 3 in FIG. 1, a multiplexed image signal having the image signal clamped at the lowest level is obtained at the output terminal 7.

There are various types of separate information signals, such as audio signals, 9-character signals, and 2-picture signals.As an example, a contour line signal of a visible television image is used as a separate information signal, and multiplexed with a thermal image signal from an infrared camera. An example in which a /D-converted signal is applied to the input terminal 4 in FIG. 1 will be explained. At this time, AND circuit 1
A signal corresponding to the above-mentioned contour line signal is input to input 9 of 8, and in the contour line part, terminal 9 is at a low level and the latch circuit 14
operates so that the output of the AND circuit 18 is not input. Therefore, even if the lowest level value latch command is issued from the comparison circuit 17, if the signal at the input terminal 9 is Low, the latch circuit 1
4 means no latch operation. Therefore, the lowest level in one screen of a thermal image by an infrared camera is always detected from the part excluding the outline part. The level is subtracted to fix the black level of the thermal image. As a result, the black level of the thermal image signal from the D/A converter 3 is fixed and pedestally controlled, so that the gradation of the image can be accurately reproduced, and at the same time, the multiplexed visible image contour can be reproduced.

If a composite signal obtained by adding a noise period pulse obtained from the noise extraction circuit 12 of FIG. 1 to the contour signal is used as another information signal input, the reproduced image will be stable against noise and a ramp operation can be performed. Of course, the noise signal may be extracted all at once before the A/D input, its waveform shaped, and added to the AND circuit 18 of the pedestal circuit 2 separately from the other information signal.

71. In the above embodiment, the case where the image is clamped at the lowest level has been described, but the maximum level may be detected and clamped at this level.

Effects of the Invention As described above, the present invention digitizes the image information signal and the separate information signal while superimposing them, - detects the maximum or minimum level in the area other than the separate information signal period on the screen, and detects this. This digital image processing circuit clamps the image information signal with respect to the level, and has the following effects.

(1) Even in the case of multiple image signals, peak or bottom detection processing can be performed on specific signals included in the multiple image signals, and image gradation can be easily reproduced.

(2) The circuit for multiplexing and reproducing different information signals can be simplified.

(3) The clamping operation is stabilized even against noise contained in the image signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a digital image processing circuit according to the present invention, and FIG. 2 is a detailed circuit diagram of the pedestal control circuit section of FIG. 1. 1...A/D conversion circuit, 2...Pedestal control circuit, 3...D/A conversion circuit, 12.
...Noise extraction circuit, 13...Comparison circuit, 14.16...Latch circuit, 16...
・Subtraction circuit, 17...OR circuit, 18.19・
...AND circuit.

Claims (3)

[Claims] (1) The image information signal and the separate information signal are superimposed and digitized, - the maximum or minimum level of the area other than the separate information period on the screen is detected, and the image signal information is adjusted to this level. A digital image processing circuit characterized by clamping. (2) The means for detecting the maximum or minimum level is a comparison circuit that compares the input signal level with the maximum or minimum level up to the previous field, and a latch that latches the maximum or minimum level of the field according to the comparison result. 2. The digital image processing circuit according to claim 1, comprising: a circuit; and means for inhibiting a latch operation of said latch circuit for a fatal signal period. (3) The noise signal contained in the input signal is extracted, and the noise signal is combined with another information signal or waveform-shaped alone to prevent the latch operation of the latch circuit during this period. Digital image processing circuit.