JPS60148122A - Plasma etching of organic matter insulating film - Google Patents
Plasma etching of organic matter insulating filmInfo
- Publication number
- JPS60148122A JPS60148122A JP436384A JP436384A JPS60148122A JP S60148122 A JPS60148122 A JP S60148122A JP 436384 A JP436384 A JP 436384A JP 436384 A JP436384 A JP 436384A JP S60148122 A JPS60148122 A JP S60148122A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- etching
- gas
- plasma etching
- organic matter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001020 plasma etching Methods 0.000 title claims abstract description 14
- 239000005416 organic matter Substances 0.000 title abstract 3
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000007789 gas Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 11
- 239000009719 polyimide resin Substances 0.000 abstract description 6
- 239000011347 resin Substances 0.000 abstract 2
- 229920005989 resin Polymers 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の分野］
この発明はポリイミド等の有機絶縁膜のプラズマエツチ
ング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method of plasma etching an organic insulating film such as polyimide.
［発明の技術的背景とその問題点］
近年、有機絶縁膜は、段差被覆性、平滑性等のすぐれた
特徴を有しているため、半導体装置の層間絶縁膜などと
して用いられるようになってきている。この有機絶縁膜
のエツチングには従来よりウェットエツチングが主とし
て用いられてきたが、集積回路の高密度化に伴って微細
加工が必要になるにしたがって、酸素ガスによるプラズ
マエツチングが用いられるようになってきた。微細加工
に適した装置としては平行平板型のプラズマエツチング
装置がある。この装置は低圧の条件下でイオンを利用す
るためアンダーカットの少ないエツチングが可能であり
、加工精度が良い。又−１基板を置くステージを水冷す
ることで基板の温度を一定とすることが容易であり、高
い均一性、再現性が得られる。[Technical background of the invention and its problems] In recent years, organic insulating films have come to be used as interlayer insulating films in semiconductor devices because they have excellent characteristics such as step coverage and smoothness. ing. Wet etching has traditionally been mainly used for etching organic insulating films, but plasma etching using oxygen gas has come to be used as microfabrication becomes necessary as the density of integrated circuits increases. Ta. A parallel plate type plasma etching apparatus is suitable for microfabrication. Since this device uses ions under low pressure conditions, it can perform etching with less undercuts and has good processing accuracy. Furthermore, by water-cooling the stage on which the -1 substrate is placed, it is easy to keep the temperature of the substrate constant, and high uniformity and reproducibility can be obtained.
しかしながら、本装置でエツチングした絶縁膜断面は垂
直となり、例えば多層配線の層間絶縁膜に用いる場合、
スルーホール部で段切れが生ずる。However, the cross section of the insulating film etched with this device is vertical, so when used for example as an interlayer insulating film of multilayer wiring,
A break occurs at the through-hole section.
一方円筒型のプラズマエツチング装置、いわゆるプラズ
マアッシャ−を用いた場合、エツチング室内圧力が平行
平板型より高いためテーパーの付いたエツチング断面が
得られる。しかし、この装置では、基板が円筒状支持体
に支持されるため、両者の密着性が悪く、支持体を冷却
したとしても基板の温痘を一定に保つことがむずかしく
、エツチングの均一性、再現性が想いという雌点がある
。On the other hand, when a cylindrical plasma etching apparatus, a so-called plasma asher, is used, a tapered etched cross section can be obtained because the pressure in the etching chamber is higher than that of a parallel plate type. However, with this device, the substrate is supported by a cylindrical support, so the adhesion between the two is poor, and even if the support is cooled, it is difficult to maintain a constant temperature on the substrate, resulting in poor etching uniformity and reproducibility. There is a female point where sex is feelings.
［発明の目的］
本発明は上記問題貞を解決するためになされたもので、
平行平板型プラズマエツチング装置を用いて加工精度、
均一性、再現性を維持しながらテーパー持ったエツチン
グ断面を得ることを可能とした有機絶縁膜のプラズマエ
ツチング方法を提供することを目的とする。[Object of the invention] The present invention has been made to solve the above problems.
Processing accuracy using parallel plate type plasma etching equipment,
An object of the present invention is to provide a plasma etching method for an organic insulating film, which makes it possible to obtain a tapered etched cross section while maintaining uniformity and reproducibility.
［発明の概要］
本発明は、平行平板型のプラズマエツチング装置を用い
、エツチングカスとして酸素ガスの中にＣＦ４ガス等の
７０口カーボンを含んだガスを用いて有様絶縁膜の選択
エツチングを行おうとづるものである。フロロカーボン
ガスガスの含有量は好ましくは５０％以下とする。[Summary of the Invention] The present invention uses a parallel plate type plasma etching apparatus to perform selective etching of a specific insulating film using a gas containing 70 carbon atoms such as CF4 gas in oxygen gas as an etching gas. It is written by Outo. The content of fluorocarbon gas is preferably 50% or less.
［発明の効果］
本発明によれば、平行平板型プラズマエツチング装置を
用いて有機絶縁膜をエツチングする際、エツチングガス
として酸素ガスの中に７０口カーボンガスを加えること
によって加工精度、均−性等を保ったまま、エツチング
断面にテーパーを付けることが可能となった。従って有
機絶縁膜を層間絶縁膜として多層配線構造の半導体装置
を製造する場合に、配線の段切れを防止して信頼性向上
を図ることができる。[Effects of the Invention] According to the present invention, when etching an organic insulating film using a parallel plate plasma etching apparatus, processing accuracy and uniformity are improved by adding 70-hole carbon gas to oxygen gas as an etching gas. It is now possible to taper the etched cross section while maintaining the same. Therefore, when manufacturing a semiconductor device having a multilayer interconnection structure using an organic insulating film as an interlayer insulating film, it is possible to prevent disconnection of interconnections and improve reliability.
［発明の実施例１ 本発明の一実施例を図を用いて詳細に説明する。[Embodiment 1 of the invention An embodiment of the present invention will be described in detail with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の一実施例７として多層
配線構造の半導体装置の製造に適用した場合の工程断面
図である。まず８１基板１１上に８＋０２等の絶縁１１
１２を介して第１層目のＡ１配線１３ （１３１，１３
２、・・・）を所定のパターンに形成する（ａ）。次に
層間の有機絶縁膜として例えばポリイミド樹脂膜１４を
形成し、その上にマスク用金属膜として例えばモリブデ
ン膜１５を形成する（ｂ）。この後、モリブデンｌｌｌ
１１５をホトレジスト１６を用いて所定のパターンに形
成する（Ｃ）。次にレジス］・１６を残したまま、平行
平板型のプラズマエツチング装置でポリイミド樹脂１１
１１４をエツチングしてスルーホール１７（１７１，１
７２，・・・）を形成する（ｄ）。この際、エツチング
ガスとして酸素にＣＦ４を含むガスを用いてエツチング
することによりポリイミド膜１４にテーパーを付けるこ
とができる。例えば代表的なエツチング条件として、Ｃ
Ｆ４ ／ （０２＋ＣＦ４ ）＝０．１なるエツチング
ガスを用い、圧力を０．５ｔｏｒｒとし、ＲＦ電力を０
．１６ Ｗ ／’ ｃＩとしたとき、ポリイミドのエツ
チング速度は約８００人７ ｌ１ｌｉ ｎとなり、スル
ーホールーパーの角度は約６０’が得られる。次にマス
クのモリブデン膜１５を除去し、第２層目のＡ１配線１
８ （１８１ 、１８２・・・）を所定のパターンに形
成することによって二層配線ができあがる。FIGS. 1(a) to 1(e) are process cross-sectional views when the present invention is applied to the manufacture of a semiconductor device having a multilayer wiring structure as a seventh embodiment of the present invention. First, insulator 11 such as 8+02 on 81 board 11
12 to the first layer A1 wiring 13 (131, 13
2,...) are formed into a predetermined pattern (a). Next, a polyimide resin film 14, for example, is formed as an interlayer organic insulating film, and a molybdenum film 15, for example, is formed thereon as a mask metal film (b). After this, molybdenum
115 is formed into a predetermined pattern using photoresist 16 (C). Next, polyimide resin 11 was etched using a parallel plate type plasma etching device, leaving resist 16.
114 and through hole 17 (171,1
72,...) is formed (d). At this time, the polyimide film 14 can be tapered by etching using a gas containing oxygen and CF4 as an etching gas. For example, as a typical etching condition, C
Using an etching gas of F4/(02+CF4)=0.1, the pressure was set to 0.5 torr, and the RF power was set to 0.
．． When the etching rate is 16 W/' cI, the etching rate of polyimide is about 800 mm, and the angle of the through-hole looper is about 60'. Next, the molybdenum film 15 of the mask is removed, and the second layer A1 wiring 1 is removed.
8 (181, 182...) in a predetermined pattern, a two-layer wiring is completed.
このようにしてできた二層配線は、スルーホール部での
第２層１導体の段切れがなく信頼性の高いものである。The two-layer wiring made in this manner is highly reliable as there is no break in the second layer single conductor at the through-hole portion.
第２図は、エツチングガス中のＣＦ４の量を種々変えた
ときのポリイミド膜のエツチング速度と１ｑられるテー
パー角を測定した実験データである。FIG. 2 shows experimental data obtained by measuring the etching rate of a polyimide film and the taper angle 1q when the amount of CF4 in the etching gas was varied.
横軸は圧力比で示しである。他のエツチング条件は０２
＋ＣＦ４の圧力が０，５ｉｏｒｒ一定、ＲＦ電力が０．
１６Ｗ／ｃＩＩである。このデータから、エツチング速
度が大きくなるに従ってテーパー角は小さくなることが
わかる。この間テーパー角は９０°から４５°まで変化
している。したがって適当なエツチング速度となるよう
にＣＦ４の含有量を選ぶことによって、テーパー角を９
０”から４５゛の間で自由に選択できることがわかる。The horizontal axis shows the pressure ratio. Other etching conditions are 02
+CF4 pressure is constant at 0.5iorr, RF power is 0.5iorr.
16W/cII. This data shows that as the etching rate increases, the taper angle decreases. During this period, the taper angle changed from 90° to 45°. Therefore, by selecting the CF4 content to achieve an appropriate etching rate, the taper angle can be adjusted to 9.
It can be seen that it can be freely selected between 0" and 45".
上記実施例では、ポリイミド樹脂膜をエツチングする際
、ボ１へレジストを残したままとしたが、これを除去し
てからエツチングを行ってもよい。In the above embodiment, when etching the polyimide resin film, the resist was left on the hole 1, but the resist may be removed before etching.
又、有機絶縁膜としてポリイミド樹脂を用いたが、本発
明はこれに限られるものではなく、テフロンなどフッ素
系の有機絶縁膜に対し゛（も有効である。Further, although polyimide resin is used as the organic insulating film, the present invention is not limited to this, and is also effective for fluorine-based organic insulating films such as Teflon.
又、ＣＦ４に限らすＣｉ Ｆａ等を用いても良い。Moreover, CiFa, etc., which are not limited to CF4, may be used.
更に、従来の垂直にエツチングする方法と、本発明とを
組合わせることによって、第３図に示すような形状にエ
ツチングすることが可能である。Furthermore, by combining the conventional vertical etching method with the present invention, it is possible to etch into the shape shown in FIG.
これは、居間絶縁膜としてのポリイミドＪＩ１１４が厚
い場合に、スルーホール１７を余り大きぐすることなく
、しかもその上端部にテーパーをつけて断線防止を図る
ことができる点で有効である。This is effective in that when the polyimide JI 114 used as the living room insulating film is thick, the through hole 17 can be tapered at its upper end to prevent disconnection without making the through hole 17 too large.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程断面図、第２図はエツチングか。
ス成分を変化させたときのエツチング速度とテーパー角
の変化を測定したデータを示す図、第３図は他の実施例
を示す断面図である。
１１・・・８１基板、１２・・・絶縁膜、１３・・・第
１層Ａｌｔｉｉ！線、１４・・・ポリイミド樹脂膜（有
機絶縁膜）１５・・・モリブデン躾、１６・・・ホトレ
ジスト、１７・・・スルーホール、１８・・・第２層Ａ
１配輸。
出願人代理人 弁理士 鈴江武彦
第１図
第１ 図
第２図
ＣＦ４／ （０２＋ＣＦｚ）
第３図1(a) to 1(e) are process sectional views for explaining one embodiment of the present invention, and FIG. 2 is an etching process. FIG. 3 is a cross-sectional view showing another embodiment. 11...81 substrate, 12...insulating film, 13...first layer Altii! Line, 14... Polyimide resin film (organic insulating film) 15... Molybdenum layer, 16... Photoresist, 17... Through hole, 18... Second layer A
1 delivery. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 1 Figure 2 CF4/ (02+CFz) Figure 3
Claims (1)
所定基板上に形成された有機絶縁膜を選択エツチングす
るに際し、エツチングガスとしてフロロカーボンカスを
含んだ酸素ガスを用いることを１′□１８１″＊■膜（
７） ７５７ ｖ 、ｘて”′グ法・（２）エツチング
ガス中のフロロカーボンガスの含有量を５０％以下とす
る特許請求の範囲第１項記載の有機絶縁膜のプラズマエ
ツチング方法。 （３１基板は下地配線が形成された半導体基板であり、
有ｎＩ８縁膜は層間絶縁膜である特許請求の範囲第１項
記載の有機絶縁膜のプラズマエツチング方法。(1) Using a parallel plate plasma etching device,
When selectively etching an organic insulating film formed on a predetermined substrate, it is recommended to use oxygen gas containing fluorocarbon scum as an etching gas.
7) 757 v,x"' etching method (2) The plasma etching method for an organic insulating film according to claim 1, wherein the content of fluorocarbon gas in the etching gas is 50% or less. (31 Substrates) is a semiconductor substrate on which underlying wiring is formed,
2. A plasma etching method for an organic insulating film according to claim 1, wherein the nI8 edge film is an interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59004363A JPH0727886B2 (en) | 1984-01-13 | 1984-01-13 | Plasma etching method for organic insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59004363A JPH0727886B2 (en) | 1984-01-13 | 1984-01-13 | Plasma etching method for organic insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60148122A true JPS60148122A (en) | 1985-08-05 |
| JPH0727886B2 JPH0727886B2 (en) | 1995-03-29 |
Family
ID=11582292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59004363A Expired - Lifetime JPH0727886B2 (en) | 1984-01-13 | 1984-01-13 | Plasma etching method for organic insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727886B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01321634A (en) * | 1988-06-22 | 1989-12-27 | Nec Corp | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57115833A (en) * | 1981-01-12 | 1982-07-19 | Nippon Telegr & Teleph Corp <Ntt> | Polyimide resin film etching technique |
-
1984
- 1984-01-13 JP JP59004363A patent/JPH0727886B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57115833A (en) * | 1981-01-12 | 1982-07-19 | Nippon Telegr & Teleph Corp <Ntt> | Polyimide resin film etching technique |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01321634A (en) * | 1988-06-22 | 1989-12-27 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727886B2 (en) | 1995-03-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |