JPS60147822A - Power-on resetting circuit - Google Patents

Power-on resetting circuit

Info

Publication number
JPS60147822A
JPS60147822A JP59004355A JP435584A JPS60147822A JP S60147822 A JPS60147822 A JP S60147822A JP 59004355 A JP59004355 A JP 59004355A JP 435584 A JP435584 A JP 435584A JP S60147822 A JPS60147822 A JP S60147822A
Authority
JP
Japan
Prior art keywords
diode
comparator
capacitor
output
becomes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59004355A
Other languages
Japanese (ja)
Other versions
JPH042963B2 (en
Inventor
Hirokazu Toya
弘和 遠矢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59004355A priority Critical patent/JPS60147822A/en
Publication of JPS60147822A publication Critical patent/JPS60147822A/en
Publication of JPH042963B2 publication Critical patent/JPH042963B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To prevent sending out of wrong signals at the rising and falling times of power supply, by connecting a cerial circuit of a capacitor and diode in parallel with a resistor connected to the power supply side of a voltage detecting section and, at the same time, a diode between the connecting point of the capacitor and diode and an earth so that the earth side becomes an anode. CONSTITUTION:Since a comparator Z1 maintains a non-operating condition until time T1 after a supply voltage Vcc rises, an output Vo (waveform b) is raised. In a period rod from T1 to T2, the inversional input terminal 3 of the comparator Z1 is higher than the non-inversional input terminal 4 by the integrating effect of a capacitor C1 and resistors R2 and R3 and, therefore, the output Vo becomes low in level inclining toward earthing potential. Since the two input potential of the comparator Z1 are inverted, the output Vo becomes high in level inclining toward the supply voltage. When the supply voltage starts declining, a diode D2 becomes reverse bias and the delaying effect by the capacitor C1 disappears. As a result, the two input potential of the comparator Z1 are inverted at a preset point Vcc1 and the output Vo becomes low in level.

Description

【発明の詳細な説明】 (技術分野) −1−一 本発明はパワーオンリセット回路に関し、特に□ マイクロプロセッサ用に適するパワーオンリセット回路
に関するものである。
Detailed Description of the Invention (Technical Field) -1-1 The present invention relates to a power-on reset circuit, and particularly to a power-on reset circuit suitable for a microprocessor.

□゛ 、“ (従来技術) 従来のパワーリセット回路はツェナーダイオ−Vと抵抗
器から成る基準電圧発生回路部と、2つの抵抗器の直列
口−から成る電圧検出部と前−基準電電回路部と電圧=
i部に接続され、初段に4゛、7・、1 、 1.、、
、、、、。
□゛,“ (Prior art) A conventional power reset circuit consists of a reference voltage generation circuit section consisting of a Zener diode V and a resistor, a voltage detection section consisting of a series connection of two resistors, and a pre-reference electric circuit section. and voltage =
Connected to part i, 4゛, 7., 1, 1. ,,
,,,,.

レクタ接地増幅口路を有する1個のコンパレータとから
構成、れえも−8あ1、。、1.イ、。
Consisting of one comparator with a grounded amplifier amplification path, Reemo-8A1. , 1. stomach,.

、 ・ ′ □ プロセッサ等のように水晶発振器を有し、発振器:)ト
1 が安定発振となるまでリセット信号を保持する必要があ
る場合には、前記パワーリセット回路41111 段に、同じくコンパレータと、抵抗1.コンデンサと゛
 ′ 護 から成る積分型遅延回路を接続して構成していた。
, ・ ′ □ If the device has a crystal oscillator, such as a processor, and it is necessary to hold the reset signal until the oscillator becomes stable oscillation, the power reset circuit 41111 stage is also provided with a comparator, Resistance 1. It was constructed by connecting an integral delay circuit consisting of a capacitor and a protector.

・ ・ 1−1− □ 従って、従来のパワーオンリセット回路はマイ1ぽ1 クロプロセッサを応用する装置1ltVcおいては複雑
と11 1 11 な9.実装スペースが大きく、又1価格も高いとζ 2− (発明の目的) 本発明の目的は従来、のパワーオンリセット回路に3け
る前記欠点を除去し、かつ電源切断時もリセットが安定
に作動するようにしたパワオリセット回路を提供するこ
とにある。
・ ・ 1-1- □ Therefore, the conventional power-on reset circuit is complicated in a device applying a microprocessor. (Objective of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks of conventional power-on reset circuits, and to provide stable reset operation even when the power is turned off. It is an object of the present invention to provide a power reset circuit configured to do the following.

(発明の構成) 不発明によれば、ツェナーダイオードと抵抗器の直列(
ロ)路から成る基準電圧発生部と、2つの抵抗器の直列
回路から成る電圧検出部と、前記基準電圧発生部と前記
電圧検出部とに接続されるコンパレータとから構成され
るパワオンリセット回路に?いて、前記電圧検出部の電
源側に接続された抵抗器と並列にコンデンサとダイオー
ドの直列回路を接続し、かつ、前記コンデンサとダイオ
ードの接続点と、接地ライン間に接地側がアノードとな
るようにダイオードを接続して成るパワーオンリセット
回路が得られる。
(Structure of the invention) According to the invention, a Zener diode and a resistor connected in series (
b) A power-on reset circuit consisting of a reference voltage generation section consisting of a circuit, a voltage detection section consisting of a series circuit of two resistors, and a comparator connected to the reference voltage generation section and the voltage detection section. To? A series circuit of a capacitor and a diode is connected in parallel with the resistor connected to the power supply side of the voltage detection section, and the ground side is an anode between the connection point of the capacitor and the diode and the ground line. A power-on reset circuit formed by connecting diodes is obtained.

(実施例) 次に本発明の実施例について図面を参照して詳細に説明
する。
(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例を示す。第1図において、不
発−のパワーリセットツェナーダイオードDI と抵抗
器几1の直列回路から成る基準電圧発生部と、2つの抵
抗器R2,)13の直列回路から成る電圧検出部と前記
基準電圧発生部と前記電圧検出部とに接続されるコンパ
レータZlとから構成されるパワーオンリセット回路に
おいて、前記電圧検出部の電源側Vccに接続された抵
抗器R2と並列に接続したコンデンサC1とダイオード
D20直列回路と、前記コンデンサC1とダイオードD
2の接続点7と接地2170間に接地側がアノードとな
るように接続したダイオードD3とを含む。
FIG. 1 shows an embodiment of the invention. In FIG. 1, there is shown a reference voltage generation section consisting of a series circuit of an unfired power reset Zener diode DI and a resistor 1, a voltage detection section consisting of a series circuit of two resistors R2, ) 13, and the reference voltage generation section. and a comparator Zl connected to the voltage detection section, the power-on reset circuit includes a capacitor C1 connected in parallel to a resistor R2 connected to the power supply side Vcc of the voltage detection section, and a diode D20 connected in series. circuit, the capacitor C1 and the diode D
2 and the ground 2170, the diode D3 is connected with the ground side serving as an anode.

コンパレータZlは初段にコレクタ接地増幅回路を有す
る1個のコンパレータで、接地端子lと電源端子2との
間の電圧VCCで動作し1反転入力端子3谷非反転入力
端子4及び出力端子5を有する。このコンパレータZl
にFi、 a配電源端子2と接地端子1との間に、電源
端子2に対して基準電圧(Vz )を発生さぜる工うに
接続されたツェナーダイオードDIと抵抗器R1とから
成る直列回路が、前記ツェナーダイオードDIと抵抗器
R1\ との接続点と、非反転入力端子4との間に接続された抵
抗器R6を介して接続され、更に前記電源端子2と前記
接地端子lとの閲E、抵抗器R2の一端が前記電源熾子
2の側の検出電圧を発生する11−1さ よう接続された抵抗F#R2と!!竺器几3の一列〒路
が前記抵抗器R2とpXi起抵抗器R3の接続点を、: 介して反転入力端子3に接続されている。前記抵抗器R
2と抵抗器R3との接続点にはダイオードD20カソー
ドが接続されており、このダイオードD2と、このダイ
オードD2のアノード0と前記□ 電源電子2との間に接続されたコンデンサCIとが抵抗
器R2に並列に接続されている。前記ダイオードD2の
アノードと、前記接地端子1との関には前記接地端子l
の側がアノードとなる向きに接続されたダイオードD3
が設けられて2)、非反転入力端子4と出力端子5との
間には抵抗器5が設けられ、更に前記電源端子2と%前
記コンパ1□ レータZlの出力端子5との間には抵抗器R4が5− 設けられている。
The comparator Zl is a single comparator having a common collector amplifier circuit in the first stage, operates with the voltage VCC between the ground terminal l and the power supply terminal 2, and has 1 inverting input terminal, 3 valley non-inverting input terminals 4, and an output terminal 5. . This comparator Zl
A series circuit consisting of a Zener diode DI and a resistor R1 connected between the distribution power supply terminal 2 and the ground terminal 1 to generate a reference voltage (Vz) for the power supply terminal 2. is connected via a resistor R6 connected between the connection point between the Zener diode DI and the resistor R1\ and the non-inverting input terminal 4, and is further connected between the power supply terminal 2 and the ground terminal l. View E, one end of the resistor R2 is connected to the resistor F#R2, which generates the detection voltage on the side of the power source 2! ! One line of the resistor 3 is connected to the inverting input terminal 3 through the connection point between the resistor R2 and the pXi resistor R3. The resistor R
A diode D20 cathode is connected to the connection point between the diode D2 and the resistor R3, and a capacitor CI connected between the diode D2 and the anode 0 of the diode D2 and the power supply electronics 2 is connected to the resistor. Connected in parallel to R2. The ground terminal l is connected between the anode of the diode D2 and the ground terminal 1.
Diode D3 connected in such a direction that the side thereof becomes the anode.
2), a resistor 5 is provided between the non-inverting input terminal 4 and the output terminal 5, and a resistor 5 is provided between the power supply terminal 2 and the output terminal 5 of the comparator Zl. A resistor R4 is provided.

2図を参照して本実施例の動作を説明すると、第2図の
波形aは、ゆ木やかな立上9.立下りをもンパレータz
lの出力端子5の電圧Voを示すものであ°ふ、コンパ
レータZlは電源電圧VCCの立上夛後T1すなわち電
源電圧V CCOまでは不動作状態のため、波形aと同
様に波形すを上昇させる。
The operation of this embodiment will be explained with reference to FIG. 2. Waveform a in FIG. 2 has a smooth rise 9. Falling also comparator z
The comparator Zl is in an inactive state after the rise of the power supply voltage VCC up to T1, that is, until the power supply voltage V CCO, so the waveform rises in the same way as waveform a. let

T1からT2 までの間hコンデン−rC1と抵抗器R
2,R3との積分効果により、コンパレータZlの反転
入力端子3が、非反転入力端子4より高くなって29.
出力端子5の電位が接地電位に近い口9レベルとなる。
Between T1 and T2, h capacitor rC1 and resistor R
2, and R3, the inverting input terminal 3 of the comparator Zl becomes higher than the non-inverting input terminal 4 and becomes 29.
The potential of the output terminal 5 becomes the 9 level, which is close to the ground potential.

T2O点で前記コンパレータZlの2つの入力の電位が
戊転するた応、出力端子5の電位は電源電dに近い・・
イレベルとなり、T3まで継続する。次に、纂2図の波
形aのように、電源電圧Vccが低下しはじめると、前
記ダイオ−rD2が逆バイアスとな9.コンデンサCI
による遅延効果がなくなり、あらかじめ設定され6− たVcclの点(すなわちT3の点)でコンパレータZ
lの2つの入力の電位が反転し、出力端子5はロウレベ
ルとなる。この状態はT4まで続き。
Since the potentials of the two inputs of the comparator Zl change at point T2O, the potential of the output terminal 5 is close to the power supply voltage d...
level and continues until T3. Next, as shown in waveform a in Figure 2, when the power supply voltage Vcc begins to drop, the diode rD2 becomes reverse biased.9. capacitor ci
The delay effect due to the voltage drop is eliminated, and the comparator Z
The potentials of the two inputs of I are inverted, and the output terminal 5 becomes low level. This state continues until T4.

前記コンパレータZlが不動作となる電圧VCCOO点
(すなわちT4の点)で前記コンパレータZlの出力端
子5の電位はほばVccoまで上昇し、それ以降は、波
形Uとほぼ同じ電位で代下する。−万コンデンサCIの
電荷はダイオードD3を通して、電源側に放電される。
At the voltage VCCOO point (ie, point T4) at which the comparator Zl becomes inoperable, the potential at the output terminal 5 of the comparator Zl rises almost to Vcco, and thereafter drops to approximately the same potential as the waveform U. -The electric charge of the capacitor CI is discharged to the power supply side through the diode D3.

このパワーオンリセット回aはコンパレータZlの出力
端子5がマイクロコンピュータのリセット端子に接続さ
れ、電源電圧が立上夛、水晶発振回路が安定するまでの
間。
This power-on reset circuit a is a period from when the output terminal 5 of the comparator Zl is connected to the reset terminal of the microcomputer until the power supply voltage rises and the crystal oscillation circuit becomes stable.

動作を停止させる他、同じく出力端子5をマイクロコン
ビエータの周辺出力回路にチャネルロック信号として与
えることにより、電源電圧VCCの立上り又は立下9時
に他装置に対して、誤p7’(信号を出すのt確実に防
止することが小米る。
In addition to stopping the operation, by similarly giving the output terminal 5 to the peripheral output circuit of the micro combiator as a channel lock signal, it is possible to prevent other devices from erroneously outputting the p7' (signal It is definitely possible to prevent this from happening.

なP、抵抗器R5及びR6は、コンパレータzlのIJ
 、=ア動作領域を短時間で通過させ、出力電圧のチャ
タリング発生を防止するための正帰還回路でありもしチ
ャタリングがおってもよければ不要となる。
P, resistors R5 and R6 are IJ of comparator zl
,=A is a positive feedback circuit for passing through the operating region in a short time and preventing chattering of the output voltage, and is unnecessary if chattering is not an issue.

(発明の効果) 本発明は、以上説明したようにコンパレータ1個中心に
、最少限の部品で電源の立上り、立下り時の誤り信号の
送出を防止するように確実に動作させ、かつ小戯、低価
格でかつ信頼性の高い等の効果がめる。
(Effects of the Invention) As explained above, the present invention is capable of reliably operating a single comparator with a minimum number of parts to prevent the sending of error signals when the power supply rises and falls, and that , low cost and high reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

R1図は本発明の一実施例を示す回路図、R2図はR1
図の回路の動作を示す波形図である。 1・・・・・・接地端子、2・・・・・・電源端子、3
・・・・・・反転入力端子、4・・・・・・非反転入力
端子、5・・・・・・出力端子、Dl・・・・・・ツェ
ナーダイオード、 D2. D3−・・・・ダイオード
、Zl・・・・・・コンパレータ、R1−R6・・・・
−・抵抗器、CI・・・・・・コンデンサ。
Diagram R1 is a circuit diagram showing an embodiment of the present invention, and diagram R2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a waveform diagram showing the operation of the circuit shown in the figure. 1... Ground terminal, 2... Power terminal, 3
...Inverting input terminal, 4...Non-inverting input terminal, 5...Output terminal, Dl...Zener diode, D2. D3-...Diode, Zl...Comparator, R1-R6...
-・Resistor, CI... Capacitor.

Claims (1)

【特許請求の範囲】[Claims] ツェナーダイオードと抵抗器の直列回時から成る基準電
圧発生部と、2つの抵抗器の直り回路か5 ら成る電圧
検出部と前記基−電生発生部と前記電圧検出部とに接続
されるコンー’V−夕とから構成〒れる″ワー第2すゞ
′トロ路′lcゝいて・前記電圧検出部の電呼側に接続
されt抵抗器と並列にコンデ′すと′イ、t7)″0直
列!!竺を接続し・か9・前記コンデンサとダイオード
?竺続点と接地ライン間に接地側がアノードとなるよう
にダイオードを接続したことを特徴とするパイ−オンリ
セット回路。
A reference voltage generating section consisting of a Zener diode and a resistor connected in series, a voltage detecting section consisting of a straight circuit of two resistors, and a cable connected to the base voltage generating section and the voltage detecting section. ``V'' is connected to the telephone side of the voltage detecting section and connected in parallel with the t resistor. series! ! 9. Connect the capacitor and diode? A pi-on reset circuit characterized in that a diode is connected between a connecting point and a ground line so that the ground side serves as an anode.
JP59004355A 1984-01-13 1984-01-13 Power-on resetting circuit Granted JPS60147822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59004355A JPS60147822A (en) 1984-01-13 1984-01-13 Power-on resetting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59004355A JPS60147822A (en) 1984-01-13 1984-01-13 Power-on resetting circuit

Publications (2)

Publication Number Publication Date
JPS60147822A true JPS60147822A (en) 1985-08-03
JPH042963B2 JPH042963B2 (en) 1992-01-21

Family

ID=11582090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59004355A Granted JPS60147822A (en) 1984-01-13 1984-01-13 Power-on resetting circuit

Country Status (1)

Country Link
JP (1) JPS60147822A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720044U (en) * 1980-07-10 1982-02-02
JPS57170431U (en) * 1982-03-23 1982-10-27

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117535A (en) * 1979-02-28 1980-09-09 Osamu Kusumi Manufacture of western tableware

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720044U (en) * 1980-07-10 1982-02-02
JPS57170431U (en) * 1982-03-23 1982-10-27

Also Published As

Publication number Publication date
JPH042963B2 (en) 1992-01-21

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