JPS60146513A - Graphic equalizer - Google Patents

Graphic equalizer

Info

Publication number
JPS60146513A
JPS60146513A JP59002874A JP287484A JPS60146513A JP S60146513 A JPS60146513 A JP S60146513A JP 59002874 A JP59002874 A JP 59002874A JP 287484 A JP287484 A JP 287484A JP S60146513 A JPS60146513 A JP S60146513A
Authority
JP
Japan
Prior art keywords
resistor
capacitor
emitter
base
desired frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59002874A
Other languages
Japanese (ja)
Inventor
Hideaki Nojima
能島 英明
Tokuo Tsujimoto
辻本 篤男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59002874A priority Critical patent/JPS60146513A/en
Publication of JPS60146513A publication Critical patent/JPS60146513A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G5/00Tone control or bandwidth control in amplifiers
    • H03G5/02Manually-operated control
    • H03G5/025Equalizers; Volume or gain control in limited frequency bands

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To simplify the circuit without narrowing the effective variable frequency range by grounding a slider of a variable resistor of an impedance varying means at the highest potential only via a series circuit of capacitors or a capacitor and a resistor. CONSTITUTION:Plural impedance varying means n1, n2...nx' having different desired frequency are connected in parallel between a base and an emitter of an amplifier transistor (TR) Q1 to the base of which an audio signal from a music source 1 is applied via a resistor R4 and a coupling capacitor C1, and the desired frequency characteristic is obtained by constituting the impedance varying means nx' of the highest potential with a variable resistor VR connected between the base and emitter of the amplifier TRQ1 and a capacitor C4 connected to the slider of the variable resistor VR.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ラジオ受信機、テープレコーダ等のオーディ
オ機器に使用されるグラフィックイコライザに関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a graphic equalizer used in audio equipment such as radio receivers and tape recorders.

従来例の構成とその問題点 従来からグラフインクイコライザは第1図に示すように
ベースにソース源1からのオーディオ信号が抵抗R4お
よび結合コンデンサC5を介して加えられる増幅用トラ
ンジスタQ1 のベース−エミッタ間に希望周波数がそ
れぞれ異なる複数のインピーダンス可変手段n、、n2
・・・・・・nx を並列に接続し、これらのインピー
ダンス可変手段n、、n2・・・・・・nx によって
上記増幅用l・ランジスタQ1 のエミッタのインピー
ダンスを下けることにより」二1己増幅用トランジスタ
Q、のゲインを上け、一方上記インピーダンス可変手段
n、 、R2・・・・・・nx によって上記増幅用ト
ランジスタQ、のベースのインピーダンスを下けること
により信号源インピーダンスR4に対する分圧ゲインロ
スを生じさぜ、第2図に示すような周波数特性を実現す
るように構成していた。尚、第1図中、R1は負荷抵抗
、R2はバイアス抵抗、R3はエミ、り抵抗、’ 2 
+ 05は結合コンデンサであり、インピーダンス可変
手段n、 、R2・・・・・・nxのそれぞれは可変抵
抗器VRの可動端子を等制約にLC直列共振回路を構成
するアクティブフィルタAFを介して接地したものであ
る。しかしながら、上述した従来のグラフィックイコラ
イザは、その有効可変周波数範囲が最低位の希望周波数
で1 と最高位の希望周波数fx 0間にしかないにも
かかわらず、それぞれ異なる希望周波数のレベルを可変
するだめのインピーダンス可変手段n1.R2・・・・
・・nx の金板において可変抵抗器とアクティブフィ
ルタによ多構成されており、必要以外に回路を複雑にし
コストメリットを出しにくいという問題を有していた。
Conventional Structure and Problems Conventionally, a GraphInk equalizer has a base-emitter structure of an amplifying transistor Q1 to which an audio signal from a source 1 is applied via a resistor R4 and a coupling capacitor C5, as shown in FIG. A plurality of impedance variable means n, , n2 each having a different desired frequency between them.
By connecting . By increasing the gain of the amplifying transistor Q, and lowering the impedance of the base of the amplifying transistor Q by the impedance variable means n, , R2...nx, the voltage division for the signal source impedance R4 is increased. The structure was designed to cause gain loss and achieve the frequency characteristics shown in FIG. 2. In Fig. 1, R1 is a load resistance, R2 is a bias resistance, R3 is an emitter resistance, '2
+05 is a coupling capacitor, and each of the impedance variable means n, , R2...nx is connected to the movable terminal of the variable resistor VR through an active filter AF that constitutes an LC series resonant circuit with equal constraints. This is what I did. However, although the above-mentioned conventional graphic equalizer has an effective variable frequency range only between 1 at the lowest desired frequency and 0 at the highest desired frequency, it is difficult to vary the level of each different desired frequency. Impedance variable means n1. R2...
The NX metal plate is made up of multiple variable resistors and active filters, which makes the circuit unnecessarily complicated and has the problem of making it difficult to achieve cost benefits.

発明の目的 本発明は、上記従来の欠点を解消するものであり、有効
可変周波数範囲を狭くすることなく回路の簡素化を図る
ことができるグラフィックイコライザを提供することを
目的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned conventional drawbacks, and to provide a graphic equalizer whose circuit can be simplified without narrowing the effective variable frequency range.

発明の構成 上記の目的を達成するため、本発明のグラフィックイコ
ライザは、それぞれ異なる希望周波数のレベルを可変す
るだめの複数段のインピーダンス可変手段のうち、最高
位のインピーダンス可変手段のみ可変抵抗器の可動端子
をコンデンサ又はコンデンサと抵抗の直列回路を介して
接地するよう構成したことを特徴とするものでるる。
Structure of the Invention In order to achieve the above object, the graphic equalizer of the present invention has a plurality of impedance variable means for varying the levels of different desired frequencies, and only the highest impedance variable means has a variable resistor. It is characterized in that the terminal is configured to be grounded via a capacitor or a series circuit of a capacitor and a resistor.

実7M世」の説明 第3図は本発明の一実施例を示しており、第1図に同一
符号は同じ構1.4 安素を示している。第3図におい
て、第1図と異なるところは最高位のインピーダンス可
変手段n′x を、」盾幅用トランジスタQ1 のベー
ス−エミッタ間に接続した可変抵抗器VRと、その可変
抵抗器vEの可動端子を接地するコンデンサC4で構成
したことである。このように構成すると、最高位の希望
周波数fx より高い周波数領域において第4図の実線
A 、 A’に示すようにゲインが上がるが、最低位の
希望周波数f1 と最高位の希望周波数fx 間の有効
周阪叔11丁変範囲に変化はない。
Fig. 3 shows an embodiment of the present invention, and the same reference numerals in Fig. 1 indicate the same structure 1.4. In Fig. 3, the difference from Fig. 1 is that the highest impedance variable means n' It is configured with a capacitor C4 whose terminal is grounded. With this configuration, the gain increases as shown by solid lines A and A' in FIG. 4 in the frequency region higher than the highest desired frequency fx, but the gain increases between the lowest desired frequency f1 and the highest desired frequency fx. There is no change in the effective Shuhan Shu 11-chohen range.

なお、本実施例のグラフィックイコライザの□IJ段、
段設後接続される周波数特性をもった回路にゝ対してゲ
インが上がった部分が影響を与えるような場合には、コ
ンデンサc4 に直列に抵抗を押入することにより、第
4図の一点鎖線に示すように補°王すればよい。
Note that the □IJ stage of the graphic equalizer of this embodiment,
If the increased gain affects a circuit with frequency characteristics that will be connected after tiering, insert a resistor in series with capacitor c4, as indicated by the dashed line in Figure 4. Just correct it as shown.

上記の実施例ではインピーダンス可変手段n、、n=・
・・・・・n′x を増幅用トランジスタのベース−エ
ミッタ間に接続したが、他にインピーダンス可変手段は
増幅用トランジスタのコレクターエミッタ間に接続して
もよいことは云うまでもない。またインピーダンス可変
手段n、、n2・・・・・−n′エニーはアクティブフ
ィルタを使用したが、アクティブフィルタに代えLCi
列共振回路を使用してもよい。
In the above embodiment, the impedance variable means n, , n=.
Although n'x is connected between the base and emitter of the amplification transistor, it goes without saying that other impedance variable means may be connected between the collector and emitter of the amplification transistor. In addition, the impedance variable means n,, n2...-n'any used an active filter, but instead of the active filter, LCi
Column resonant circuits may also be used.

発明の効果 以上のように本発明によれば、最高位の希望周波数のレ
ベルを可変するだめのインピーダンス可変手段のみを、
可変抵抗器の可動端子をコンデンサ又はコンデンサと抵
抗の直列回路を介して接地するよう構成したので、回路
の簡素化を図ることができ、その有効周波数可変範囲を
確保することができる利点を有する。
Effects of the Invention As described above, according to the present invention, only the impedance variable means for varying the level of the highest desired frequency,
Since the movable terminal of the variable resistor is configured to be grounded via a capacitor or a series circuit of a capacitor and a resistor, the circuit can be simplified and has the advantage that its effective frequency variable range can be secured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のグラフィックイコライザの回路結線図、
第2図はその周波数特性図、第3図は本発明のグラフィ
ックイコライザの一実施例を示す回路結線図、第4図は
その周波数特性図である。 Ql ・・・・・・増幅用トラレジスタ、1・・・・・
・ソース源、R4・・・・・信号源インピーダンス、n
l、R2・山・・n/・・・・・・インピーダンス可変
手段、C4・・・・・・コンデンサ。 代理人の氏名 弁理士 中 尾 敏 男 はが1名矛2
図 手続補正書働式) 昭和グ年9万/ど口 昭和59年特許願第 2874 号 2発明の名称 グラフインクイコライザ 3補正をする者 事件との関係 生、I−許 出 願 人任 所 大阪府
門真市太字門真1006番地名 称 (582)松下電
器産業株式会社代表者 山 下 俊 彦 4代理人 〒571 住 所 大阪府門真市大字門真1006番地松下電器産
業株式会社内 Z、補正の内容 (1)図面の第4図を別紙の通り補正しまず。
Figure 1 is a circuit diagram of a conventional graphic equalizer.
FIG. 2 is a frequency characteristic diagram thereof, FIG. 3 is a circuit connection diagram showing an embodiment of the graphic equalizer of the present invention, and FIG. 4 is a frequency characteristic diagram thereof. Ql ・・・・・・Target register for amplification, 1・・・・・・
・Source source, R4...Signal source impedance, n
l, R2・mountain...n/...impedance variable means, C4...capacitor. Name of agent: Patent attorney Toshi Nakao (1 person, 2 persons)
Figure procedure amendment form) 1978 90,000/Doguchi 1987 Patent Application No. 2874 2 Name of the invention Graph Ink Equalizer 3 Relationship with the person who makes the amendment 1006 Bold Kadoma, Kadoma City, Osaka Name (582) Matsushita Electric Industrial Co., Ltd. Representative Toshihiko Yamashita 4 Agent 571 Address 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Z within Matsushita Electric Industrial Co., Ltd. Details of the amendment ( 1) First, correct Figure 4 of the drawing as shown in the attached sheet.

Claims (1)

【特許請求の範囲】[Claims] 増幅用トランジスタのベースーエミッタ又はコレクター
エミッタ間に並列に接続したそれぞれ異なる希望周波数
のレベルを可変するだめの複数のインピーダンス可変手
段のうち最高位の希望周波数のレベルを可変するインピ
ーダンス可変手段のみ、可変抵抗器の可動端子をコンデ
ンサ又はコンデンサと抵抗の直列回路を介して接地する
よう構成したことを特徴とするグラフィックイコライザ
Of the plurality of impedance variable means connected in parallel between the base-emitter or collector-emitter of the amplification transistor for varying the level of different desired frequencies, only the impedance variable means for varying the level of the highest desired frequency is variable. A graphic equalizer characterized in that a movable terminal of a resistor is configured to be grounded via a capacitor or a series circuit of a capacitor and a resistor.
JP59002874A 1984-01-11 1984-01-11 Graphic equalizer Pending JPS60146513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59002874A JPS60146513A (en) 1984-01-11 1984-01-11 Graphic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59002874A JPS60146513A (en) 1984-01-11 1984-01-11 Graphic equalizer

Publications (1)

Publication Number Publication Date
JPS60146513A true JPS60146513A (en) 1985-08-02

Family

ID=11541495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59002874A Pending JPS60146513A (en) 1984-01-11 1984-01-11 Graphic equalizer

Country Status (1)

Country Link
JP (1) JPS60146513A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61163428U (en) * 1985-03-29 1986-10-09

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254353A (en) * 1975-10-29 1977-05-02 Victor Co Of Japan Ltd Tone controller

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254353A (en) * 1975-10-29 1977-05-02 Victor Co Of Japan Ltd Tone controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61163428U (en) * 1985-03-29 1986-10-09

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