JPS6014581B2 - Variable power supply circuit system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable power supply circuit system that can obtain an output voltage in a range lower than the input voltage or in a range higher than the input voltage with a simple configuration.

FIG. 1 is a circuit diagram showing a conventional fin source conversion circuit, which is the basis of the present invention. A step-up type for obtaining voltage is shown, and in both cases, a tomb flow coil L is inserted in the dark line between the input terminal 1 and the output terminal 3, and
A capacitor C is connected between output terminals 3 and 4,
A comparison controller CCP is provided which compares the output voltage Vout with a reference voltage V''.

In the step-down type shown in Figure A, a switch S is provided in series to the input side of the flow line logic L, and a comparator controller CCP controls the duty ratio according to the on/off time ratio of the switch S. The output voltage Vout is lowered by decreasing the duty ratio with the upper limit being 100%, that is, the output pressure Vomax when the switch S is in the on state, and the output voltage Vout is made to match the reference voltage Vr. .

Note that the capacitor C is for ripple removal of the output voltage Vout, and the diode ○. is a flywheel diode for forming a DC circuit between the output terminals 3 and 4 when the switch S is turned off. In addition, in the step-up type shown in Figure B, a switch S2 is inserted between the output side of the blocking wire L and the other wire between the input terminal 2 and the output terminal 4, and this In order to release the electromagnetic energy accumulated in the blockage wire L when the switch S2 is turned off, the output voltage y is higher than the input voltage Vin.
The output voltage Vout is increased by increasing the duty ratio to approximately 85%, with the output voltage Vomin when the output voltage Vout is obtained and the duty ratio of the switch S2 is close to 0% as the lower limit, and the reference voltage Vr and the output fin are Pressure Vou
t.

Note that the diode D2 is provided to prevent the charge in the capacitor C from discharging to the input side when the switch S2 is turned on.

In addition, in this case, the comparison controller CCP is composed of an oscillator, a comparator, and a modulator that pulse width modulates the output of the oscillator using the output of the comparator. However, in the step-down type, the comparison controller CCP is simply a comparator. using the output voltage Vo
There is also a self-excited type that controls the switch S in response to changes in ut, and various control means have been proposed.

However, this type of power conversion circuit is not available in the February 1972 issue of "Transistor Technology" (Published by CQ Publishing Co., Ltd. → P15).
1. As shown in Tables 2-3, the lower limit output voltage Vomin of the step-up type is approximately 2V higher than the input voltage Vin, and the upper limit voltage Vomax of the step-down type is approximately IV lower than the input voltage Vin. However, it is not possible to obtain an output voltage Vout of 1, and also it is not possible to obtain an output voltage Vout that is higher or lower than the input voltage Vin by the same circuit.

The purpose of the present invention is to fundamentally solve these drawbacks of the conventional system. By skillfully combining buck-type operation and boost-type operation, the same circuit can control the input voltage in the high and low directions. The present invention provides an extremely effective variable power supply circuit system capable of obtaining a wide range of output voltages.

Hereinafter, the details of the present invention will be explained with reference to FIG. 2, which shows an example.

FIG. 2 is a circuit diagram showing an embodiment of the first invention;
It includes a switch S and a second switch S2,
It is equipped with diodes D, , D2, which is a combination of the step-down type and the step-up type shown in FIG. A tester DEC is provided as a test means for testing the on/off duty ratio, and its output is applied to an OR gate G and an AND gate G2, and a comparison controller CCP for each switch S, , S2 is provided. It controls the output supply.

FIG. 3 is a block diagram showing a specific example of the calibrator DEC, and includes flip-flop circuits (hereinafter referred to as FFC) FF. ，
The AND gates G and A and the inverter constitute a test circuit DET that detects a 100% duty ratio, and the FFC, FF2 and AND gates G and B form a test circuit DEL that tests a 0% duty ratio. These are supplied with an external clock pulse CL.
K and a delayed clock pulse DCLK obtained by slightly delaying the clock pulse CLK by a delay circuit DL are combined.

Now, when the control signals of each switch SI, S2 are on, “
H'' (high level) and "L" (low level) when off, the duty ratio of the first switch S is less than 100% and the duty ratio of the second switch S2 exceeds %. If so, the control signal a of the first switch S is “H”.
”, “L” are repeated, so even if the FFC/FF is set when the output of the inverter IN becomes “H”, it is reset by the delayed clock pulse DCLK.
The output Q of FFC/FF repeats “H” and “L” and becomes “
When the signal is high, the AND gate G,. is turned on.
The clock pulse CLK is output from the AND gate ○ earlier than the IJ set of FFC/FF by the delay time of the delay circuit DL.
、． The clock pulse CLK is applied to AND gates G, . does not pass through, and FFC and FF3 are not set. On the other hand, when the duty ratio of the control signal a becomes 100%, the output of the inverter IN continues to be "L", and the FFC and FF output the delayed clock pulse DCL.
To maintain the reset state by K, output Q is “H”
Then, the clock pulse CLK is applied to the AND gates G, . , sets FFC・FF3, and sets its output Q to “H”.
”, and sends out 2 as the verification output c.FFC・FF2 also uses the control signal b of the second switch S2.
exceeds the duty ratio %, the set-reset is repeated and the output Q is set to "H" in the reset state, but the FFC/FF is delayed by delay time 2 of the delay circuit DL.
2 is reset, the clock pulse CLK becomes AN
Do not pass through D gate G and do not reset FFC/FF3.

However, if the duty ratio of control signal b becomes %, then F
In order for FC・FF2 to maintain the reset state, the clock pulse CLK passes through AND gates C and 2 and FFC・F
Reset F3 and return the verification output c to "L".

Therefore, in FIG. 2, when the duty ratio of the first switch S, is less than 100% and the duty ratio of the second switch S2 is 0%, that is, in the off state, the certifier DEC,
Since the verification output c of is “L” and the AND gate ○2 is off, the output of the comparison controller CCP is the output of the OR gate ○,
The voltage is applied only to the first switch S, through which a step-down type operation is performed.

Therefore, when the output voltage Vo peak changes in the increasing direction due to an increase in the reference voltage Vr, the duty ratio of the first switch S increases, and the duty ratio is determined in a state where the reference voltage Vr and the output voltage Vout match. .

Furthermore, if the output voltage yo peak decreases, the Dunay ratio also decreases.

By the way, if we ignore the loss of each circuit element, P.
I16, {1- As shown in the formula, the output voltage Vo peak is given by the following formula.

TSION Vout=TSI.

N1TSIOFF・Vin...'11 Here, TSI
ON is the on time of the first switch S, and TSIOFF is the off time of the first switch S. However, in reality, the upper limit Vomax of the output voltage Vo is 1 to 2 V lower than the theoretical value when the duty ratio is 100% due to losses in the first switch S, the blocking wire L, and the diode D2. Become. Further, the duty ratio of the first switch S is 10
0%, that is, in the on state, the certifier DEC sets the verification output c to "H", so this force is applied to the first switch S, via the R gate G, and the first switch S, is turned on. At the same time, the AND gate G2 is turned on and the output of the comparison controller CCP is connected to the second switch S2.
It performs step-up operation, and the output voltage yo
If the output voltage is in the increasing direction, the duty ratio of the second switch S2 also increases, and the duty ratio is determined in a state where the reference voltage Vr and the output voltage output match.

In this case, if the loss of each circuit element is ignored, the output voltage Vo peak is given by the following formula, as shown in formulas PI18 and 18 of "Transistor Technology" July 1977 issue (published by CQ Publishing Co., Ltd.). It will be done.

Nin・TS phantom N) 2Vo mountain = 2. ,.

ut. Lpbis20N+TS20FF) 10 Vin...
(2) However, lout' is the output current, Lp is the inductance of the blocking wire L, TS phantom N is the on time of the second switch S2, and TS phantom FF is the OFF time of the second switch S2.
Furthermore, the first term on the right side of equation '2} is an increase in the output voltage Vout based on the electromagnetic energy accumulated in the dance line ring L while the second switch S2 is on, but the second term on the right side Vin corresponds to the upper limit output voltage Vomax in the step-down type because there is actually a loss due to circuit elements.

In addition, the duty ratio of the first switch S is 100%.
In addition, when the duty ratio of the second switch S2 exceeds 0% and the output voltage Vout is decreasing, the duty ratio of the second switch S2 decreases, resulting in an equilibrium state.

Further, when the duty ratio of the second switch S2 becomes %, the verification circuit DEC. Since the test output c becomes “L”,
When the AND gate ○2 is turned off and step-down operation is performed, and the output voltage Vo peak is in the direction of decreasing,
Balance is achieved by reducing the duty ratio of the first switch S.

Therefore, according to the circuit of FIG. 2, the output voltage y in a lower range and a higher range centering on the input voltage Vin.
The peak o can be obtained by setting the reference voltage Vr, but since the step-down type and step-up type operations are performed separately, it is not possible to obtain the output voltage Vout equal to the input voltage yin as described above. .

FIG. 4 is a circuit diagram showing an embodiment of the second invention that can obtain an output pressure yout equal to the input voltage Vin, and has two outputs as described below instead of the calibrator DEC in FIG. 2. OR gate G4, A
It is equipped with a pulse generator PG controlled by an ND gate ○5 and a comparison controller CCP, and when the duty ratio of the first switch S exceeds a predetermined value based on the verification operation of the verification device DEC2, the pulse generator PG is activated. Each switch S,...
S2 is turned on and off, thereby obtaining an output voltage Vo having a value equal to the input voltage Vin, and increasing the voltage between the above-mentioned upper limit output voltage Vomax in step-down type operation and lower limit output voltage Vomin in step-up type operation. 5 is a block diagram showing an example of the configuration of the calibrator DEC2 in FIG. 4, in which the control signal of the first switch S and The control signal b of the second switch S2 is given, and the detection circuit DET changes its output to “H” when the duty ratio of the control signal a becomes Q% or more.
”, and the detection circuit DET8 sets its output to “H” when the duty ratio of the control signal b becomes 8% or more. Therefore, if Q<8, the control signal a, When each duty ratio of control signal a is less than Q%, the output of each detection circuit DETQ, DET8 is "L", so each verification output c, d is both 11L, but when the duty ratio of control signal a is more than Q% And if the duty ratio of the control signal b is less than 8%, the output of the detection circuit DETQ becomes “H”.
", and the output of the detection circuit DET8 is inverted by the inverter state 2 and becomes "H", which is applied to the AND gate G,2, so that only the verification output d becomes "H".
This state is maintained until the duty ratio of the control signal b reaches 8%.

Also, if the duty ratio of control signal b reaches 8%,
The output of the detection circuit DET6 changes to "H" and is sent out as the verification output c.

FIG. 6 is a block diagram showing a specific example of the detection circuits DETQ, DET8, and when the duty ratio of each control signal a, b changes around Q or 8%, the operation of the detection circuits DET0, DET8. In order to prevent this from becoming unstable, a hysteresis characteristic is provided with respect to changes in the duty ratio.

That is, as the waveforms of each part are shown in the time chart of FIG. 7, the control signal CS generated based on the clock pulse CP obtained from the oscillator output of the comparison controller CCP in FIG. delayed clock pulses CP, .
CP2 is given to inputs 1 and 2 of selector SEL, respectively, and FFC. When the FF is in a reset state and its output Q is "L", the selector SEL selects input 1 and sends the delayed clock pulse CP to the FFC. It is applied as a clock pulse CPc to the clock input CK of the FF. Therefore, the duty ratio of the control signal CS is Q
Or, if it does not reach 8% and the period of "H" is shorter than Q, FFC.FF is not set and its output Q is "
Maintain “L”.

On the other hand, if the duty ratio of the control signal CS is Q or 8
% and the period of “H” is q or more, FFC.
The FF is set and the output Q is turned to "H", and the selector SEL is controlled, and this time the delayed clock pulse CP2 is set.
FFC. as clock pulse CPc. It is applied to the clock input CK of the FF.

Therefore, until the "H" period of control signal CS becomes shorter than Q2, FFC. If the set state of FF is maintained and the "H" period of control signal CS becomes shorter than Q2, FFC. The FF is reset and the output Q is set to "L", and the selector SEL is controlled to output the delayed clock pulse C.
Let them select P.

As mentioned above, FFC. FF is “H” of control signal CS
It is set when the period is equal to or greater than Q, and the control signal C
Since it is reset when the "H" period of S becomes less than Q2, it exhibits a hysteresis characteristic of Q - Q2, and Q,
, Q2 are set according to the duty ratio Q or B%, and FFC. If the output Q of the FF is sent as the detection force DO, a stable Z duty ratio detection operation can be obtained.

Therefore, in FIG. 4, if the output voltage Vout is lower than the input voltage, the duty ratio of the first switch S is less than the predetermined value Q%, and the duty ratio of the second switch S2 is 0%, the certifier Both outputs Zc and d of DEC2 are “L”
”, the AND gate G4 is in the off state, and the output of CP is supplied to the comparison controller only to the first switch S through the OR gate ○, and the output voltage yout increases due to the increase in the reference voltage Vr. When the voltage increases, the duty ratio of the first switch S also increases, and the duty ratio is determined in a state where the reference voltage Vr and the output voltage Vout match.

Note that if the output voltage yo mountain decreases, the first switch S,
The duty ratio of is also reduced. Further, if the duty ratio of the first switch S becomes equal to or higher than the predetermined value Q% due to an increase in the output voltage yout, then the duty ratio of the second switch S2 is less than the specific value 8%, and the verification circuit DEC2
While the output c of the pulse generator is "L", the output d changes to "H", so the AND gate G4 is turned on and passes the output of the pulse generator PG, and the second to the switch S2, the first and second switches S,
, S2 are both turned on and off, and a voltage near the input voltage Vin is generated by the interaction between the buck type operation and the boost type operation, and when the reference voltage Vr and the output voltage yo peak match, Each switch S. , S2 are determined.

However, for the on/off operations of the first switch S and the second switch S2, it is necessary to provide a period in which both are on at the same time. It is assumed that each switch S, , S2 performs on/off operations in synchronization with each other. Further, when the output voltage Vout further increases due to an increase in the reference voltage yr, if the duty ratio of the second switch S2 becomes a specific value of 8% or more, the output c of the calibrator DEC2 becomes "H".
Since the output d becomes "L" and the output c is given to the first switch S, via the OR gate G, the same switch S,
The duty ratio of CCP becomes 100%, that is, the ON state, the AND gates become ON, the AND gate G4 becomes OFF, and the output of the comparison controller CCP is sent to the second switch via the AND gate G2 and the OR gate G3. S2, and only the second switch S2 performs on/off operation, resulting in a boost type operation, and the reference voltage V and the output voltage
The duty ratio of the second switch S2 is determined in a state where the values match.

Therefore, a predetermined value Q% in the duty ratio of the first switch S is determined corresponding to the vicinity of the upper limit voltage Vom cape x in the step-down type operation, and the lower limit voltage Vom in the step-up type operation is determined.
If a specific value of 8% in the duty ratio of the second switch S2 is determined in correspondence with the vicinity of min, the output voltage Vo peak in a range lower and higher than the input voltage Vin, including the output voltage Vout equal to the input voltage Vin. can be obtained.

In addition, when changing the output voltage yo mountain in the decreasing direction, when the duty ratio of the second switch S2 is equal to or higher than the specific value 8%, the duty ratio of the second switch S2 is decreased and the second
The duty ratio of switch S2 is less than the specific value 8% and the first
When the duty ratio of switch S2 is equal to or higher than the predetermined value Q%,
The duty ratio of each switch S,, S2 is decreased, and the first
When the duty ratio of switch S is less than the predetermined value Q%,
This reduces the duty ratio of the switch S.

In addition, as the pulse generator PG, C
If a pulse with a duty ratio corresponding to the output of P is generated in synchronization with the output of the comparator controller CCP, a multipipulator etc. can be applied, and a frequency dividing circuit that divides the clock pulse can be used. , the frequency division operation may be controlled by the output of the comparison controller CCF.

In addition, when the calibrators DEC, DEC2 are configured with analog circuits, using a predetermined reactor wave detector and wave detector,
It is sufficient to detect the change in duty ratio as a change in frequency, and apply the output voltage to CP to the comparison controller according to the conditions.
The same effect can be obtained even if a partial pressure is applied, and various modifications are possible.

Incidentally, by detecting the output radio wave and changing the duty ratio of each switch S, , S2 based on the detection, it is possible to maintain the output current at a predetermined value.

As is clear from the above description, according to the present invention, with a simple configuration, output voltages in a range higher and lower than the input voltage can be freely obtained, and in particular, according to the second invention, output voltages that are equal to the input voltage can also be obtained. Since it is possible to obtain an output voltage with a continuous variation range, it is highly effective as a power supply circuit for various uses.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional power conversion circuit that is the basis of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the first invention, and FIG.
The figure is a block diagram showing a specific example of the tester in Figure 2,
FIG. 4 is a circuit diagram showing an embodiment of the second invention, and FIG. 5 is a circuit diagram showing an embodiment of the second invention.
The calibrator in the figure. 6 is a block diagram showing a specific example of the verification circuit in FIG. 5, and FIG. 7 is a time chart showing waveforms of various parts in FIG. 6. 1, 2...input terminal, 3,
4... Output terminal,... Hata streamline theory, S. ...First
Switch, S2...Second switch, CCP...Comparison controller, DEC,, DEC2...Verifier, G,,G3
...OR gate, G2, G4...AND gate, PG...
Pulse generator, Vim...input voltage, Vout...output voltage, Vr...reference voltage. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Scope of Claims] 1. A first switch provided in series to the input side of a blocking wire inserted into one line of the power supply circuit, and between the output side of the blocking wire and another line of the power supply circuit. Comparing means for controlling each of the switches by comparing the inserted second switch and the output voltage of the power supply circuit with a reference voltage and changing the on/off duty ratio; and a verification means for controlling the output supply of the comparison means to each of the switches, and when the output voltage is in an increasing direction and the duty ratio of the first switch is less than 100%, the duty ratio of the first switch is determined. and the duty ratio of the second switch is set to 0%, and when the output voltage is increasing and the duty ratio of the first switch is 100%, the duty ratio of the second switch is increased and the output voltage is decreased. When the output voltage is in the decreasing direction and the duty ratio of the second switch exceeds 0%, the duty ratio of the second switch is decreased, and when the output voltage is in the decreasing direction and the duty ratio of the second switch is 0%, the duty ratio of the second switch is A variable power supply circuit system characterized by reducing the duty ratio of one switch. 2. A first switch installed in series with the input side of the blocking wire inserted into one line of the power supply circuit, and a second switch inserted between the output side of the blocking wire and the other line of the power supply circuit. , a comparing means for comparing the output voltage of the power supply circuit with a reference voltage and controlling each of the switches by changing the on/off duty ratio; verifying means for controlling the output supply of the comparing means to increase the duty ratio of the first switch when the output voltage is increasing and the duty ratio of the first switch is less than a predetermined value; The duty ratio of the two switches is set to 0%, and when the output voltage is increasing and the duty ratio of the first switch is above the predetermined value, the first and second switches are turned on and off with a period in which they are simultaneously turned on. controlling and increasing the duty ratio of each of the switches, and when the output voltage is increasing and the duty ratio of the second switch exceeds a specific value, increasing the duty ratio of the second switch and increasing the duty ratio of the first switch. A variable power supply circuit system characterized in that the duty ratio of the switch is 100%, and when the output voltage is in a decreasing direction, the duty ratio is decreased in accordance with the duty ratio of each of the switches. 3. The variable power supply circuit system according to claim 2, characterized in that the test means for testing the duty ratio of each switch is one whose test output has a hysteresis characteristic with respect to changes in the duty ratio.