JPS60145691A - Semiconductor laser - Google Patents

Semiconductor laser

Info

Publication number
JPS60145691A
JPS60145691A JP218084A JP218084A JPS60145691A JP S60145691 A JPS60145691 A JP S60145691A JP 218084 A JP218084 A JP 218084A JP 218084 A JP218084 A JP 218084A JP S60145691 A JPS60145691 A JP S60145691A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
active layer
layers
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP218084A
Other languages
Japanese (ja)
Inventor
Kenichi Kobayashi
健一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP218084A priority Critical patent/JPS60145691A/en
Publication of JPS60145691A publication Critical patent/JPS60145691A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/04Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042Electrical excitation ; Circuits therefor
    • H01S5/0421Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
    • H01S5/0422Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers with n- and p-contacts on the same side of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • H01S5/2238Buried stripe structure with a terraced structure

Abstract

PURPOSE:To obtain the titled device which stably oscillates on single lateral mode at a low threshold value and is excellent in frequency characteristic by a method wherein the side surface of a stepwise section containing the first- third semiconductor layers is provided with a double hetero structure where an active layer is sandwiched by the first and second clad layers having forbidden widths larger than that of the active layer. CONSTITUTION:An insulation semiconductor substrate 10 is provided with step 40 containing a double hetero structure formed of the first semiconductor layer 50, second semiconductor layer 60, and third semiconductor layers 70a and 70b made of two layers. The forbidden band widths of the semiconductor layers 50, 70a, and 70b are not larger than that of the active layer 15, and the forbidden band width of the semiconductor layer 60 is larger than that of the active layer 15. The side surface of this step 40 is provided with the double hetero structure of a semiconductor laser consisting of the first clad layer 11, the active layer 15, and the second clad layer 12. The light emitting region of this laser turns into the active layer 15 on the side surface of the step 40.

Description

【発明の詳細な説明】 本発明は低しきい値で安定な単−横モードで発振し周波
数特性の優れた半導体レーザに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor laser that oscillates in a stable single transverse mode with a low threshold value and has excellent frequency characteristics.

半導体レーザとして、低しきい値で安定な単−横モード
発振することは、光通信や元情報処理用の光源として用
いる場合に重要な条件となり、また周波数特性も情報伝
達量、情報処理量等に関係し重要な要素となる。従来の
半導体レーザは、埋め込み構造を採用し、pn接合の逆
バイアスにより発光領域に有効に電流を注入して低しき
い値化を図っており、また周波数特性を良くするために
はpn逆バイアス接合の容量を低減することが重要であ
る。
As a semiconductor laser, stable single-transverse mode oscillation with a low threshold is an important condition when used as a light source for optical communication and original information processing, and the frequency characteristics also depend on the amount of information transmitted, information processing, etc. It is an important element related to Conventional semiconductor lasers employ a buried structure, and effectively inject current into the light emitting region by reverse biasing the pn junction to lower the threshold voltage. It is important to reduce the capacitance of the junction.

しかし、このpn逆バイアス接合の容量を低減するには
とのpn逆バイアス容量を形成するp形あるいはn形の
半導体層の不純物濃度(ドーピング濃度)を低減するこ
とであるが、これら半導体層の不純物濃度はレーザの静
特性の悪化2歩留りの悪化、温度特性等に影響を与える
ため容易に低減ができなかった。例えば、結晶成長中の
不純物のオートドーピングにより、n電流ブロック層の
薄膜化、およびp型への反転等の問題を生ずる。
However, in order to reduce the capacitance of this pn reverse bias junction, it is necessary to reduce the impurity concentration (doping concentration) of the p-type or n-type semiconductor layers that form the pn reverse bias capacitance. The impurity concentration cannot be easily reduced because it affects the static characteristics of the laser, the yield rate, and the temperature characteristics. For example, autodoping of impurities during crystal growth causes problems such as thinning of the n-current blocking layer and inversion to p-type.

また、pn逆バイアス接合部に低濃度層を導入すること
も有効ではあるが、BH槽構造大幅に変化させないため
には2層の厚さが薄い必要があり、空乏層を大幅に広げ
ることは出来なかった。
Also, although it is effective to introduce a low concentration layer into the pn reverse bias junction, the thickness of the two layers needs to be thin in order not to significantly change the BH tank structure, and it is difficult to widen the depletion layer significantly. I could not do it.

第1図は従来のこの種の半導体レーザの縦断面図であり
、絶縁性基板10上に形成された埋め込み構造の半導体
レーザを示す。活性層15に効率よく電流を注入するた
めにp形の埋め込み層16゜18の間にn形の電流ブロ
ック層17を備え、そこで形成されるpn接合の逆バイ
アスで中央のメサ80の両側以外の電流を阻止している
。そのため、pn逆バイアス接合容量をもっており、そ
の容量によってレーザの高周波特性が悪化している。
FIG. 1 is a vertical cross-sectional view of a conventional semiconductor laser of this type, showing a semiconductor laser having a buried structure formed on an insulating substrate 10. As shown in FIG. In order to efficiently inject current into the active layer 15, an n-type current blocking layer 17 is provided between the p-type buried layers 16 and 18, and the reverse bias of the pn junction formed there allows the current to be injected into the active layer 15 except on both sides of the central mesa 80. The current is blocked. Therefore, it has a pn reverse bias junction capacitance, and this capacitance deteriorates the high frequency characteristics of the laser.

このpn逆バイアス接合容量を低減するには、この接合
容量を形成するp層あるいはn層のドーピング濃度を低
減する事であるが、n型・の電流ブロック層エフのドー
ピングを減少させると電流ブロッキング層がオートドー
ピングによりとぎれることが生じる。また、n型ブロッ
ク層170層厚を増しオートドーピングを避けようとす
ると、n型ブロック層17が中央のメサ80の部分にも
積層しやすく問題を生じる。また、p形の埋め込み層1
6.18のドーピング量はある程度以下に減少させると
発振しきい値の上昇を1ねくことになる。
In order to reduce this pn reverse bias junction capacitance, it is necessary to reduce the doping concentration of the p layer or n layer that forms this junction capacitance, but if the doping of the n-type current blocking layer F is reduced, the current blocking Layer discontinuities occur due to autodoping. Furthermore, if an attempt is made to increase the thickness of the n-type block layer 170 to avoid autodoping, the n-type block layer 17 is likely to be stacked on the mesa 80 in the center, causing a problem. In addition, p-type buried layer 1
If the doping amount of 6.18 is reduced below a certain level, the oscillation threshold will increase by one level.

以上のように、pnの逆バイアスを形成する層の層厚及
びドーピング量を大幅に動かすことは出来ない。このた
めpn逆バイアス接合容量の大幅な低減は困難で高周波
特性が良くなかった。さらに、絶縁性基板10は電極を
上部に形成するために絶縁をもたせただけであった。
As described above, the layer thickness and doping amount of the layer forming the pn reverse bias cannot be changed significantly. Therefore, it was difficult to significantly reduce the pn reverse bias junction capacitance, and the high frequency characteristics were not good. Further, the insulating substrate 10 was only provided with insulation in order to form electrodes thereon.

本発明の目的は、このような問題点を解決し、低しきい
値で安定な単−横モード発振し周波数特性の優れた半導
体レーザを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and to provide a semiconductor laser that oscillates in a stable single-transverse mode with a low threshold and has excellent frequency characteristics.

本発明の半導体レーザの構成は、絶縁性半導体基板上に
、活性層よシ禁制帯幅が小さい第1の半導体層と、前記
活性層より禁制帯幅が大きい第2の半導体層と、前記活
性層より禁制帯幅が小さい数層からなる第3の半導体層
とを含む階段状のステップ部を設け、前記階段状のステ
ップ部の少なくとも側面上に前記活性層より禁制帯幅が
大きい第1および第2のクラッド層により前記活性層を
挾んだダブルへテロ構造を有することを特徴とする。
The structure of the semiconductor laser of the present invention includes, on an insulating semiconductor substrate, a first semiconductor layer having a smaller band gap than the active layer, a second semiconductor layer having a band gap larger than the active layer, and a second semiconductor layer having a band gap larger than the active layer. A step-like step portion including a third semiconductor layer consisting of several layers having a forbidden band width smaller than that of the active layer; It is characterized by having a double heterostructure in which the active layer is sandwiched between second cladding layers.

本発明の構成によれば、第1の半導体層、第2半導体層
、第3の半導体層が活性層に屈折率差を形成させ、その
屈折率導波路により単−横モード発振せしめる事ができ
る。さらに、その屈折率導波路幅はほぼ第2の半導体層
厚に階段状ステップ側面の傾斜角の正弦の逆数を掛けた
値であり、第2の半導体層厚で決定される。また、発光
領域である階段状ステップ側面の活性層へ、絶縁性基板
と第3の半導体層とによる電流ブロック効果により、効
率よく電流は注入される。また、この電流のブロックが
、絶縁性半導体基板で行われると共に、pn逆バイアス
接合においても行われるが、pn逆バイアス接合部分に
おいては、このpn逆バイアス接合を形成する層となる
第3の半導体層の層厚がレーザの静特性とほぼ無関係に
なるため、この第3の半導体層の層厚を増してこの層内
の不純物濃度に変化をもたせられるので、第3の半導体
層を層厚の厚い低濃度不純物層とすることが出来る。こ
のためpn逆バイアス接合容量を大幅に低減でき高周波
特性を改善できる。
According to the configuration of the present invention, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer form a refractive index difference in the active layer, and the refractive index waveguide can cause single-transverse mode oscillation. . Furthermore, the refractive index waveguide width is approximately the value obtained by multiplying the second semiconductor layer thickness by the reciprocal of the sine of the inclination angle of the stepped step side surface, and is determined by the second semiconductor layer thickness. Furthermore, current is efficiently injected into the active layer on the side surface of the stepped step, which is the light emitting region, due to the current blocking effect of the insulating substrate and the third semiconductor layer. In addition, this current blocking is performed in the insulating semiconductor substrate and also in the pn reverse bias junction. Since the layer thickness is almost independent of the static characteristics of the laser, it is possible to increase the thickness of this third semiconductor layer and change the impurity concentration in this layer. A thick low concentration impurity layer can be formed. Therefore, the pn reverse bias junction capacitance can be significantly reduced and the high frequency characteristics can be improved.

以下本発明を図面により詳細に説明する。The present invention will be explained in detail below with reference to the drawings.

第2図は本発明の実施例の断面構成図である。FIG. 2 is a cross-sectional configuration diagram of an embodiment of the present invention.

この実施例は、絶縁性半導体基板10の上に、第1の半
導体層50.第2の半導体層60及び2層よりなる第3
の半導体層70a 、70bで形成されるダブルへテロ
構造を含む階段状のステップ40を有するものである。
In this embodiment, a first semiconductor layer 50. a second semiconductor layer 60 and a third semiconductor layer made of two layers;
It has a stepped step 40 including a double heterostructure formed of semiconductor layers 70a and 70b.

このダブルへテロ構造を形成している第1の半導体層5
0及び第3の半導体層70a 、70b の禁制帯幅は
、活性層15の禁制帯幅より大きくなく、第2の半導体
層60の禁制帯幅は活性層15の禁制帯幅より大きい。
The first semiconductor layer 5 forming this double heterostructure
The forbidden band widths of the 0 and third semiconductor layers 70a and 70b are not larger than the forbidden band width of the active layer 15, and the forbidden band width of the second semiconductor layer 60 is larger than the forbidden band width of the active layer 15.

この階段状ステップ40の側面上に第1のクラッド層1
1、活性層15.第2のクラッド層12よりなる半導体
レーザのダブルへテロ構造を有している。
A first cladding layer 1 is formed on the side surface of this stepped step 40.
1. Active layer 15. It has a double heterostructure of a semiconductor laser consisting of a second cladding layer 12.

このレーザ発光領域は階段状ステップ40の側面上の活
性層15となる。なお、13はキャップ層、20.30
は電極である。
This laser emitting region becomes the active layer 15 on the side surface of the stepped step 40. In addition, 13 is a cap layer, 20.30
is an electrode.

この階段状ステップ40の底面上にある活性層15には
、絶縁性半導体基板10により電流は注入されず、また
、階段状ステップ40の上面上にある活性層15には第
2の半導体層60と第3の半導体層70a 、70b 
により形成されるpn接合逆バイアスにより電流は注入
されず、このため階段状ステップ40の側面上の活性層
15に有効に電流が注入される。
No current is injected into the active layer 15 on the bottom surface of the stepped step 40 by the insulating semiconductor substrate 10, and the second semiconductor layer 60 is injected into the active layer 15 on the top surface of the stepped step 40. and third semiconductor layers 70a and 70b
No current is injected due to the pn junction reverse bias formed by the pn junction, and therefore current is effectively injected into the active layer 15 on the side surface of the stepped step 40.

第3図は第2図の発光領域近傍の発振横モードを説明す
る模式図である。階段状ステップ40の側面の活性層1
5において、図中の部分A、dでは活性層近傍に活性層
15より禁制帯幅の小さい第1の半導体層50あるいは
第3の半導体層70a。
FIG. 3 is a schematic diagram illustrating the oscillation transverse mode near the light emitting region of FIG. 2. FIG. Active layer 1 on the side of stepped step 40
5, the first semiconductor layer 50 or the third semiconductor layer 70a, which has a smaller forbidden band width than the active layer 15, is located near the active layer in parts A and d in the figure.

70bが存在し、部分Bでは近傍に禁制帯幅の小さい半
導体層が存在しないし、また第1の半導体層50あるい
は第3の半導体層701での間隔は部分A、Cと比較し
て大きく、活性層15には階段状ステップ40の側面で
屈折率差が存在し単−横モードを発振する。
70b exists, and there is no semiconductor layer with a small forbidden band width nearby in portion B, and the spacing in the first semiconductor layer 50 or the third semiconductor layer 701 is larger than in portions A and C. The active layer 15 has a refractive index difference on the side surfaces of the stepped steps 40, and oscillates in a single transverse mode.

また、第3の半導体層70a、70bの不純物濃度及び
層厚は発振横モードに影臀しないため、層厚を厚くし不
純物濃度の小さい第3の半導体層70aと通常の不純物
濃度の第3の半導体層70bの2層に分けそれぞれ十分
な厚さをもたせる事ができるためその接合容量を低減で
きると共に、階段状ステップ40の下面は絶縁性基板1
0であるため容量は小さくなる。
In addition, since the impurity concentration and layer thickness of the third semiconductor layers 70a and 70b do not affect the oscillation transverse mode, the layer thickness is increased to form a third semiconductor layer 70a with a small impurity concentration and a third semiconductor layer 70a with a normal impurity concentration. Since the semiconductor layer 70b can be divided into two layers and each layer can have sufficient thickness, the junction capacitance can be reduced, and the lower surface of the stepped step 40 is formed on the insulating substrate 1.
Since it is 0, the capacity becomes small.

以下本実施例を具体例により説明する。This embodiment will be explained below using a specific example.

絶縁性G a A s基板10上に有機金属分解法(以
下MOCVD法という)を用いて第1の半導体層50と
なるp型Q a A s層を1μm、第2の半導体層6
0となるp型kl o、s Qa o、y A s層を
l μm 。
A p-type Q as layer that will become the first semiconductor layer 50 is formed on an insulating Ga As substrate 10 using a metal organic decomposition method (hereinafter referred to as MOCVD method), and a second semiconductor layer 6 is formed on the insulating Ga As substrate 10 to a thickness of 1 μm.
The p-type klo, s Qa o, y A s layer which becomes 0 is l μm.

第3の半導体層70aとなるノンドープのG a A 
3層1 μm 、第3の半導体層70bとなるn W 
(ja Ass層μmを連続成長した。屈折率導波路幅
を決定する第2の半導体層60の成長速度は200人/
min であり、非常に制御性に優れているため、安定
な単−横モード発振する屈折率導波路幅を容易に制御で
きる。このようにして作製したウェファを通常のホトリ
ングラフィと化学エツチングで少なく、之も第1の半導
体層50の途中まで、あるいQ;1全部、あるいはそれ
以上をウェファ内で部分的に除去し階段状ステップ40
を作製する。
Non-doped Ga A that becomes the third semiconductor layer 70a
3 layers with a thickness of 1 μm, n W which becomes the third semiconductor layer 70b
(ja Ass layer μm was continuously grown. The growth rate of the second semiconductor layer 60, which determines the refractive index waveguide width, was 200 people/
min, and has excellent controllability, so the width of the refractive index waveguide for stable single-transverse mode oscillation can be easily controlled. The thus produced wafer is subjected to conventional photolithography and chemical etching to partially remove part of the first semiconductor layer 50, or all or more of the first semiconductor layer 50 within the wafer. Stair step 40
Create.

以上のような工程を終えたウェファ上に2回目のMOC
VD法により、第1のクラッド層11と2のクラッド層
12となるAlo、Ga O,7A S層を2μm、ざ
らにキャップ層13を連続成長した。
The second MOC is applied to the wafer that has completed the above steps.
Alo, GaO, 7A S layers, which will become the first cladding layer 11 and the second cladding layer 12, have a thickness of 2 μm and a cap layer 13 is continuously grown by the VD method.

このMOCV、lJ法では、第3図に示すように、階段
上ステップの下面、上面及び側面に一様に成長する。次
に、この階段上ステップ上面に積層した層を第3の半導
体層7Qa 、70bを含めて、通常のホトリソグラフ
ィと化学エツチングで部分的に除去し、第1図に示した
ようにp側及びn側の電極20,30を形成しさらに配
線21.31を接続して素子化した。この際通常の絶縁
膜を用いて電極形成のため露出した段差側面は保護しで
ある。
In the MOCV and IJ methods, as shown in FIG. 3, the film grows uniformly on the bottom, top and side surfaces of the steps. Next, the layers laminated on the upper surface of the steps, including the third semiconductor layers 7Qa and 70b, are partially removed by ordinary photolithography and chemical etching, and the p-side and N-side electrodes 20 and 30 were formed, and wirings 21 and 31 were connected to form a device. At this time, a normal insulating film is used to protect the exposed stepped side surfaces for electrode formation.

この実施例におけるレーザ発振は、階段上ステップ−側
面の活性層における安定な単−横モードであり、発振し
きい値電流はl Q Q mhg度であり、またp、n
逆バイアス接合の容量は10pF以下であった。
The laser oscillation in this example is a stable single-transverse mode in the step-side active layer, and the oscillation threshold current is l Q Q mhg degrees, and p, n
The capacitance of the reverse bias junction was less than 10 pF.

この実施例は、GaAs Kはぼ格子整合したA I 
G a A s混晶系により構成したが、種々の混晶系
でも作製もできる。たとえば、GaAs基板に格子整合
するA/GaInP混晶系でも実混晶へるし、InP基
板上のI n Qa As P でも実施できる。
In this example, GaAs K is approximately lattice matched to A I
Although it is constructed using a GaAs mixed crystal system, it can also be manufactured using various mixed crystal systems. For example, an A/GaInP mixed crystal system lattice-matched to a GaAs substrate can be used as a real mixed crystal, or an InP substrate can be formed using In Qa As P.

さらに、活性層の半導体層の禁制帯幅が半導体基板の禁
制帯幅より大きい結晶系においては、例えば、この実施
例のQ a A s基板上のA lG a A s系、
GaAs基板上のkit Ga I n P糸にオイテ
は、第4図の第2の実施例に示すように、第2図におけ
る第1の半導体層50を含まない構造が可能となり、結
晶成長で作製する半導体層を1つ減らすことが出来るが
、この場合も同様の特性を得る事ができる。
Furthermore, in a crystal system in which the forbidden band width of the semiconductor layer of the active layer is larger than that of the semiconductor substrate, for example, the A lGa As system on the Q a As substrate of this example,
As shown in the second embodiment of FIG. 4, the structure of the kit Ga I n P yarn on the GaAs substrate does not include the first semiconductor layer 50 in FIG. 2, and can be fabricated by crystal growth. Although the number of semiconductor layers can be reduced by one, similar characteristics can be obtained in this case as well.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の絶縁性基板を用いた半導体レーザの断面
図、第2図は本発明の第1の実施例の断面図、第3図は
第2図の実施例の発振モードを示した模式図、第4図は
本発明の第2の実施例の断面図である。図において 10・・・・・・絶縁性半導体基板、11・・・・・・
第1のクラッド層、12・・・・・・第2のクラッド層
、13・・・・・・キャップ層、15・・・・・・活性
層、16・・・・・・電流閉込めN117・・・・・・
電流ブロック層、18・・・・・・埋込み層、19・・
・・・・電極形成層、20.30・・・・・・電極、2
1.31・・・・・・配線、40・・・・・・階段状ス
テップ、50・・・・・・第1の半導体層、60・・・
・・・第2の半導体JWI% 70a 、70b ・・
・・・・第3の半導体層、80・・・・・・メサ 卒1回 Jθ 峯4圀
Figure 1 is a sectional view of a conventional semiconductor laser using an insulating substrate, Figure 2 is a sectional view of a first embodiment of the present invention, and Figure 3 shows the oscillation mode of the embodiment of Figure 2. The schematic diagram, FIG. 4, is a sectional view of a second embodiment of the present invention. In the figure, 10... insulating semiconductor substrate, 11...
First cladding layer, 12... Second cladding layer, 13... Cap layer, 15... Active layer, 16... Current confinement N117・・・・・・
Current blocking layer, 18...Buried layer, 19...
... Electrode forming layer, 20.30 ... Electrode, 2
1.31...Wiring, 40...Staircase step, 50...First semiconductor layer, 60...
...Second semiconductor JWI% 70a, 70b...
...Third semiconductor layer, 80...Mesa graduate once Jθ Mine 4koku

Claims (1)

【特許請求の範囲】 1)絶縁性半導体基板上に、活性層よりも禁制帯幅が小
さい第1の半導体層と、前記活性層より禁制帯幅が大き
い第2の半導体層と、前記活性層より禁制帯幅が小さく
数層からなる第3の半導体層とを含む階段状のステップ
部を設け、このステップ部の少なくとも側面上に前記活
性層より禁制帯幅が大きい第1および第2のクラッド層
により前記活性層を挾んだダブルへテロ構造を有するこ
とを特徴とする半導体レーザ。 幻 絶縁性半導体基板が活性層の禁制帯幅より小さいも
のからなるとき、この絶縁性半導体基板が第1の半導体
層を兼ねることによりこの第1の半導体層を不要とした
ことを特徴とする特許請求の範囲第1項記載の半導体レ
ーザ。
[Scope of Claims] 1) On an insulating semiconductor substrate, a first semiconductor layer having a narrower band gap than the active layer, a second semiconductor layer having a band gap larger than the active layer, and the active layer. A step-like step portion including a third semiconductor layer having a smaller forbidden band width and consisting of several layers is provided, and first and second claddings having a larger forbidden band width than the active layer are provided on at least a side surface of the step portion. A semiconductor laser characterized in that it has a double heterostructure in which the active layer is sandwiched between layers. Illusion A patent characterized in that when the insulating semiconductor substrate is made of a material smaller than the forbidden band width of the active layer, the insulating semiconductor substrate also serves as the first semiconductor layer, thereby eliminating the need for the first semiconductor layer. A semiconductor laser according to claim 1.
JP218084A 1984-01-10 1984-01-10 Semiconductor laser Pending JPS60145691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP218084A JPS60145691A (en) 1984-01-10 1984-01-10 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP218084A JPS60145691A (en) 1984-01-10 1984-01-10 Semiconductor laser

Publications (1)

Publication Number Publication Date
JPS60145691A true JPS60145691A (en) 1985-08-01

Family

ID=11522159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP218084A Pending JPS60145691A (en) 1984-01-10 1984-01-10 Semiconductor laser

Country Status (1)

Country Link
JP (1) JPS60145691A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62296591A (en) * 1986-06-17 1987-12-23 Nec Corp Semiconductor laser

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62296591A (en) * 1986-06-17 1987-12-23 Nec Corp Semiconductor laser
JPH0543309B2 (en) * 1986-06-17 1993-07-01 Nippon Electric Co

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