JPH06291414A - Surface emitting type semiconductor laser element - Google Patents

Surface emitting type semiconductor laser element

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Publication number
JPH06291414A
JPH06291414A JP9854593A JP9854593A JPH06291414A JP H06291414 A JPH06291414 A JP H06291414A JP 9854593 A JP9854593 A JP 9854593A JP 9854593 A JP9854593 A JP 9854593A JP H06291414 A JPH06291414 A JP H06291414A
Authority
JP
Japan
Prior art keywords
layer
electrode
semiconductor laser
type semiconductor
optical confinement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9854593A
Other languages
Japanese (ja)
Inventor
Toru Fukushima
徹 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP9854593A priority Critical patent/JPH06291414A/en
Publication of JPH06291414A publication Critical patent/JPH06291414A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a surface emitting type semiconductor laser element, which has a low threshold current and is capable of making a high-speed response. CONSTITUTION:A lower optical confinement layer 32, a lower clad layer 33, an active layer 34 and an upper optical confinement layer 40 are laminated in order on a semi-insulative semiconductor substrate 31, an N electrode 41 is provided on the layer 40, P electrodes 42 are provided on lower clad layers 36 and 37 and holes are injected in the layer 34 through the lower surface or the side surfaces of the layer 34 without going through the layer 32.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、光通信、光計測などに
用いられる高速応答可能な面発光型半導体レーザ素子に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface-emitting type semiconductor laser device capable of high-speed response, which is used for optical communication, optical measurement and the like.

【0002】[0002]

【従来技術】面発光型半導体レーザ素子は、光インター
コネクションや、並列伝送などに用いられる有望な素子
として注目され、現在までに、幾つかの構造が提案され
ている。例えば、 1)図2に示す構造では、活性層3に温度特性の良いI
nGaAs歪み量子井戸層を用い、その上下に配置され
たGaAs−AlAsの対よりなる半導体多層反射膜
2、4とともにn−GaAs基板1上に成長させ、エッ
チングにより発光部分のメサを形成している。しかし、
この構造では、p電極7側の半導体多層反射膜4の有す
る高い抵抗(GaAs−AlAs界面に生ずるバンドギ
ャップ差によるものである)によって、活性層温度が上
昇するため、発振しきい値電流が上昇し、効率が低下す
るなどの問題点があった(文献1参照)。5はGaAs
−AlAsの対よりなる半導体多層反射膜、6はポリイ
ミド絶縁層、8は非反射膜である。9は光取り出し窓を
有するn電極である。 2)この傾向は光通信に用いられる波長1.3〜1.5
μm付近で発光するInP系材料において特に著しい。
例えば、図3に示すように、埋め込み型面発光半導体レ
ーザ素子においても、しきい値電流は100mA以上と
高く、実用上問題があった。また、現在まで、室温連続
発振はInP系面発光半導体レーザ素子においては実現
していない(文献2、3参照)。図中、11はn−Ga
As基板、12はn−GaAlAsクラッド層?、13
はn−GaAlAs/AlAs半導体多層反射膜、14
はp−GaAs活性層、15はp−GaAlAsクラッ
ド層、16はn−GaAs電流狭窄層、17はp−Ga
As電流狭窄層、18はp−GaAlAsキャップ層、
19はp電極、20はn電極である。 3)メサ型面発光半導体レーザ素子においては、図4に
示すように、反射膜26、27として誘電体多層膜を利
用し、p電極28をp−InPバッファ層23上面に直
接設けることで、極力直列抵抗を低減した構造になって
いる。これにより室温での発振しきい値も50mA(パ
ルス駆動)まで低減されたが、まだ連続発振にはいたっ
ていない。その主たる理由は、薄いp−InPクラッド
層23の有する抵抗値と、メサ形状による放熱の悪さ、
注入電流密度が不均一であることなどである(文献4参
照)。図中、21はp−InP基板、22はp−InG
aAsPストップエッチ層、24はp−InGaAsP
活性層、25はn−InPクラッド層、29はn電極、
30はポリイミド絶縁層である。 文献1:48th Device Research Conference., 53A-1, J
une,1990. 文献2:IEEE J.Quantum.Electron., QE-24, No.9, pp.
1845-1855,Sept.1988. 文献3:48th Device Research Conference., Post Dea
dline Paper, 5B-2,June,1990. 文献4:49th Device Research Conference., Post Dea
dline Paper, 3A-8,June,1991.
2. Description of the Related Art Surface-emitting type semiconductor laser devices have attracted attention as promising devices used for optical interconnection, parallel transmission, etc., and several structures have been proposed so far. For example, 1) In the structure shown in FIG.
An nGaAs strained quantum well layer is used and grown on an n-GaAs substrate 1 together with semiconductor multilayer reflective films 2 and 4 made of a pair of GaAs-AlAs arranged above and below the nGaAs strained quantum well layer, and a mesa of a light emitting portion is formed by etching. . But,
In this structure, the active layer temperature rises due to the high resistance of the semiconductor multilayer reflective film 4 on the p-electrode 7 side (due to the bandgap difference generated at the GaAs-AlAs interface), so the oscillation threshold current rises. However, there is a problem that the efficiency is lowered (see Document 1). 5 is GaAs
A semiconductor multilayer reflective film made of a pair of -AlAs, 6 is a polyimide insulating layer, and 8 is a non-reflective film. Reference numeral 9 is an n electrode having a light extraction window. 2) This tendency shows that the wavelength used for optical communication is 1.3 to 1.5.
This is particularly remarkable in InP-based materials that emit light in the vicinity of μm.
For example, as shown in FIG. 3, even in the embedded surface emitting semiconductor laser device, the threshold current is as high as 100 mA or more, which is a practical problem. Up to now, room temperature continuous oscillation has not been realized in InP-based surface emitting semiconductor laser devices (see References 2 and 3). In the figure, 11 is n-Ga
As substrate, 12 is n-GaAlAs clad layer? , 13
Is an n-GaAlAs / AlAs semiconductor multilayer reflective film, 14
Is a p-GaAs active layer, 15 is a p-GaAlAs cladding layer, 16 is an n-GaAs current confinement layer, and 17 is p-Ga.
As current confinement layer, 18 is p-GaAlAs cap layer,
Reference numeral 19 is a p-electrode, and 20 is an n-electrode. 3) In the mesa-type surface-emitting semiconductor laser device, as shown in FIG. 4, a dielectric multilayer film is used as the reflection films 26 and 27, and the p electrode 28 is directly provided on the upper surface of the p-InP buffer layer 23. The structure reduces the series resistance as much as possible. As a result, the oscillation threshold value at room temperature was also reduced to 50 mA (pulse drive), but continuous oscillation has not yet been reached. The main reasons are the resistance value of the thin p-InP cladding layer 23 and the poor heat dissipation due to the mesa shape.
For example, the injection current density is non-uniform (see Reference 4). In the figure, 21 is a p-InP substrate and 22 is a p-InG substrate.
aAsP stop etch layer, 24 is p-InGaAsP
An active layer, 25 is an n-InP clad layer, 29 is an n electrode,
30 is a polyimide insulating layer. Reference 1: 48th Device Research Conference., 53A-1, J
une, 1990. Reference 2: IEEE J. Quantum. Electron., QE-24, No. 9, pp.
1845-1855, Sept. 1988. Reference 3: 48th Device Research Conference., Post Dea
dline Paper, 5B-2, June, 1990. Reference 4: 49th Device Research Conference., Post Dea
dline Paper, 3A-8, June, 1991.

【0003】[0003]

【発明が解決しようとする課題】上述のような従来技術
の問題点を整理すると、次のようになる。即ち、 1)半導体多層膜は同一成長装置内で一時に形成でき、
しかも膜厚制御性が良好なので、この種の面発光半導体
レーザ素子の反射膜として良く利用されるが、p電極側
の半導体多層膜の抵抗値は高くなる。特に、InP系多
層膜の場合に、この抵抗値は高くなる。 2)キャビティを形成する際、従来のごときpn接合に
よる電流ブロック層を用いた埋め込み構造では、大きな
寄生容量が発生し、高速変調が不可能になる。 3)文献4の例では、高速変調も可能であるが、メサ型
の活性層24の熱放散が悪く、特性が劣化する。また、
活性層24内の電流はp電極28に近い活性層24周辺
部に集中し、活性層24中央部の電流密度が減少するた
め、光電界との重なりが減少するので、損失が増加、し
きい値電流が増大してしまう。
The problems of the prior art as described above can be summarized as follows. That is, 1) the semiconductor multilayer film can be formed at the same time in the same growth apparatus,
Moreover, since the film thickness controllability is good, it is often used as a reflective film of this type of surface emitting semiconductor laser device, but the resistance value of the semiconductor multilayer film on the p-electrode side becomes high. Particularly, in the case of InP-based multilayer film, this resistance value becomes high. 2) When forming a cavity, in a conventional buried structure using a current blocking layer with a pn junction, a large parasitic capacitance is generated and high-speed modulation becomes impossible. 3) In the example of Reference 4, high-speed modulation is possible, but the heat dissipation of the mesa-type active layer 24 is poor and the characteristics deteriorate. Also,
The current in the active layer 24 is concentrated in the peripheral portion of the active layer 24 close to the p-electrode 28, and the current density in the central portion of the active layer 24 is reduced. The value current increases.

【0004】[0004]

【課題を解決するための手段】本発明は上記問題点を解
決した面発光型半導体レーザ素子を提供するもので、半
絶縁性半導体基板上に下部光閉じ込め層、下部クラッド
層、活性層および上部光閉じ込め層が順次積層され、n
電極は上部光閉じ込め層上に設けられ、p電極は下部ク
ラッド層上に設けられ、正孔は下部光閉じ込め層を経ず
に活性層下面ないし側面から活性層に注入されることを
特徴とするものである。
SUMMARY OF THE INVENTION The present invention provides a surface-emitting type semiconductor laser device which solves the above problems, and includes a lower optical confinement layer, a lower cladding layer, an active layer and an upper layer on a semi-insulating semiconductor substrate. Light confinement layers are sequentially stacked, and n
The electrode is provided on the upper optical confinement layer, the p-electrode is provided on the lower clad layer, and holes are injected into the active layer from the lower surface or the side surface of the active layer without passing through the lower optical confinement layer. It is a thing.

【0005】[0005]

【作用】上述のように、p電極が下部クラッド層上に設
けられ、移動度の低い正孔が下部光閉じ込め層を経ずに
活性層下面ないし側面から活性層に注入されると、注入
電流は活性層に均一に注入され、しかも、抵抗の高い下
部光閉じ込め層を通らないため、素子の直列抵抗は低減
する。また、n、p各電極は対向せずに基板面上に形成
されているため、pn接合などの浮遊容量も存在せず、
高速応答特性も可能になる。
As described above, when the p-electrode is provided on the lower clad layer and holes having low mobility are injected into the active layer from the lower surface or the side surface of the active layer without passing through the lower optical confinement layer, the injection current is reduced. Is uniformly injected into the active layer and does not pass through the high-resistance lower optical confinement layer, so that the series resistance of the device is reduced. Further, since the n and p electrodes are formed on the substrate surface without facing each other, there is no stray capacitance such as a pn junction,
High-speed response characteristics are also possible.

【0006】[0006]

【実施例】以下、図面に示した実施例に基づいて本発明
を詳細に説明する。図1(a)、(b)はそれぞれ、本
発明にかかる面発光型半導体レーザ素子の一実施例の断
面図と上面図である。この構造は、本発明者が先に特願
平4−105388号にて提案した量子井戸半導体レー
ザ素子(通常のへき開端面発光型)と同様なものであ
る。本実施例の素子は以下の工程で製作した。即ち、 1)先ず、有機金属気相成長(MOCVD)法などによ
り、半絶縁性InP基板31上に、同じく半絶縁性半導
体多層膜32(バンドギャップ波長λg =1.4μmの
InGaAsP層2000Åと、InP層2000Åを
30対積層したもの)、1μm厚さの5×1017cm-3
程度にZnをドープしたp−InP層33、0.6μm
厚さのアンドープInGaAsP活性層34(バンドギ
ャップ波長λg =1.5μm)、0.2μm厚さのアン
ドープInP層35を順次エピタキシャル成長させる。 2)次いで、アンドープInP層35上に、SiO2
どの薄膜をプラズマCVD法などにより形成し、フォト
リソグラフィにより径4μmの円形状に加工する。 3)次いで、この円形状のSiO2 膜をマスクとして、
半絶縁性半導体多層膜32表面に達する化学エッチング
を行い、円形状メサを形成する。 4)次いで、前記SiO2 膜を選択成長マスクとして、
第2回目の有機金属気相成長により、5×1017cm-3
程度にZnをドープしたp−InP層36、1×1019
cm-3以上にZnをドープしたp−InGaAsP層3
7(バンドギャップ波長λg =1.3μm)、電流狭窄
用のFeをドープした半絶縁性InP層38を成長させ
て、先に加工した円形メサの周囲を埋め込む。 5)次いで、SiO2 マスクを除去した後、第3回目の
有機金属気相成長により、1×1018cm-3程度のキャ
リア濃度を有するn−InP層39、半絶縁性半導体多
層膜32と同じ構成の、しかし1×1018cm-3程度に
ドープしたn型半導体多層膜40を形成する。さらに、
直径10μm程度のn電極41を形成し、このn電極4
1をマスクとしてp−InGaAsP層37までエッチ
ングしてメサを形成し、このメサの周囲にp電極42を
形成する。 本実施例では、注入電流はp電極42から、半絶縁性半
導体多層膜32を通らずに、下部クラッド層であるp−
InP層33、36を通り、InGaAsP活性層34
の下面と側面から注入される。従って、注入電流は活性
層34内に均一に注入される。また、注入電流は半絶縁
性InP層38により狭窄され、n電極41とp電極4
2は対向していないため、高速応答特性が損なわれるこ
とがない。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. 1A and 1B are a cross-sectional view and a top view of an embodiment of a surface emitting semiconductor laser device according to the present invention. This structure is similar to the quantum well semiconductor laser device (normal cleaved edge emitting type) proposed by the present inventor in Japanese Patent Application No. 4-105388. The device of this example was manufactured by the following steps. That is, 1) First, a semi-insulating semiconductor multilayer film 32 (an InGaAsP layer 2000Å having a band gap wavelength λ g = 1.4 μm) is also formed on a semi-insulating InP substrate 31 by a metal organic chemical vapor deposition (MOCVD) method or the like. , 30 pairs of InP layers 2000 Å), 1 μm thick 5 × 10 17 cm −3
Zn-doped p-InP layer 33, 0.6 μm
An undoped InGaAsP active layer 34 (bandgap wavelength λ g = 1.5 μm) having a thickness and an undoped InP layer 35 having a thickness of 0.2 μm are sequentially epitaxially grown. 2) Next, a thin film of SiO 2 or the like is formed on the undoped InP layer 35 by the plasma CVD method or the like, and processed into a circular shape having a diameter of 4 μm by photolithography. 3) Next, using this circular SiO 2 film as a mask,
Chemical etching that reaches the surface of the semi-insulating semiconductor multilayer film 32 is performed to form a circular mesa. 4) Next, using the SiO 2 film as a selective growth mask,
5 × 10 17 cm −3 by the second metalorganic vapor phase epitaxy
Zn-doped p-InP layer 36, 1 × 10 19
p-InGaAsP layer 3 doped with Zn at cm -3 or more
7 (bandgap wavelength λ g = 1.3 μm), a Fe-doped semi-insulating InP layer 38 for current confinement is grown to fill the periphery of the previously processed circular mesa. 5) Next, after removing the SiO 2 mask, an n-InP layer 39 having a carrier concentration of about 1 × 10 18 cm −3 and a semi-insulating semiconductor multilayer film 32 are formed by the third metal organic chemical vapor deposition. An n-type semiconductor multilayer film 40 having the same structure but doped to about 1 × 10 18 cm −3 is formed. further,
An n-electrode 41 having a diameter of about 10 μm is formed, and the n-electrode 4
1 is used as a mask to etch the p-InGaAsP layer 37 to form a mesa, and a p-electrode 42 is formed around the mesa. In the present embodiment, the injected current does not pass through the semi-insulating semiconductor multilayer film 32 from the p-electrode 42, but is p- which is the lower cladding layer.
The InGaAsP active layer 34 passes through the InP layers 33 and 36.
Is injected from the bottom and sides. Therefore, the injection current is uniformly injected into the active layer 34. The injected current is confined by the semi-insulating InP layer 38, and the n-electrode 41 and the p-electrode 4
Since Nos. 2 do not face each other, high-speed response characteristics are not impaired.

【0007】[0007]

【発明の効果】以上説明したように本発明によれば、半
絶縁性半導体基板上に下部光閉じ込め層、下部クラッド
層、活性層および上部光閉じ込め層が順次積層され、n
電極は上部光閉じ込め層上に設けられ、p電極は下部ク
ラッド層上に設けられ、正孔は下部光閉じ込め層を経ず
に活性層下面ないし側面から活性層に注入されるため、
しきい値電流が低く、高速応答が可能な面発光型半導体
レーザ素子が得られるという優れた効果がある。
As described above, according to the present invention, a lower optical confinement layer, a lower cladding layer, an active layer and an upper optical confinement layer are sequentially stacked on a semi-insulating semiconductor substrate,
The electrode is provided on the upper optical confinement layer, the p electrode is provided on the lower clad layer, and holes are injected into the active layer from the lower surface or the side surface of the active layer without passing through the lower optical confinement layer.
There is an excellent effect that a surface-emitting type semiconductor laser device having a low threshold current and capable of high-speed response can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)、(b)はそれぞれ、本発明にかかる面
発光型半導体レーザ素子の一実施例の断面図と上面図で
ある。
1A and 1B are respectively a cross-sectional view and a top view of an embodiment of a surface-emitting type semiconductor laser device according to the present invention.

【図2】従来の面発光型半導体レーザ素子の断面図であ
る。
FIG. 2 is a sectional view of a conventional surface-emitting type semiconductor laser device.

【図3】従来の他の面発光型半導体レーザ素子の断面斜
視図である。
FIG. 3 is a sectional perspective view of another conventional surface-emitting type semiconductor laser device.

【図4】従来のさらなる他の面発光型半導体レーザ素子
の断面図である。
FIG. 4 is a sectional view of still another conventional surface-emitting type semiconductor laser device.

【符号の説明】[Explanation of symbols]

31 InP基板 32、40 半導体多層膜 33、36 p−InP層 34 InGaAsP活性層 35 InP層 37 p−InGaAsP層 38 半絶縁性InP層 39 n−InP層 41 n電極 42 p電極 31 InP substrate 32, 40 Semiconductor multilayer film 33, 36 p-InP layer 34 InGaAsP active layer 35 InP layer 37 p-InGaAsP layer 38 Semi-insulating InP layer 39 n-InP layer 41 n-electrode 42 p-electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半絶縁性半導体基板上に下部光閉じ込め
層、下部クラッド層、活性層および上部光閉じ込め層が
順次積層され、n電極は上部光閉じ込め層上に設けら
れ、p電極は下部クラッド層上に設けられ、正孔は下部
光閉じ込め層を経ずに活性層下面ないし側面から活性層
に注入されることを特徴とする面発光型半導体レーザ素
子。
1. A lower optical confinement layer, a lower clad layer, an active layer and an upper optical confinement layer are sequentially stacked on a semi-insulating semiconductor substrate, an n-electrode is provided on the upper optical confinement layer, and a p-electrode is a lower clad. A surface-emitting type semiconductor laser device provided on the layer, wherein holes are injected into the active layer from the lower surface or side surfaces of the active layer without passing through the lower optical confinement layer.
JP9854593A 1993-03-31 1993-03-31 Surface emitting type semiconductor laser element Pending JPH06291414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9854593A JPH06291414A (en) 1993-03-31 1993-03-31 Surface emitting type semiconductor laser element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9854593A JPH06291414A (en) 1993-03-31 1993-03-31 Surface emitting type semiconductor laser element

Publications (1)

Publication Number Publication Date
JPH06291414A true JPH06291414A (en) 1994-10-18

Family

ID=14222665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9854593A Pending JPH06291414A (en) 1993-03-31 1993-03-31 Surface emitting type semiconductor laser element

Country Status (1)

Country Link
JP (1) JPH06291414A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002344087A (en) * 2001-05-11 2002-11-29 Nippon Telegr & Teleph Corp <Ntt> SEMI-INSULATING InP SUBSTRATE AND SEMICONDUCTOR OPTICAL ELEMENT AS WELL AS METHOD FOR FORMING SEMICONDUCTOR THIN FILM
US7974327B2 (en) 2006-03-14 2011-07-05 Furukawa Electric Co., Ltd. Surface emitting laser element array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002344087A (en) * 2001-05-11 2002-11-29 Nippon Telegr & Teleph Corp <Ntt> SEMI-INSULATING InP SUBSTRATE AND SEMICONDUCTOR OPTICAL ELEMENT AS WELL AS METHOD FOR FORMING SEMICONDUCTOR THIN FILM
US7974327B2 (en) 2006-03-14 2011-07-05 Furukawa Electric Co., Ltd. Surface emitting laser element array

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