JPS60145652A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60145652A JPS60145652A JP59002954A JP295484A JPS60145652A JP S60145652 A JPS60145652 A JP S60145652A JP 59002954 A JP59002954 A JP 59002954A JP 295484 A JP295484 A JP 295484A JP S60145652 A JPS60145652 A JP S60145652A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- mask alignment
- semiconductor substrate
- mask
- alignment pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Semiconductor Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、例えば半導体基板上のエビ抵抗部分にトリ
ミング工程で写真製版をする時の、マスク合わせパター
ンに目盛りを付けることを特徴とする半導体装置の製造
方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device characterized in that a scale is attached to a mask alignment pattern when, for example, photolithography is performed on a resistive portion on a semiconductor substrate in a trimming process. The present invention relates to a manufacturing method.
従来、この種の方法として第１図に示すものがある。第
１図において、１は半導体基板上のマスク合わせパター
ン、２はこのマスク合わせパターン１に重ね合わせたト
リミングマスクのマスク合わせパターンである。３はエ
ビ抵抗部分の素子パターンであり、４＆まエビ抵抗部分
上のトリミングマスクのパターンである。A conventional method of this type is shown in FIG. In FIG. 1, 1 is a mask alignment pattern on a semiconductor substrate, and 2 is a mask alignment pattern of a trimming mask superimposed on this mask alignment pattern 1. In FIG. 3 is an element pattern of the shrimp resistance portion, and 4 is a trimming mask pattern on the shrimp resistance portion.
次忙操作匠ついて説明する。エビ抵抗を形成しＬ後、抵
抗値を測定し、所定の許容値内に入っていない場合Ｋ）
リミング工程を行う。その場合、第１図（ａ）のように
半導体基板上のマスク合わせバクーンＩＫ、トリミング
用マスクのマスク合わせパターン２を重ね合わせる。次
いでエビ抵抗部分の素子バクーン３上のトリミングバｐ
−７４ｙ＜、測定結果のデータに即した寸法だけ目視に
より、目合わせて第１図（ｂ） ７見ながら第１図（ｄ
）のようＶｃｘ／４ 左にずらして写真製版を行ってい
た。Next, I will explain about the busy operation technique. After forming the shrimp resistance, measure the resistance value, and if it is not within the specified tolerance value K)
Perform the rimming process. In that case, as shown in FIG. 1(a), the mask alignment pattern IK on the semiconductor substrate and the mask alignment pattern 2 of the trimming mask are superimposed. Next, remove the trimming pad on the element Bakun 3 of the shrimp resistance part.
-74y<, visually check only the dimensions according to the data of the measurement results, and match them to figure 1 (b).
), photoengraving was performed by shifting Vcx/4 to the left.
しかし、実際は目視によって行ったため、誤差が含ま２
１工いる。第１図（ｃ）Ｇｊ、その時の両マスク合わせ
パターン１，２の位置である、
従来のトリミング工程の写真製版の方法は以上の！５Ｖ
ｃ行ｈｎていたので、マスク合わせパターン１．２で１
度確認した後、エビ抵抗部分の素子パターン３７目視し
なから、目合わせｔ″１−らさなけｌばならず、作業能
率も悪く、作業者による誤差も生じ、マスク合わせ精度
、再現性、歩留の低下などの欠点があっに０
〔発明の概要〕
この発明は、上記のような従来のものの欠点を除去する
ためになさｔｔ ｒ、−もので、トリミング用マスクの
マスク合わせパターンまｋは半導体基板とのマスク合せ
パターンに、測定結果のデータに即した寸法だけマスク
をすらてことかできるように、目盛ｔつけること匠より
、マスク合わせ精度１作業者間による再現性２作業能率
１歩留の向上を目的とした半導体装置の製造方法を提供
するものである。However, since this was actually done by visual inspection, there may be errors.
It takes 1 car. Figure 1 (c) Gj, the positions of both mask alignment patterns 1 and 2 at that time.The conventional photolithography method of the trimming process is as described above! 5V
Since there were c rows hn, mask alignment pattern 1.2 was 1.
After checking the accuracy, it is necessary to visually check the element pattern 37 of the shrimp resistance part and then align it t''1-, which leads to poor work efficiency and errors caused by the operator, resulting in poor mask alignment accuracy and reproducibility. [Summary of the Invention] The present invention was made to eliminate the drawbacks of the conventional products as described above, and it is a method for improving the mask alignment pattern of a trimming mask. To make it possible to align the mask with the semiconductor substrate by the dimensions that match the measurement result data, the master craftsman has added a scale t to the mask alignment pattern with the semiconductor substrate. The present invention provides a method for manufacturing a semiconductor device with the aim of improving yield.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第２図（ａ）〜（ｄ）はこの発明の一実施例を説明する
ための主訣段１３！−における状ａｉ示す平面図で、１
１は半導体基板上のマスク合わせパターン、１２はこの
半導体基板上のマスク合わせパターン１１に重ね合わせ
罠目盛り付きのマスク合わせバター／で、１２′Ｅ丁目
盛り乞示す。マスク合わせバク−７１２の場合、一段ず
ら丁と、エビ抵抗パターンはｒ／４ ずｎるように設計
しである。１３はエビ抵抗部分の素子パターンであり、
１４は前記エビ抵抗部分の素子パターン１３上のトリミ
ングマスクのパターンである。第２図（ｃ）は目盛り伺
きのマスク合わせパターンを１膜圧にずらしてマスク合
わせをした時の図であり、このようにして合わすとエビ
抵抗の素子パターン１３は第２図（ｄ）のよ５に正しく
ｌ／４ずれて写真製版さｊることになる。FIGS. 2(a) to 2(d) are key points 13 for explaining one embodiment of the present invention! - A plan view showing the state ai at 1
1 is a mask alignment pattern on a semiconductor substrate, and 12 is a mask alignment butter/with a trap scale overlapping the mask alignment pattern 11 on the semiconductor substrate, and 12'E-th mark is shown. In the case of the mask matching Baku-712, the shrimp resistance pattern is designed to have a single-stage staggered pattern and an r/4 step. 13 is the element pattern of the shrimp resistance part,
14 is a pattern of a trimming mask on the element pattern 13 of the shrimp resistance portion. FIG. 2(c) is a diagram when the mask alignment pattern according to the scale is shifted by one film thickness and the mask alignment is performed. When aligned in this way, the element pattern 13 of the shrimp resistor is as shown in FIG. 2(d). The photoengraving process will be performed with the correct l/4 deviation.
次に＃作について説明する。半導体基板上のマスク合わ
せパターン１１に、トリミング用マスクのマスク合わせ
パターン１２ＶｌＫね合わせる。このときてでに測定結
果のデータに即しに目盛分だけマスクのマスク合わせパ
ターン１２をすらしてノロ、ね合わせ写真製版ケー［る
。この手法ケ用いると、作業者間による不均一性等上記
の欠点等が除去さｒる。Next, I will explain #work. The mask alignment pattern 12VlK of the trimming mask is aligned with the mask alignment pattern 11 on the semiconductor substrate. At this time, the mask alignment pattern 12 of the mask is smoothed by the scale according to the data of the measurement results, and the photolithographic process is carried out. When this technique is used, the above-mentioned drawbacks such as non-uniformity among workers are eliminated.
なお、上記実施例ではエピタキシャル成長させた半導体
基板上のエビ抵抗部分のトリミング工程を示したが、イ
オン注入乞した半導体基板上の動作領域でも同じである
。In the above embodiment, the process of trimming the resistor portion on the epitaxially grown semiconductor substrate was shown, but the same process can be applied to the operation region on the semiconductor substrate that has undergone ion implantation.
また、上記実施例ではトリミングマスクのマスク合わせ
パターン１２に目盛１２′ケつけたか、半導体基板上の
１スク合わせパターン１１Ｖｃ前工程で目盛をつけてお
いても上記実施例と同様の効果を奏する。Further, in the above embodiment, the scale 12' is added to the mask alignment pattern 12 of the trimming mask, or even if the scale is attached in a process prior to the 1-screen alignment pattern 11Vc on the semiconductor substrate, the same effect as in the above embodiment can be obtained.
以上説明したように、この発明シヱ、マスクまたは半導
体基板のマスク合わせパターンに目盛をつけたので、マ
スク合わせ精度の向上２作業者間による不均一性の減少
２作業能率１歩留の向上がはかｊる利点がある。As explained above, in this invention, since the mask or the mask alignment pattern of the semiconductor substrate is calibrated, the accuracy of mask alignment is improved, the non-uniformity between workers is reduced, the work efficiency is improved, and the yield is improved. It has the advantage of growing.
第１図（ａ）〜（ｄ）はトリミング工程の写真製版の従
来の方法を説ツＪするための主安段階における状態を示
す平面図、第２図（ａ）〜（ｄ）はこの発明の一実施例
を説明するための主要段階における状態を示す平面図で
ある。
図中、１１は半導体基板上のマスク合わせパターン、１
２は目盛り付きのマスク合わせパターン、１２′は目盛
、１３はエビ抵抗部分の素子パターン、１４はトリミン
グマスクのパターンである。
なお、図中の同一符号は同一まｋは相当部分を示す。
代理人 大音増雄 （外２名）
第１図
（ａ） （ｂ）
（Ｃ） （ｄ）
第２図
（ａ） （ｂ）
（ｃ） （ｄ）FIGS. 1(a) to (d) are plan views showing the state at the main stage for explaining the conventional method of photolithography in the trimming process, and FIGS. 2(a) to (d) are plan views of the present invention FIG. 2 is a plan view illustrating a state at a main stage for explaining one embodiment of the present invention. In the figure, 11 is a mask alignment pattern on a semiconductor substrate, 1
2 is a mask alignment pattern with graduations, 12' is a graduation, 13 is an element pattern of the shrimp resistance portion, and 14 is a trimming mask pattern. Note that the same reference numerals in the figures indicate corresponding parts. Agent Masuo Ohone (2 others) Figure 1 (a) (b) (C) (d) Figure 2 (a) (b) (c) (d)
Claims (1)
抵抗部分を作り、トリミングマスクを用いてトリミング
をすることにより前記エビ抵抗部分の抵抗値を所定の許
容値内に調整する工程を含む半導体装置の製造方法にお
いて、前記トリミングマスクのマスク合わせパターンま
たは前記半導体基板上のマスク合わせパターンに目盛を
付け、この目盛を用いて前記トリミングマスクの位置決
め乞行うことｔ特徴とする半導体装置の製造方法。 （２）半導体基板は、ＧａＡｓ基板であることｔ特徴と
する特許請求の範囲第（１）項記載の半導体装置の製造
方法。[Claims] (11) A step of forming a resistor portion on an epitaxially grown semiconductor substrate and trimming the resistor portion using a trimming mask to adjust the resistance value of the resistor portion to within a predetermined tolerance value. A method of manufacturing a semiconductor device comprising: attaching scales to the mask alignment pattern of the trimming mask or the mask alignment pattern on the semiconductor substrate, and positioning the trimming mask using the scales. Method (2) The method for manufacturing a semiconductor device according to claim (1), wherein the semiconductor substrate is a GaAs substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59002954A JPS60145652A (en) | 1984-01-09 | 1984-01-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59002954A JPS60145652A (en) | 1984-01-09 | 1984-01-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60145652A true JPS60145652A (en) | 1985-08-01 |
Family
ID=11543757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59002954A Pending JPS60145652A (en) | 1984-01-09 | 1984-01-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60145652A (en) |
-
1984
- 1984-01-09 JP JP59002954A patent/JPS60145652A/en active Pending
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