JPS6014511A - Power amplifying device - Google Patents

Abstract

PURPOSE:To operate a device effectively even for higher harmonic distortion while preventing the reduction of a maximum output by constituting the device with a class ''D'' power stage which is operated with a power source voltage different between a large output and a small output, a D type flip flop, and a comparator. CONSTITUTION:An input signal is compared with a forecast signal of n number of clocks before by a comparator 2, and logical ''1'' is given to an FF D1 in case of (the input signal) >= (the forecast signal), and logical ''0'' is given there in case of (the input signal) < (the forecast signal). As the result, outputs of FFs D1-Dn which are driven with a clock higher than the input signal are logical ''1'' still in the section where the input signal is increased continuously, and they are logical ''0'' still in the section where the input signal is decreased continuously, and an amplifier 11 is operated as a class ''D'' amplifier, and the signal is restored to the original signal by an integrator 12 and is fed back to the comparator 2. Unless all of outputs of FFs D1-Dn are ''1'' or ''0'', the amplifier 11 is operated with power source voltages E2 and E3. If the gate is ''1'', a transistor TR Q2 is operated with a power source voltage (E1+E2), and the switching amplitude is (E1+E2); and otherwise, the amplitude is changed to (E3+E4). With respect to higher harmonic distortion, an effect similar to a conventional device is obtained by said negative feedback.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a power amplification device that aims to reduce harmonic distortion and improve power efficiency of a class D (switching operation) power amplifier.

(Configuration of conventional example and its problems) An example of a conventional PWM type class power amplifier is shown in FIG. In FIG. 81, the input signal from signal source 1 is compared by comparator 2 with a triangular wave of constant amplitude. The triangular wave to be compared is obtained by oscillating at a constant frequency by the oscillator 3 and converting the waveform by the triangular wave converter 4.

As a result, at point a, the well-known υPWM modulation is obtained,
The power of the PWM modulated wave is amplified by the TTD class power amplifier 5, the human power signal is demodulated by the integrator 6, and an audible sound is generated by the speaker 7. As a result, class A operation, B
Power loss can be improved by amplifying power by switching operation compared to a power amplifier that operates in parallel mode, but this alone is not perfect. In other words, as shown in Figure 2, in the audio signal power amplifier, the load of the class D power amplifier is the integrator coil (inductive load), so the current flowing through the transistor (Figure 2(b)) is equal to the voltage (Figure 2(b)). (a)
), which causes a relatively large power loss (FIG. 2(C)) at each switching.

The most basic methods for improving power loss in class D power amplifiers include (1) reducing the number of switching operations, and (2) reducing the switching amplitude. In a power amplifier, (1
), it is necessary to increase the integrator time constant, which narrows the reproduction bandwidth9, and case (2) has the disadvantage that the maximum output is reduced.

(Objective of the Invention) The present invention aims to implement the above-mentioned basic countermeasures while preventing a reduction in reproduction bandwidth and maximum output, and as a result, it can effectively operate against harmonic distortion. The present invention aims to provide a power amplification device that provides

(Structure of the Invention) In order to improve its power efficiency, the class D power amplifier device according to the present invention includes a class D power stage that operates with different power supply voltages during high output and low output, and an increase or decrease in the input signal. It is composed of a D-type flip-flop that detects the degree of change in the signal and a comparator that reduces harmonic distortion.

(Explanation of Embodiment) FIG. 3 is a diagram illustrating an embodiment of the power amplification device according to the present invention, in which a signal from a signal source 1 is sent to a comparator (hereinafter referred to as a comparator) 2, and a signal n clocks before (predicted signal ) and input signal≧predicted signal... ■Input signal <predicted signal...middle...■.

If it is in the state of ■, a logic 'pin' signal is output to the D-type flyklop D, and if it is in the state of ■, it outputs a logic +10 signal.
1 signal is given as data.

As a result, the output of the D-type 7 lip-flop (DI-Dn), which is driven by a sufficiently higher clock than the input signal, is that the logic "1" remains in the section where the input signal continues to increase, and the logic "1" remains in the section where the input signal continues to decrease. remains at logic -0' and is not used as a control signal for the class D power amplifier 11. The amplifier performs class D operation and is restored to the original signal (power amplified input signal) by the integrator 12. will be returned. D
The type 7 lip-flop has n stages connected in series, but the DI
If ~Dn are all logic 'I' or -P, AND gate 13 or NAND gate 14 will cause transistor l Q1*Q4 to not operate, and amplifier 11 will be connected to supply voltage
21"3 to operate.

AN whose outputs from D1 to Dn all detect logic lII+
When the D gate is 1111, it means that the input signal has been increasing since n clocks ago, and in this state, the transistor of the class D power amplifier 11. 1 is ONL,
Transistor Q2 operates with the power supply voltage (E, +B2),
The switching amplitude is (EI+E2), and if the reverse input signal continues to decrease, the switching amplitude is reduced by the NAND gate 14 and the transistor Q4. The negative switching amplitude of 3 changes to (E3+E4).

FIG. 4 is a timing chart showing this principle.

As for harmonic distortion countermeasures, the original signal regenerated by the integrator 12 is fed back to the comparator 2, which has the same effect as the negative feedback in conventional class B or class A amplifiers. The power efficiency is also improved due to the effect of switching the power supply and the reduction in the number of switching operations.

(Effects of the Invention) As described above, according to the present invention, changes in the input signal such as increase or decrease can be detected, the power supply voltage can be changed at low output and high output, and the integrator output can be negatively fed back. By reducing the number of switching times, power efficiency can be improved without narrowing the reproduction bandwidth or reducing the maximum output. Furthermore, harmonic distortion can be suppressed by negative feedback of the integrator output.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional PWM modulation class amplification device, Fig. 2 is an explanatory diagram of power loss, Fig. 3 is a diagram showing an embodiment of the present invention, and Fig. 4 is a diagram illustrating the principle of the present invention. FIG. l ・・・・・・・・・Signal source, 2・・・・・・・・・
・Comparator (comparator), 11...
Amplifier, 12...Integrator, 13...
・・・・・・AND gate, 14・・・・・・・・・
NAND gate.

Claims (1)

[Claims] Connecting the output of a class D operating power amplifier that operates with a plurality of power supply voltages to a load resistor and one input terminal of a comparator via an integrator, and connecting an input signal source to the other input terminal of the comparator, A power amplifying device characterized in that the output of the comparator is used as a data input of a D-type 7 lip-flop connected in multiple stages, and the power supply voltage of the class-2 power amplifier is changed in accordance with the output of the D-type 7 lip-flop.