JPS60144960A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To adjust capacitance and the increase of capacitance with high accuracy by changing one part or the whole of a built-in capacitance element into two layers, using an uppermost layer electrode as a split-electrode and cutting a mutual connecting section. CONSTITUTION:A lowermost layer electrode 1 in a double-layer capacitance element is formed on an SiO2 film 7 on an Si substrate 6, an internal electrode 2 is formed on the electrode 1 through an SiO2 film 8, and an uppermost layer electrode 3 mutually connected by a connecting section 4 is disposed on the electrode 2 through an SiO2 film 9. The electrode 3 is connected to the lower layer electrode 1 through a connecting section 4' and a through-hole 5, and coated with a protective film 10. A wafer is treated, a laser is projected to the connecting section 4 or 4' in the uppermost layer electrode while inspecting the connecting section 4 or 4', and the connecting section 4 or 4' is evaporated together with the protective film 10 and a capacitance value is adjusted. According to the constitution, a capacitance and the capacitance ratio can be formed with high accuracy, and a D/A converter is manufactured easily with high precision.

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device incorporating a high-precision capacitor or a capacitor with a reduced error in capacitance ratio between a plurality of capacitors. The present invention relates to integrated circuit devices.

[Prior art]

In recent years, MO8 technology has been rapidly expanding its application fields with the rapid progress in manufacturing technology and circuit design technology.

Conventionally, in the field of digital-to-analog and analog-to-digital converters using resistive elements, digital-to-analog and analog-to-digital converters using capacitors have been manufactured.

Digital/analog and analog/analog using capacitive elements
The main cause of deterioration in digital converter accuracy is the accuracy of the capacitance ratio between capacitive elements.

Conventionally, as a method of ensuring a capacitance ratio between capacitive elements, a method of connecting unit capacitors in parallel as shown in FIGS. 1 and 2 is well known. FIG. 1 is a plan view of an example of a conventional capacitive element, and FIG. 2 is a cross-sectional view of FIG. 1. Figures 1 and 2
In the figure, a lowermost electrode 1 is formed on an insulating film 7 formed on a semiconductor substrate 6, and an upper electrode 2 is formed through an insulating film 8.
1 is generally formed. As mentioned above, instead of obtaining a specified capacitance with a single capacitive element, multiple capacitive elements were used in parallel to ensure the accuracy of the capacitance ratio, but digital-to-analog conversion requires high precision of 10 bits or more. When trying to obtain the desired accuracy, it is extremely difficult to achieve the desired accuracy due to the effects of process variations and stray capacitance.

Furthermore, in order to avoid the influence of stray capacitance, it is necessary to increase the unit capacitance. This method inevitably has the drawback that the area of the capacitive element increases, resulting in an increase in the chip area.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device including a capacitive element which has high capacitance accuracy and capacitance ratio accuracy and is miniaturized, eliminating the above-mentioned drawbacks.

[Structure of the invention]

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device incorporating a plurality of capacitive elements, in which a part or all of the capacitive elements are two-layer capacitive elements, and the two-layer capacitive element has one uppermost layer electrode. Or, it consists of a plurality of divided electrodes connected to each other, and the uppermost layer electrode is connected to the lowermost layer electrode of the capacitor, and the uppermost layer electrode is connected to the lowermost layer electrode or the divided electrode is built-in. configured.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a plan view of one embodiment of the present invention, and FIG. 4 is a sectional view taken along line A-A' in FIG.

As shown in FIGS. 4 and 5, the bottom layer electrode 1 for a two-layer capacitive element is provided on an insulating film 7 formed on a semiconductor substrate 6, and the internal electrode 2 is provided on the bottom layer electrode 1. The uppermost layer electrodes 3 are provided on the insulating film 8 and further connected to each other by the connecting portions 4. The uppermost layer electrodes 3 are provided on the insulating film 9 on the internal electrodes 2.

The uppermost layer electrodes 3 and 4 are connected to the lowermost layer electrode 1 through a through hole 5 by a connecting portion 4, and the entire capacitive element portion is covered with a surface protective film 10 in the final processing step. .

Next, after the wafer processing process is completed, the integrated circuit mounting is inspected for characteristics in the wafer state, but at this time, without inspection, laser energy is irradiated to the top layer electrode connection part 4 or 4', and the surface protective film and Top layer electrode connection part 4 or 4
′ is evaporated and cut.

Note that the uppermost layer electrode connecting portions 4 and 4' are formed sufficiently thinner than the uppermost layer electrode portion 3, so they can be easily cut by laser beam irradiation, and the surrounding surface protective film will be reused at the cut portion. Since it melts and flows and completely covers the cut, there are no reliability issues.

In the above embodiments, the electrode shape is shown to be rectangular, but it may be circular, polygonal, etc., and is not particularly limited.

Further, as electrode materials, it is relatively easy to use polysilicon or silicon for the lowermost layer electrode 1, polysilicon or aluminum for the inner electrode 2, and aluminum for the lowermost layer electrode 3.

As the interlayer insulating film for capacitance formation, the first layer insulating film 8 is made of silicon oxide film, silicon nitride film, etc.
The second layer insulating film 9 may be made equal to the first layer, or a silicon oxide film, a silicon oxide film, or a PEG film may be made with a current of several thousand amps. In particular, when the second layer insulating film 9 is made to have a film thickness of several thousand holes, as in the latter case, the gate polysilicon and aluminum wiring are It has the feature that it can be used as an internal electrode and an uppermost layer electrode, and does not require a special process to form a two-layer capacitive element.

〔Effect of the invention〕

As explained above, according to the present invention, the built-in capacitive element can be made into two layers without increasing the number of steps, and the uppermost N1tt pole of the two-layered capacitive element can be divided iI! By adjusting the capacitance value by cutting the poles and irradiating them with laser energy, it is possible to obtain high-precision capacitors and capacitance ratios without increasing the size of the capacitors. Therefore, high-precision digitization and analog conversion can be achieved. This has the effect that utensils etc. can be easily manufactured.

[Brief explanation of drawings]

Fig. 1 is a plan view of an example of a conventional capacitive element, and Fig. 2 is a plan view of an example of a conventional capacitive element.
FIG. 3 is a plan view of an embodiment of the present invention; FIG.
The figure is a sectional view taken along the line A-A in FIG. 3. 1... Bottom layer electrode, 2... Internal electrode,
3...Top layer electrode, 4,4'...Top layer electrode connection part, 5...Through hole, 6...
... semiconductor substrate, 7. '8.9・・・Insulating film,
10... Surface protective film, 21... Upper electrode. Sheep l concave 2nd figure

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device incorporating a plurality of capacitance elements, some or all of the capacitance elements are two-layer capacitance elements, and the top layer electrodes of the two-layer capacitance elements are connected to each other. It consists of a plurality of divided electrodes, and the uppermost layer electrode is connected to the lowermost layer electrode of the capacitive element, and the capacitance is increased by cutting the connection between the uppermost layer electrode and the lowermost layer electrode or the connection between the divided electrodes. 1. A semiconductor integrated circuit device comprising a built-in capacitive element having a capacitive element portion for adjusting capacitance that can be adjusted.