JPS60142775A - Picture processing unit - Google Patents

Abstract

PURPOSE:To reduce the amount of hardware by providing a means reading a picture element value from a picture data storage means at a fixed interval and a means writing an output of a median filter circuit at a fixed interval to eliminate a high energy noise with a filter of a small size. CONSTITUTION:Addresses of the 1st and 2nd picture memories 3, 5 are generated by an address counter 1 of a picture processing unit, added to an address conversion circuit 2 in synchronizing with the clock and converted into an address scanned repetitively at each other picture element by the circuit 2. The converted address is applied to the 1st memory 3 inputting a picture data from a picture signal generator of a device such as a video camera. Furthermore, the picture element value including the noise from the memory 3 is read to the median filter circuit 4 at a fixed interval, an output of the filter circuit 4 is written in the memory 5 and the noise with high energy is eliminated by the filter of a small size so as to simplify the constitution of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing device, and particularly, when removing noise from image data, it is possible to perform large-scale noise removal processing with a small-sized filter.

[Conventional technology and problems]

For example, when converting an image into an image signal and storing it in an image memory, this image signal contains unwanted noise. A median filter is used as one of this noise processing. The median filter, as shown in FIG. 1A, for example, sequentially scans an image using a filter f having windows of a fixed size, and outputs the intermediate value extracted by each window. When a filter with three windows is used as shown in FIG. 1(a), and the pixel sizes of each window are bO, bl, and b2, a pixel with a size intermediate between these three is output. Now, if ba<b2<bl, then the intermediate b2 value will be output as the value of the central pixel of this filter. Therefore, as shown in FIG. 1(b),
Even if noise N exists in image signal a, by performing this median filter processing, as shown in (C),
Noise N can be removed.

Furthermore, as shown in Fig. 2(a), when noise N exists in two pixels, the median filter with the number of windows of 3 shown in Fig. 1 cannot remove them; By using a median filter of such size, noise can be removed as shown in Figure 2(b).However, if a median filter with a window number of 5 is used, However, as shown in Figure 3(a), if noise N exists in three pixels, the processing result will be as shown in Figure 3(b) and the noise N cannot be removed. requires the use of a median filter with 7 windows.In other words, according to the conventional noise removal method, when the size of the noise to be removed is n, the size (number of windows) is 2n+1. In general, in order to remove isolated noise in an image, it is necessary to use a median filter that is twice the size of the isolated noise.

However, when using a large median filter, in order to extract the intermediate values, it is necessary to sort the data extracted from each window, arrange them in order of size, and perform a sorting operation to extract the intermediate values. be. For this reason, if the size of the median filter is increased in order to remove large noises, there is a drawback in that the amount of hardware such as the sorting circuit increases accordingly.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus capable of removing large-sized noise using a small-sized filter in order to improve the above-mentioned drawbacks.

[Structure of the invention]

In order to achieve the above object, the image processing device of the present invention includes: an image data holding means for holding image data; a filter having a window for scanning pixel values held in the image data holding means; An image processing device that has a median filter circuit that extracts a pixel value with an intermediate size from among the pixel values output from these windows, and the image data is read out at regular intervals from pixel values held in the image data holding means. The present invention is characterized by comprising a reading means and a writing means for writing the output of the median filter circuit at regular intervals.

[Embodiments of the invention]

First, the outline of the present invention will be explained with reference to FIG.

In the present invention, pixels 1.2.3, .
-, for example, 1.3.5.7.9 is outputted by a median filter F to output a pixel with an intermediate value among these pixels, and then 2.4.6.8.10 is outputted by a median filter F. Outputs the intermediate one among them. This results in
As shown in FIG. 4(a), even if the noise N is for example three consecutive pixels, it can be removed by a median filter with five windows and processing as shown in FIG. 4(b) can be performed. As a result, if the size of the median filter is n, isolated noise of (n/2)+1 or less can be removed.

An embodiment of the present invention will be described with reference to a map in FIG.

In FIG. 5, 1 is an address counter and the first
2 is an address conversion circuit that generates addresses for the image memory 3 and the second image memory 5, and inputs addresses that increase in ascending order from address counter 1 to 1.2.3.4- in synchronization with the clock. For example, 1.3.5-12.
4. 6- and 11-il image memory for converting addresses in order to carry over and scan every other pixel; 3 is an 11-il image memory, which receives image data output from an image signal generator (not shown) such as a video camera; 4 is a median filter circuit that extracts pixels output from the first image memory 3 using the median filter and outputs pixels with intermediate values. 5 is a second image memory in which pixels output from the median filter circuit 4 are stored; 6;
is the address correction circuit and the median filter circuit 4
This is to correct the time delay caused by the address conversion circuit 2, and generates an address with a time delay with respect to the address series converted by the address conversion circuit 2. In FIG. 5, image data output from an image data output unit such as a video camera (not shown) is input to the first image memory 3. This image data contains noise.

Further, the median filter circuit 4 uses a median filter having a size of 5.times.1, as shown in FIG. 4, for example.

Now 1.2 from address counter 1 in synchronization with the clock
．． 3- and addresses are generated in ascending order.

This address is transmitted to address conversion circuit 2 and is 1.3
．． 5-. 2.4.6-, and as a result, the pixel values are output from the first image memory 3 while being carried over every other pixel, and are input to the median filter circuit 4. The median filter circuit 4 sorts the five pixel values corresponding to the size of the median filter and transmits the intermediate pixel value to the first image memory 35, as explained in FIG. 4(a). At this time, the address correction circuit 6 corrects the time delay caused by the median filter circuit 4 and converts the address output from the address conversion circuit 2 into the second address.
Since the pixel value is output to the image memory 5, the pixel value output from the median filter circuit 4 is stored at a predetermined address in the second M image memory 5. By sequentially processing the image data stored in the first image memory 3 in this way, noise processing is performed as explained in FIG. 4, and the image data from which the noise has been removed is stored in the second image memory 5. It will be stored.

By the way, one of the processes for image data is to perform differential processing on the image data to detect a change point in its density. FIG. 6 shows a conventional example of such differential processing. In the figure, pixels 1 to 6 have a pixel value of "1", pixels 7 to 13
The pixel value "3" is stored in the field. Now, these pixels are processed by a 9×1 median filter F, for example, as shown in
” and send it to the median filter register MF.
Set it to section R1 of H, and in the next step ■, pixels 3 to 1
Process 1 and output the intermediate value "3", which is divided into classification R2.
In the next step (2), pixels 4 to 12 are subjected to median filter processing and the intermediate value "3" is set in the category R3. These are divided into sections DI, D2, and D of the differential filter DF.
3 is multiplied by the numerical values "-1", rOJ, and "1" corresponding to the classification, and the sum of these multiplication results is calculated and outputted. In this case, the following formula is calculated and the numerical value is "2".
is obtained.

LX (-1) +3XO+3X1=2 This "2" is output and set in the memory as shown in FIG. 6(b). Such calculations are performed on the pixels shown in FIG. 6(a), and the product-sum calculation results shown in FIG. 6(b) are obtained. As a result,
It can be seen that the density change is large at pixel 6.7.

Such a differential operation can be executed by the image processing device of the present invention. In the case of the present invention, for example, FIG.
), a 5×1 median filter MF is used. Among the pixels shown in 711J (a) 1 to 13, for example, as shown in ■, pixels 2, 4, 6, 8 .10 is processed and the intermediate value is the pixel value "
1” and sends it to the median filter register M.
Set the FH section numeral to 1 and set the pixel to 4.6 in the next step ■
．． 8.10.12 is subjected to median filter processing and the intermediate value "3" is set to the numerator 2. These are the numerical values "-1" set in the sections dl and d2 of the differential filter DF,
Multiply each category correspondence by "1", find the sum of these multiplication results, and output this. In this case, the following equation is calculated and the numerical value "2" is obtained.

LX (-1)+3X1=2 This "2" is output and set in the memory as shown in FIG. 7(b). Such calculations are performed on the pixels shown in FIG. 7(a), and the product-sum calculation results shown in FIG. 7(b) are obtained. As a result, it can be seen that the density change is large at pixel 6.7.

In such processing, the median filter processing and the differential calculation by the product-sum calculation described above can be pipelined, and the circuit configuration can be simplified.

0 - Next, the image processing shown in FIG. 7 will be explained using another embodiment of the present invention shown in FIG.

In FIG. 8, the same reference numerals on the map indicate the same parts. Reference numeral 10 denotes an arithmetic circuit which calculates the above formula and has a median filter register MFR and a differential filter DF, and which performs multiplication and addition for each section. Reference numeral 11 denotes an address correction circuit, which corrects the time delay caused by the median filter circuit 4 and the arithmetic circuit 10, and generates an address with a time delay with respect to the address series converted by the address conversion circuit 2. . The second image memory 12 is a memory in which the calculation results of the calculation circuit 10 are stored.

In FIG. 8, input images are stored in the first image memory 3 as in the case of FIG. And the address
1.2.3.4, - in synchronization with the clock from counter 1
-Generates the address “-”, which is the address conversion circuit 2
Accordingly, the pixel values are output from the first image memory 3 every other pixel and input to the median filter circuit 4. 7(a) by this median filter circuit 4.
, (2) are subjected to median filter processing as described above, and the numerical values 1.3, - are output to the arithmetic circuit 10. In the arithmetic circuit 10, this numerical value 1.3-... is placed in each section of the median filter register VFR, and the numerical value "-" set in the sections d1 and d2 of the differential filter DF is set.
1" and "1", the multiplication results are summed, and a differential operation is performed. The calculation result of the calculation circuit 10 is then stored in the second image memory 12.

〔Effect of the invention〕

According to the present invention, a large noise removal effect can be obtained with a small-sized median filter, which not only reduces the amount of hardware but also shortens processing time.

[Brief explanation of the drawing]

Figures 1 and 2 are illustrations of the median filter, Figure 3 is an illustration of problems with the median filter, Figure 94 is an illustration of the principle of the present invention, and Figure 5 is the configuration of the first embodiment of the invention. 6 is an explanatory diagram of a differential operation using a conventional median filter, FIG. 7 is an explanatory diagram of a differential operation to which the present invention is applied, and FIG. 8 is a configuration diagram of another embodiment of the present invention. In the figure, 1 is an address counter, 2 is an address conversion circuit, 3 is a first image memory, 4 is a median filter circuit,
5 is a second image memory, 6 is an address correction circuit, 10 is an arithmetic circuit, 11 is an address correction circuit, and 12 is a second image memory. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani 3

Claims (1)

[Claims] 1. An image data holding means for holding image data, a filter having a window for scanning pixel values held in the image data holding means, and a filter for scanning pixel values output from these windows. An image processing device having a median filter circuit for extracting a pixel value having an intermediate size, the image data reading means for reading out the pixel values held in the image data holding means at regular intervals, and the output of the median filter circuit. An image processing device characterized by comprising a writing means for writing at regular intervals. 2. The image processing apparatus according to claim 1, further comprising an arithmetic circuit that performs a product-sum processing on the output of the median filter circuit.