JPS60142519A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the method of manufacturing semiconductor device which gives less damage of resist layer and is superior in the mass-productivity by carrying out the etching with a high power only for the period corresponding to the etching for the average thickness of etching layer and also carrying out the over etching thereafter with a low power for the other etching layer. CONSTITUTION:An aluminum alloy layer 3 of 10,000Angstrom is deposited on a silicon oxide layer 2 formed on a substrate 1 and wiring patters are formed by etching a resist layer 4 coated on said alloy layer by photo etching process. Thereafter, the aluminum alloy layer 3 is etched by reactive ion etching method. In this case, etching is carried out with a high power only for 10min (10,000Angstrom / 1,000Angstrom ) corresponding to 10,000Angstrom which is an average thickness of aluminum alloy layer 3. After 10min, the silicon oxide layer 2 is etched in some places and a ratio for resist selection is lowered and the etching is carried out with a low power during an overetching period.

Description

[Detailed description of the invention] Technical details of the invention! i! r] The present invention uses a reactive ion etching method to form a resist IN.
The present invention relates to a method for manufacturing a semiconductor device (1) in which an etching layer that has not been considered is etched.

Technical background of the invention and its problems] In recent years, reactive ion etching has been widely used for etching semiconductor devices. The reactive ion etching method is a method in which the object to be etched is placed on the anode or cathode of parallel plate electrodes, and etching is performed using the incident energy of ions generated by glow discharge.
The advantage is that the dimensional accuracy of the pattern is good.

For example, consider the case where an aluminum alloy layer 3 formed on a semiconductor substrate with a silicon oxide layer 2 interposed therebetween is etched as shown in FIGS. 1(a) and 1(b). A resist layer 4 is formed on the aluminum alloy layer 3 according to the wiring pattern. When this aluminum alloy layer 3 is etched using a high etching power, the resist layer 4 is seriously damaged. For example, when etching with a high power of 390 W, the etching rate of the aluminum alloy layer 3 is about 1000/min, and the selectivity to resist is 3.8 while etching the aluminum alloy layer 3.
It is 2.0 during overetching. The purpose of overetching is to prevent unetched portions from remaining due to variations in the height of the aluminum alloy layer 30, and is usually carried out only at a portion (9) of the thickness of the aluminum alloy layer 3. The reason why the selectivity to resist during overetching is low is that the underlying silicon oxide layer is also etched, and the etching of the resist layer is promoted by oxygen zolazma. Now, when etching the aluminum alloy layer 3 of 1oooo X, including over-etching, (1oooo
00
a, s + aooo X, / 2.0 = 2e3
t, L + 1500 X = 4131 K, making it miserable and fat.

In order to prevent such damage to the resist layer 4, reactive ion etching is performed by turning down the nozzle and using low power. For example, when etching with a low power of 350 W, the etching rate of the aluminum alloy layer 3 is approximately 450 K for 7 minutes, and the selectivity to resist is 4.5 during etching of the aluminum alloy layer 3 and 30 during over-etching. . Similarly 10000K
When etching the aluminum alloy layer 3 of
3000 K 73.0 = 2222 K + 10
'OOX = 3222
X-1-3000K) 7450K = 28.9
There was an open chain that lasted for a long time. Etching time or
As a result, the manufacturing time became longer and the mass productivity of semiconductor devices could not be improved.

[Objective of the Invention] The present invention has been developed in consideration of the above ↑ IV, and provides a method for manufacturing a semiconductor device that causes less damage to the resist layer and is excellent in mass production. : The purpose is to provide.

[Summary of the Invention] To achieve this object, a method for manufacturing a semiconductor device according to the present invention involves etching with a rope warp for a time equivalent to etching the average thickness of the etching layer, and then etching with a low power. T+ to overetch the remaining etching layer! It is assumed to be f-symptom.

Embodiment of the Invention A method for manufacturing a semiconductor device according to an embodiment of the invention will be described with reference to FIG. A 10000X aluminum alloy layer 3 is formed on a silicon oxide layer 2 formed on a semiconductor substrate 1.
The resist layer 4 coated thereon is etched by a photo-etching process to form a wiring pattern. Thereafter, the aluminum alloy layer 3 is etched using a reactive ion etching method. First, high power (3
90W) to etch the aluminum alloy layer 3. The aluminum alloy layer 3 has an average thickness of 10,000 mm.
10000X/1000 people etched by A amount = 1
Etching with high power for 0 minutes (Figure 2 (b))
.

After 10 minutes, the silicon oxide layer 2 is etched in some places and the selectivity to resist becomes low, so etching is performed at low power (350 W) during over-etching (FIG. 2(C)). 3000 x / 450 x -6, to perform 30% oats etching.
Etch at low heat for 7 minutes.

Damage to the resist caused by the two-stage etching of high-power etching followed by low-power etching is due to the resist selectivity of 3.5% during etching of the aluminum alloy layer 3 with high power. S: Since the resist selectivity during overetching at low power is 30, 1oo
oo X 73,8 + :3000 AI 3.0
= 2631 K + 1ooo X = 3631
K and 88% compared to the conventional high power case.

And the etching time is; 10000 x / 100
0 X + 3000 X / 450 days = 10 minutes + 6
7 minutes = 16.7 minutes, which is 58 minutes compared to the conventional low-zower case.
%. As described above, according to this embodiment, there is little damage to the resist layer and the mass productivity is excellent.

In the previous embodiment, the case where an aluminum alloy layer was etched was described, but etching layers other than an aluminum alloy layer, such as a polysilicon layer, a holybdenum layer, and an aluminum-silicon-copper (AI-St-Cn)
The two-stage etching method of the present invention can also be used for etching layers.

In order to switch between the quotient power and the low power in reactive ion etching, the power of the frequency power supply itself may be switched as described above. It may be adjusted by

Further, it goes without saying that the power of the two-stage etching is not limited to the above-mentioned values.

Effects of the Invention As described below, according to the present invention, it is possible to shorten the etching time of the etching layer while preventing damage to the resist layer. For example, assuming that 24 wafers per 10 wafers can be etched 12 wafers at a time, the etching time for 10 wafers is 2XHi, 7 minutes = 33.4 minutes, and it is possible to etch only with low power. Etching time 2xJ8=57.
This decreases to about 58% compared to 8 minutes. As mentioned above, the damage of resist J.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are explanatory diagrams of a conventional method for manufacturing a semiconductor device, and FIGS. 2(a) and 2(b) are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. be. 1... Semiconductor substrate, 2... Silicon oxide layer, 3...
- Aluminum alloy layer, 4... resist layer. Applicant's agent Kiyoshi Inomata

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which an etching layer that is not covered with a resist layer is etched by a reactive ion etching method, wherein the etching layer (a) is etched for a period of time equivalent to etching the average thickness of the etching layer (a). 1. A method for manufacturing a semiconductor device, characterized in that etching is performed with a sieving power, and then the remaining etching layer is over-etched with a low power.