JPS60141022A - Coder and decoder - Google Patents

Coder and decoder

Info

Publication number
JPS60141022A
JPS60141022A JP24701483A JP24701483A JPS60141022A JP S60141022 A JPS60141022 A JP S60141022A JP 24701483 A JP24701483 A JP 24701483A JP 24701483 A JP24701483 A JP 24701483A JP S60141022 A JPS60141022 A JP S60141022A
Authority
JP
Japan
Prior art keywords
section
decoder
encoder
gain
switches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24701483A
Other languages
Japanese (ja)
Inventor
Kazuo Ogasawara
和夫 小笠原
Toru Shibata
柴田 透
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP24701483A priority Critical patent/JPS60141022A/en
Publication of JPS60141022A publication Critical patent/JPS60141022A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B14/00Transmission systems not characterised by the medium used for transmission
    • H04B14/02Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Analogue/Digital Conversion (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE:To satisfy the insertion loss variation and te crosstalk characteristic specification by providing a selection circuit to the input stage of a transmission or reception filter and adjusting the gain of a coder or a decoder through the selection so as to use a single reference voltage source. CONSTITUTION:It is made possible to adjust the gain of the reception side independently of the gain adjustment at the transmission side by using a reception filer 14' and a gain adjusting section 21. Fig. (a) shows an example of the input stage of the reception filter 14' with a switch group, a capacitor group and an input stage amplifier 28. Switches 22, 23 are for substantial switched capacitor operation so as to constitute the input stage of a PAM output wave of the decoder 6. Other switches and capacitors 24'-27', represent the input capacitor group and the switch group and the gain adjustment section 21 is constituted as an example by a 2-bit selection signal generating circuit. Only the switches of the switches 24-27 are conductive when they are selected by the gain adjusting section 21 and the remaining switches are nonconductive. The gain adjustment of the reception side is conducted independently by the reference voltage source 19 and the output voltage adjusting section 20 at the input stage of the filter 14' in this way.

Description

【発明の詳細な説明】 (技術分野) 本発明は符号復号器に関する。[Detailed description of the invention] (Technical field) The present invention relates to a code decoder.

(従来技術) 従来、符号器復号器(以下、C0DECという。″)に
2いては、基準電圧源を内蔵して5なかった。
(Prior Art) Conventionally, an encoder/decoder (hereinafter referred to as CODEC) has a built-in reference voltage source.

第1南は従来のC0DECの第1の例を示すプロン。The first south part is a prong showing the first example of a conventional CODEC.

り図である。第1図42いて、アナログ信号は帯域制限
さizた後、アナログ入力端子1に印加δれ。
This is a diagram. In FIG. 142, the analog signal is band-limited and then applied to the analog input terminal 1.

符号器部5によj9PcM信号に変換されてデジタル出
力端子2から出力さする。デジタル入力端子4から入っ
てきたPCM信号は復号器部6により8kHzのP A
M (Pulse Amplitudefviodu 
l a t i on5.波としてアナログ出力端子か
ら出力される。符号器部5と復号器部6に使用する単−
基準重圧は端子7から供給ざnる。端子7から印加さ扛
る単−基準電圧は低インピーダンス駆動が容易なため、
符号器部5と復号器部6に共通に用いてもクロストーク
特性が劣化することは通常ない。
The signal is converted into a j9PcM signal by the encoder section 5 and outputted from the digital output terminal 2. The PCM signal input from the digital input terminal 4 is converted into an 8kHz PA by the decoder section 6.
M (Pulse Amplitude
la ti on5. Output from the analog output terminal as a wave. Single unit used for encoder section 5 and decoder section 6
The reference pressure is supplied from terminal 7. Since the single reference voltage applied from terminal 7 can be easily driven with low impedance,
Even if it is used in common for the encoder section 5 and decoder section 6, the crosstalk characteristics usually do not deteriorate.

C0DECのシステムは8kHz毎にサンプリングすゐ
サンプリングシステムのため、符号器部の入力アナログ
信号はサンプリング定理よjp4kHz以下の帯域制限
が必要″である。−万、復号器部のアナログ出力はPA
M波であるため平滑することが必要である。
Since the CODEC system uses a sampling system that samples every 8 kHz, the analog signal input to the encoder section must be limited to a frequency of 4 kHz or less according to the sampling theorem.
Since it is an M wave, it is necessary to smooth it.

MO8技術の進歩は帯域制限や平滑する機能、すなわち
フィルタ技術のLSI化をaf能とした。
Advances in MO8 technology have made it possible to implement band limiting and smoothing functions, that is, LSI filter technology.

スイッチトーキャパシタ・フィルタ(以下、SCFとい
う。)は容量とスイッチを組合せて等動抵抗を、芙現し
、この等動抵抗と容置で時定数が定゛まる。
A switched-toe capacitor filter (hereinafter referred to as SCF) combines a capacitor and a switch to create equal dynamic resistance, and the time constant is determined by this equal dynamic resistance and capacity.

第2図(a)にSCFの等動抵抗の原理図をボす。Figure 2(a) shows the principle of equal dynamic resistance of SCF.

端子8と端子9の間にスイッチ10および11が接続さ
れ、その中点に容量12(容t11をCとする)が接地
電位の間に接続されている。第2図(b)にスイッチ1
0yよび11のタイミングチャートを示す。第2図(b
)において@H”状態でそれぞれのスイッチは導通とす
る。時刻t = nT でスイッチ10が導通し、端子
8に印加さ几ていた電圧Vによシ、スイッチ10を介し
て答蓋12に光電される。充電された電荷Qは、スイッ
チ10と容量12の時定数が時間Tに対して十分少さい
と仮定して、Q=CV ・・・・・・・・・・・・・・
・(1)によ請求まる。、時刻t # nT+、T に
おいて、スイッチ10は非導通となる。その後、スイッ
チ11が導通して容量12に充電さn71c醒荷Qが端
子9から時刻t = n T −1−Tの直前までに放
電されたとする(すなわち容量12とスイッチ11の時
定数は十分に小さいと仮定する)。
Switches 10 and 11 are connected between terminals 8 and 9, and a capacitor 12 (capacitance t11 is C) is connected to the ground potential at the midpoint thereof. Switch 1 is shown in Figure 2(b).
0y and 11 timing charts are shown. Figure 2 (b
), each switch is conductive in the @H” state. At time t = nT, the switch 10 is conductive, and a photovoltaic voltage is applied to the cover 12 via the switch 10 due to the voltage V applied to the terminal 8. Assuming that the time constant of the switch 10 and the capacitor 12 is sufficiently small relative to the time T, the charged charge Q is calculated as follows: Q=CV ・・・・・・・・・・・・・・・・・・
・Requests will be made in accordance with (1). , at time t#nT+,T, the switch 10 becomes non-conductive. After that, it is assumed that the switch 11 is turned on and the capacitor 12 is charged with a discharged charge Q from the terminal 9 by just before time t = n T -1-T (that is, the time constant of the capacitor 12 and the switch 11 is sufficient). ).

このとき時間Tの間に、端子8から端子9へ流nた電荷
Qは(1)式よ請求まシ1等価電流1eはI e # 
Q/T = CV/T ・・・・・・・・・・・・・・
・(2)によ請求まる。(2)式はオームの法則を通用
すfLば等動抵抗fLeがまシ R6=V/ I 6− T / C・・・・・・・・・
・・・・・・・・・(3)となる。(3)式から容易に
理解されるように時定数(1/C几)は容量比で決まる
ため精度良く得られる。このため調整技術を用いて時定
数を合わせる必要もない。
At this time, the charge Q flowing from the terminal 8 to the terminal 9 during the time T can be expressed as equation (1).1 The equivalent current 1e is I e #
Q/T = CV/T ・・・・・・・・・・・・・・・
・Requests will be made in accordance with (2). Equation (2) applies Ohm's law to fL, equal dynamic resistance fLe, and R6=V/I6-T/C...
......(3). As can be easily understood from equation (3), the time constant (1/C) is determined by the capacitance ratio and can therefore be obtained with high accuracy. Therefore, there is no need to use adjustment techniques to match the time constants.

第3図は従来のC0DECの第2の例を示すブロック図
で、8CFを用いて帯域制限や平滑す心機能tl−LS
Iの中に組込んだ従来例である。
Figure 3 is a block diagram showing a second example of the conventional CODEC, in which the cardiac function tl-LS is band-limited and smoothed using 8CF.
This is a conventional example incorporated into I.

第3図は第1図において符号器部5側に8CFによる送
信フィルタ13によシ帯域制Viを行ない、復号器部6
側は5CFvcよる受信フィルタ14fcより平滑機能
の1,81化を行なったものでめる。
FIG. 3 shows that in FIG. 1, a transmission filter 13 of 8CF is used to perform band control Vi on the encoder section 5 side, and the decoder section 6
On the other hand, a receiving filter 14fc based on 5CFvc has a smoothing function of 1.81.

M(J8 1.II技術を用いた基準電圧源の実現も近
年可能となってきた。代表的な基準電圧源の構成方法と
して通常281m考えられる。一つはMOSトランジス
タのしきい11電圧の異なる同極性MO8トtトランジ
スタいたΔVT 形基準電圧源でるる。他の一つはNP
N)?ンジメタやPNPNシトジスタのバンドギャップ
電圧を取シ出して用いるバンドギャップ形j準電圧源が
ある。更に。
In recent years, it has become possible to realize a reference voltage source using M (J8 1. There is a ΔVT type reference voltage source with MO8 and T transistors of the same polarity.The other one is NP.
N)? There is a bandgap type j-quasi-voltage source that extracts and uses the bandgap voltage of a PNPN digital transistor or a PNPN digital transistor. Furthermore.

これ以外にもMOSトランジスタの弱反転層領域におけ
るゲート・ソース蒐圧VGIIとドレイン[iInの関
係が指数関数となるバイアス条件を用いた。基準電圧源
もあるが余シ用いられていない。
In addition to this, bias conditions were used in which the relationship between the gate-source pressure VGII and the drain [iIn in the weak inversion layer region of the MOS transistor was an exponential function. There is also a reference voltage source, but it is not used much.

第4図は従来のC0−1)E Cの興3の例を示すブロ
ック図で、基準電圧源をLSIの甲に内蔵したものであ
る。第4図において、第3図から追加されたのは送信側
の基準電圧源15および出力電圧調整部17と、受信側
の基準電圧源16および出力電圧調整部18である。
FIG. 4 is a block diagram showing an example of a conventional C0-1)EC system, in which a reference voltage source is built into the back of the LSI. In FIG. 4, what has been added from FIG. 3 is a reference voltage source 15 and an output voltage regulator 17 on the transmitting side, and a reference voltage source 16 and an output voltage regulator 18 on the receiving side.

第4図の如き送信側と受信側それぞれに独立に基準電圧
源15.16と出力all!l歪部17. 18を設け
るのは、送信側と受信側の調整が独立に実施できるため
送信側と受信側独立に利得調整が実施できるため非常に
有用でめると共に、送信側と受信側のクロストーク特性
改畳への一助となった。
As shown in FIG. 4, the reference voltage sources 15 and 16 and the outputs all! l Strain section 17. 18 is very useful because it allows adjustment of the transmitting and receiving sides to be performed independently, and gain adjustment can be performed independently of the transmitting and receiving sides. It helped with the tatami.

しかしながら、送1g側と受信側を先金独立に基準電圧
源を用意することは面積が2倍必要となシL8Iのチッ
プ面積に対する占有率τ高めるという欠点があった。
However, providing separate reference voltage sources for the transmitting side and the receiving side has the disadvantage of requiring twice the area and increasing the occupation rate τ of the L8I chip area.

第5図は従来のC0DECの第4の例を示すブロック図
で、送信側と受信側のタロストーク特性が許容される範
囲内で、LSIのチップ面積を最小とする手法として考
えられたものである。第5図は基準電圧像19と出力電
圧調整部20を送信側と受1d側で共通に持ち、符号器
部5と復号器部6に供給するものである。この構成とす
ることでクロストーク特性の許容する範囲内で面積を最
小とするC0I)ECが提供できた。
Figure 5 is a block diagram showing a fourth example of a conventional CODEC, which was conceived as a method to minimize the LSI chip area within the allowable range of Talostalk characteristics on the transmitting and receiving sides. . In FIG. 5, a reference voltage image 19 and an output voltage adjustment section 20 are shared by the transmitting side and the receiving side 1d, and are supplied to the encoder section 5 and the decoder section 6. With this configuration, it was possible to provide a C0I)EC with a minimum area within the range allowed by the crosstalk characteristics.

しかしながら、送信側および受信側の利得変動に対する
規格が狭くなるに伴ない、第5図の如き構成では限界に
近すいてきた。すなわち、第5図tこ象いて基準電圧源
19と、出力調整部20によシ送傷側と受イば側に共通
に供給されるものの、符号器部5における挿入損失や復
号器部6におVブる挿入損失の変動に対して規格の幅が
狭くな多すぎるようになり、更にはクロストーク特性の
規格も狭くなってさた。このため、 C01)ECを安
定に製造する上で非常に不安定な要素を残すことになる
という欠点を有していた。
However, as the standards for gain fluctuations on the transmitting and receiving sides become narrower, the configuration shown in FIG. 5 is approaching its limits. That is, as shown in FIG. The range of standards has become too narrow for variations in insertion loss that vary widely, and the standards for crosstalk characteristics have also become narrower. For this reason, there was a drawback that a very unstable element remained in stable production of C01) EC.

(発明の口重) X=明の目的は、上記の欠点て除去することによシ、単
一の基準電圧源を用いて、かり押入損失変動やクロスト
ーク特性規格を満足して、安定に製造できるところの符
号器復号器を提供することにある。
(Importance of the invention) The purpose of X=light is to eliminate the above-mentioned drawbacks, use a single reference voltage source, satisfy the intrusion loss fluctuation and crosstalk characteristic standards, and achieve stable performance. The object of the present invention is to provide an encoder-decoder that can be manufactured easily.

(発明の構成) 不発明の符号器復号器は、符号器部と、復号器部と、該
符号器部及び復号器部に同一の基準電圧を供給する単一
の基準電圧源と、該基準1圧源の出力電圧を調整する出
力゛酸圧調整部と、それぞれ前記符号器部への人力の帯
域制限2よび前記復号器部の出力の平滑化をするための
スイッテト・キャパアシタからなる送信フィルタ及び受
信フィルタとを含む符号器復号器におい、て、前記送1
gフィルタおるいは前記受信フィルタの入力段に複数個
のスイッチと複数個の容量からなる選択回路を設けその
選択により前記符号器部あるいは前記復号器部の利得を
調整する利得調整部を有する仁とから構成される。
(Structure of the Invention) The uninvented encoder-decoder includes an encoder section, a decoder section, a single reference voltage source that supplies the same reference voltage to the encoder section and the decoder section, and a single reference voltage source that supplies the same reference voltage to the encoder section and the decoder section. a transmission filter consisting of an output acid pressure adjustment section for adjusting the output voltage of the voltage source; and a suite capacitor for manually limiting the band to the encoder section and smoothing the output of the decoder section, respectively. an encoder/decoder including a receive filter;
g filter or a gain adjustment section that includes a selection circuit consisting of a plurality of switches and a plurality of capacitors at the input stage of the reception filter and adjusts the gain of the encoder section or the decoder section according to the selection thereof; It consists of

(実施例) 以下、本発明の実施例について図面を参照して説明する
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第6図は不発明の第1の実施例を示すブロック図である
FIG. 6 is a block diagram showing a first embodiment of the invention.

本実施例は、符号器部5と、復号器部6と、この符号器
7115及び復号器部6に同一の基準電圧を供給する基
準rt電圧源9と、この基準電圧源19の出力磁圧tl
−―整する出力ば圧pA整部20と、符曳号器都5への
入力の帯域制限および復号器部6の出力を平滑化するだ
めのスイッテト・キャバアシタからなる送信フィルタ1
3及び受信フィルタ14’とを含むC0DECにおいて
、受信フィルタ14′の入力段に複数個のスイッチと複
数個の容量からなる選択回路を設けその選択によシ復号
器部6の利得を調整する利得調整部21を有することか
ら構成される。
This embodiment includes an encoder section 5, a decoder section 6, a reference rt voltage source 9 that supplies the same reference voltage to the encoder 7115 and the decoder section 6, and an output magnetic voltage of the reference voltage source 19. tl
--Transmission filter 1 consisting of an output pressure adjustment section 20 for adjusting the output voltage pA, and a suite filter for band limiting the input to the encoder section 5 and smoothing the output of the decoder section 6.
3 and a reception filter 14', a selection circuit including a plurality of switches and a plurality of capacitors is provided at the input stage of the reception filter 14', and the gain of the decoder section 6 is adjusted according to the selection thereof. It is configured by having an adjustment section 21.

すなわ°ら、第6図に2いて謁5図の従来例と異なるの
は、受信フィルタ14’の利得調整部21の設置と、こ
れに伴う従来例で用いていた受信フィルタ14の人力段
に複数個のスイッチと複数個の容量からなる選択回路を
組み込んだ受信フィルタ14′を設けたことにおる。
In other words, what is different from the conventional example shown in FIG. 6 and shown in FIG. A receiving filter 14' incorporating a selection circuit consisting of a plurality of switches and a plurality of capacitors is provided in the receiver.

第6図において、基準電圧源19と出力調整部20によ
シ符号器5のオl」得調整は所望の範囲に調整できたも
のとする。ここにおいて従来の構成では受信側について
調整部が残されていなかったため、受信側の利得調整は
不可能であった。′2I−実施例においては、受信フィ
ルタ14′と利得調li部21を用いて、送信側のオロ
得調堅とは独立に受信側の利得調整を行うことが可能と
なる。
In FIG. 6, it is assumed that the reference voltage source 19 and the output adjustment section 20 are able to adjust the output of the encoder 5 within a desired range. Here, in the conventional configuration, no adjustment section was left on the receiving side, so it was impossible to adjust the gain on the receiving side. In the '2I-embodiment, by using the reception filter 14' and the gain adjustment unit 21, it is possible to adjust the gain on the reception side independently of the gain adjustment on the transmission side.

第7図は本実施例の部分詳細回路図で、受1Mフィルタ
14′の入力段の一例をスイッチ群と容量群および入力
段増幅器28で表示したものである。
FIG. 7 is a partial detailed circuit diagram of this embodiment, showing an example of the input stage of the receiving 1M filter 14' by a switch group, a capacitor group, and an input stage amplifier 28.

スイッチ22および23は本来のスイッチ)−キャパシ
タ動作のためのスイッチであり、破線で示した復号器6
のPAM出力波の入力段を構成するものである。スイッ
チ24,25.26および27と容量24’、25’、
26’および27′は、受イぎフィルタ14′の入力段
容量群とスイッチ群を表わすものであp1本実施例にお
いては利得調整部21が2ビツトの選択信号発生回路(
図示していないが公知の技術で容易に形成できる。)で
構成された場合の一例でわる。スイッチ24゜25.2
6および27はいずれもスイッテト・キャパシタ動作と
は関係せず、利得調整部21にょシ選択さn、たスイッ
チだけが導通状態となり、残シのスイッチは必ず非導通
となるものである。ただし、利得調整部21による利得
調整ステップが荒くても可能なときは2ビツトに相尚す
る人力容量の実現方法として、2つのスイッチを同時に
導通せしめて並列接続した谷菫で人力容量を実現するこ
とも可能でめる。この人力容量で周波数特性を#:更せ
ずに利得V@整が実現できる。
Switches 22 and 23 are actual switches)-switches for capacitor operation, and the decoder 6 shown in broken lines
This constitutes the input stage of the PAM output wave. Switches 24, 25, 26 and 27 and capacitors 24', 25',
26' and 27' represent an input stage capacitance group and a switch group of the reception filter 14'. p1 In this embodiment, the gain adjustment section 21 is a 2-bit selection signal generation circuit (
Although not shown, it can be easily formed using known techniques. ). Switch 24°25.2
Both of the switches 6 and 27 are unrelated to the switched capacitor operation, and only the switches selected by the gain adjustment section 21 are conductive, and the remaining switches are always non-conductive. However, even if the gain adjustment step by the gain adjustment section 21 is rough, if possible, as a method of achieving a human power capacity equivalent to 2 bits, the human power capacity is realized by connecting two switches in parallel by simultaneously making them conductive. It is also possible. With this human power capacity, the gain V can be adjusted without changing the frequency characteristics.

このように、受信側フィルタ14’の入力段にお仏て基
準電圧源19と出力電圧調整部20と独立に受信側の利
得調整が実施でさるため、送信側と受信側の利得調整が
細かく行なうことができ特性の優れたC0DECを実現
できる。
In this way, the gain adjustment on the receiving side is performed independently of the reference voltage source 19 and the output voltage adjustment section 20 in the input stage of the receiving filter 14', so that the gain adjustment on the transmitting side and the receiving side can be finely adjusted. Therefore, a CODEC with excellent characteristics can be realized.

第8図は本発明の第2の実施例を示すブロック図でおる
。第8図において第6図に示した第lの実施例との相異
点は、送1Mフィルタ13′に利得調督部29を持って
きたことである。送信フィルタ13′の人力容量を第1
の実施例における受信フィルタ14′と同様にスイッチ
群と柊量群を設けることにより1周波数特性に無関係に
利得調整を行なえるようにしたものである。このことに
よp送信側と受信側を独立に利得調整することができる
FIG. 8 is a block diagram showing a second embodiment of the present invention. The difference in FIG. 8 from the first embodiment shown in FIG. 6 is that a gain adjustment section 29 is provided in the sending 1M filter 13'. The human power capacity of the transmission filter 13' is
Similarly to the receiving filter 14' in the embodiment, by providing a switch group and a filter group, gain adjustment can be performed regardless of one frequency characteristic. This allows the gains to be adjusted independently on the transmitting side and the receiving side.

第9図は不発明の第3の実施例を示すブロック図でおる
。渠9図は出力醒圧調螢部20の出力インピーダンスが
高くなシ迭領側と受(* 1itlJのクロストーク特
性が劣化した際の特性改嵜を行なった実施例である。第
8図に示した第2の実施例との相異点は、出力幅圧g整
s2oの出力に独立してバッファ増幅器30および31
を接続することにより、符号器部5と復号器部6とを分
離して、クロストーク特性の改讐を計ったものであシ、
第1の実施例を示した第6図に適用しても同等の効果は
得られるものである。
FIG. 9 is a block diagram showing a third embodiment of the invention. Figure 9 shows an example in which the characteristics were modified when the crosstalk characteristics of the output side and the receiver (*1itlJ) were deteriorated when the output impedance of the output pressure adjustment section 20 was high. The difference from the second embodiment shown is that buffer amplifiers 30 and 31 are provided independently at the output of the output width pressure g adjustment s2o.
By connecting the encoder section 5 and the decoder section 6, the crosstalk characteristics are improved.
Even when applied to FIG. 6, which shows the first embodiment, the same effect can be obtained.

なお、上記実施例の説明においては、基準電圧源として
ΔVT 形やバンドキャップ形のいずれを用いても実現
できるし、出力磁圧調整部または利得調整部においては
、公知でめる多結晶シリコン導体を用いたヒユーズや、
金属導体の一例でめるることは明らかでおる。
In addition, in the description of the above embodiment, it can be realized by using either a ΔVT type or a bandcap type as the reference voltage source, and a publicly available polycrystalline silicon conductor can be used in the output magnetic pressure adjustment section or the gain adjustment section. A fuse using
It is clear that this can be done using an example of a metal conductor.

(発明の効果) 以上、詳細に説明したと2L不発明によれは、符−@器
部と復号器部のオU得調歪が独立に実施でき、又、バッ
ファ増幅器により符号器部と復号器部が分離され、挿入
損失変動やクロストーク規格を満足して1女定に製造で
さるところの符号器復号器が得られる。
(Effects of the Invention) As described above in detail, according to the 2L invention, the encoder section and the decoder section can perform the O/U gain distortion independently, and the encoder section and the decoding section can be performed by the buffer amplifier. The encoder and decoder parts are separated, and an encoder/decoder that satisfies insertion loss variation and crosstalk standards and can be manufactured in one step is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の符号器復号器の第1の例を示すブロック
図、第2図(a)はスイッチト・キャノ(シフの原理図
、第2図勃)はそのタイミングチャート、第3図、第4
図、第5図はそれぞれ従来の符号器復号器の第2.第3
.第4の例を示すブロック図、第6図は本発明の第1の
実施例を示すブロック図。 第7図はその部分詳細回路図、第8図、第9図はそれぞ
れ本発明の83. 第4の実施例を示すブロック図であ
る。 1・・・・・・アナログ入力端子、2・・・・・・ディ
ジタル出力端子、3・・・・・・アナログ出力端子、4
・・・・・・ディジタル入力端子、5・・・・・・符号
器部、6・・・・・・復号器部、7.8.9・・・・・
・端子、10.11・・・・・・スイッチ、12・・・
・・・接電、13.13’・・・・・・送信フィルタ、
14.14’・・・・・・受信フィルタ、15.16・
・・・・・基準ぼ庄原% 17.18・・・・・・出力
電圧詞饅部、19・・・・・・基準電圧源、20・・・
・・・出力電圧調脱部、21・・・・・・利得調整部、
22〜27・・・・・・スイッチ、24′〜27′・・
・・・・容量、28・・・・・・入力段増幅器、29・
・・・・・利得調説部、30.31・・・・・・出力バ
ッファ増幅器。 阜1杷 争2いC幻 茅Z面 (レフ r−1 t=rz丁 1=nTf7− 卒+梠 半1口 2) Y−7割 卒θ侶 竿グ詔
Figure 1 is a block diagram showing a first example of a conventional encoder-decoder, Figure 2 (a) is a switched cano (Schiff's principle diagram, diagram of Figure 2) is its timing chart, Figure 3 , 4th
5 and 5 respectively show the second example of the conventional encoder/decoder. Third
.. FIG. 6 is a block diagram showing the fourth example, and FIG. 6 is a block diagram showing the first embodiment of the present invention. FIG. 7 is a partial detailed circuit diagram thereof, and FIGS. 8 and 9 are respectively 83. of the present invention. It is a block diagram showing a fourth example. 1...Analog input terminal, 2...Digital output terminal, 3...Analog output terminal, 4
...Digital input terminal, 5...Encoder section, 6...Decoder section, 7.8.9...
・Terminal, 10.11... Switch, 12...
...Electrical connection, 13.13'...Transmission filter,
14.14'... Reception filter, 15.16.
...Reference Boshohara % 17.18 ... Output voltage source, 19 ... Reference voltage source, 20 ...
. . . Output voltage adjustment section, 21 . . . Gain adjustment section,
22~27...Switch, 24'~27'...
... Capacity, 28 ... Input stage amplifier, 29.
... Gain adjustment section, 30.31 ... Output buffer amplifier.阜1 loquat fight 2i C phantom Z side (Ref r-1 t=rz ding 1=nTf7- So + 梠half 1 mouth 2) Y-70% graduation θ shōg edict

Claims (2)

【特許請求の範囲】[Claims] (1)符号器部と、後号器部と%該符号器部および復号
器部に同一の基準重圧を供給する単一の基準電圧源と、
該丞準屈圧源の出力直圧を調整する出カシ圧調整部と、
それぞれ前記符号器部への人力の帯域制限および前記儂
号器部の出力の平滑化をするためのスイッチト・キャパ
アシタからなる送信フィルタ及び受信フィルタとを含む
符号器復号器において、@iJ記送信フィルタあるいは
前記受信フィルタの入力段に搾、数個の名イッチと複数
個の容量刀>、+1;+なる選択回路を設けその選択に
よυ前記符号器部あるいは^IJ記復号器部の利得を調
整する利得調整部を有することを待機とする符号器復号
器。
(1) a single reference voltage source that provides the same reference voltage to the encoder section, the post-coder section and the decoder section;
an output pressure adjustment section that adjusts the output direct pressure of the semi-flexural pressure source;
In an encoder/decoder including a transmission filter and a reception filter each comprising a switched capacitor for manually limiting the band to the encoder section and smoothing the output of the encoder section, @iJ transmission is performed. At the input stage of the filter or the reception filter, a selection circuit including several switches and a plurality of capacitance switches is provided, and the gain of the encoder section or the IJ recording/decoder section is determined by the selection. An encoder-decoder comprising a gain adjustment unit for adjusting the gain adjustment unit.
(2)出力醒圧調鷲部が符号器部と虚号器部へそれぞれ
同一の基準重圧を供給する独立したバッファ増幅器f、
有することからなる特許請求の範囲用(1)項記載の符
号器復号器。
(2) An independent buffer amplifier f whose output voltage adjustment section supplies the same reference pressure to the encoder section and the imaginary signal section, respectively;
An encoder-decoder according to claim (1) comprising:
JP24701483A 1983-12-28 1983-12-28 Coder and decoder Pending JPS60141022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24701483A JPS60141022A (en) 1983-12-28 1983-12-28 Coder and decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24701483A JPS60141022A (en) 1983-12-28 1983-12-28 Coder and decoder

Publications (1)

Publication Number Publication Date
JPS60141022A true JPS60141022A (en) 1985-07-26

Family

ID=17157107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24701483A Pending JPS60141022A (en) 1983-12-28 1983-12-28 Coder and decoder

Country Status (1)

Country Link
JP (1) JPS60141022A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63196121A (en) * 1987-02-09 1988-08-15 Nec Corp Coder and decoder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713833A (en) * 1980-06-28 1982-01-23 Fujitsu Ltd Analog-to-digital converter for pcm circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713833A (en) * 1980-06-28 1982-01-23 Fujitsu Ltd Analog-to-digital converter for pcm circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63196121A (en) * 1987-02-09 1988-08-15 Nec Corp Coder and decoder

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