JPS60164822A - Dc voltage generating circuit - Google Patents

Abstract

PURPOSE:To generate two high-precision DC voltages independent of each other and reduce the circuit scale by making it possible that DC voltages set to values independent of each other are generated with one stabilized power source and a series connection resistance group. CONSTITUTION:A stabilized power source 11 outputs a stabilized voltage 101. The voltage 101 and a negative feedback voltage 106 are supplied to a DC amplifier 21, and the amplifier 21 outputs a DC reference voltage 102. A negative feedback circuit 23 consists of plural switching elements, and plural DC voltages 105 obtained by dividing the voltage 102 by a series connection resistance group 22 are supplied to one ends of these switching elements. The other ends of these switching elements are connected to the negative feedback voltage input terminal of the amplifier 21. Only one of plural switching elements is made conductive to output one of voltages 105 as a voltage 106. An adjusting circuit 24 receives plural voltages 104, which are a part of plural DC voltages of the resistance group 22, and selects fixedly one DC voltage of them and outputs it as a reference voltage 107 to a terminal 26.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a DC voltage generation circuit, and is particularly used as a reference voltage for a composite encoder (hereinafter abbreviated as CODEC), etc. It relates to a circuit that generates voltage.

(Prior Art) A CODEC is a device that converts an input audio signal into a PCM signal, and vice versa, and is also manufactured as a monolithic integrated circuit.

Conventionally, some integrated circuit CODECs do not have a built-in reference voltage generation circuit, but have a configuration shown in the block diagram of FIG. 1 in which a reference voltage is supplied from an external terminal. In this figure (
:'0 In DBC, the analog signal is band-limited to prevent aliasing distortion, is applied to the analog input terminal 1, is converted to an IPcM signal by the encoder 5, and is output from the digital output terminal 2. The PCM signal input from the digital input terminal 4 is converted into 8kHz OPAM (P
u1se Ampl i tude Modul a
t ion ) wave is output from the analog output terminal 3. A reference voltage used for encoder 5 and decoder 6 is supplied from terminal 9.

The reference voltage applied to the terminal 9 is a rounded voltage that is easy to drive with low impedance.
It is thought that the crosstalk characteristics will not normally deteriorate even if used in common.

In this C0DBC of the method shown in Fig. 1, the reference voltage is connected to terminal 9.
Since the voltage is supplied from the circuit, a dedicated terminal for reference voltage/voltage input is required, and external components are required as a reference voltage generation circuit. Therefore, in order to reduce the number of required parts, an integrated circuit in which a reference voltage generation circuit is mounted on a CODHC chip has been developed. In addition, a C0I) BC has appeared in which the encoder and compounder operate with reference voltages of different magnitudes.

FIG. 2 is a block diagram of a conventional CODFliC proposed in response to such technological trends. This C0DBC
Here, reference voltage generation circuits 7 and 8 are provided that independently supply reference voltages to the encoder 5 and decoder 6.
A monolithic IC (all integrated on one chip)
It is manufactured as an integrated circuit) and is 5-. The reference voltage generation circuit 7 consists of a stabilized power supply 11 and an adjustment circuit 12, and the reference voltage generation circuit 8 consists of a stabilized power supply 1
3 and an adjustment circuit 14. The stabilized power supply 11.13 receives DC power supplied from the outside to this C0DBC and outputs a stabilized voltage. This stabilized voltage has little fluctuation in voltage value with respect to voltage fluctuations of input DC power and ambient temperature fluctuations.

The adjustment circuit 12.14 divides the stabilized voltage and outputs a predetermined reference voltage. The accuracy of the reference voltage is extremely high. Therefore, after the stabilized power supply 11.13 is manufactured and the stabilized voltage is determined, the adjustment circuit 12.・By adjusting 14, a reference voltage with the required accuracy is obtained from K. - The conventional reference voltage generation circuit 7.8 shown in FIG. 2, together with the encoder 5 and decoder 6, is implemented as a monolithic IC. Therefore, compared to the method shown in Fig. 1, the C0DI in Fig. 2
In C, a small number of terminals is sufficient, and no external parts are required for the reference voltage generation circuit. However, since each of the reference voltage generation circuits 7 and 8 has one output reference voltage,
6- Two reference voltage generation circuits are required as COI>IC. Therefore, one CODBC has two stabilized power supplies, which requires a large area on the chip and consumes a large amount of power.

Similarly, two mutually independent circuits of the same size are required as adjustment circuits. Therefore, the area occupied by the chip is large. In recent years, the accuracy of the reference voltage has increased and a circuit scale of 6 to 9 bits is required, so the chip area for the adjustment circuit has tended to become larger and larger. Therefore, if a DC voltage generation circuit such as a conventional reference voltage generation circuit is used, it is not easy to realize the CODEC as a monolithic IC, and even if it is realized, it will be expensive.

(Object of the Invention) An object of the present invention is to provide a DC voltage generation circuit that generates two highly accurate DC voltages having mutually independent values, and which requires a small circuit scale.

(Configuration of the Invention) The configuration of the DC voltage generation circuit according to the present invention includes a stabilized power supply that receives DC power and outputs a stabilized DC voltage, a DC amplifier that receives the stabilized voltage, and an output voltage of the DC amplifier. a plurality of resistive elements connected in series that divide the voltage and generate a plurality of DC voltages of different magnitudes; and one end connected to the output terminal of the different DC voltages, and the other end connected to the negative feedback voltage input terminal of the DC amplifier. a plurality of negative feedback circuit connection means whose ends are connected; and means for outputting two voltages of the output voltage of the DC amplifier and the DC voltage, of which the plurality of negative feedback circuit connection means are connected. 1
Only one of the negative feedback circuits becomes conductive, and the negative feedback circuit connecting means that becomes conductive leads the DC voltage that makes the output voltage of the DC amplifier within a predetermined range to the negative feedback voltage input terminal.

(Example) Next, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a block diagram of a first embodiment of the invention.

The stabilized power supply 11 outputs a stabilized voltage 101. The DC amplifier 21 receives the stabilized voltage 101 and the negative feedback voltage 106 and outputs a DC reference voltage 102. The series-connected resistance group 22 is made up of a plurality of resistance elements connected in series, and receives the reference voltage 102 at one end and the connection potential at the other end.

The negative feedback circuit 23 includes a plurality of switching elements (corresponding to the negative feedback circuit connection means in the configuration section of the invention described above).

A plurality of DC voltages 1 obtained by dividing the output voltage 102 by a series-connected resistor group 22 are connected to one end of these switching elements.
05 are supplied respectively. The other ends of these switching elements are connected to the negative feedback voltage input terminal of the DC amplifier 21. Then, only one of the plurality of switching elements becomes conductive, and one of the DC voltages 105 is output as a negative feedback voltage 106. The adjustment circuit 24 is
It receives a plurality of voltages 104 that are some of the plurality of DC voltages of the series-connected resistor group 22, selects one of the DC voltages fixedly, and outputs it to the terminal 26 as a reference voltage 107.

In this embodiment, the reference voltage 102 is determined by the negative feedback voltage 106, and the reference voltage 107 is determined by the selection in the adjustment circuit 24. DC amplifier 21. The circuit consisting of the series-connected resistance group 22 and the negative feedback circuit 23 has a function as one adjustment circuit. That is, after the chemotaxis voltage 101 is determined, a switching element to be made conductive is selected in the negative feedback circuit 23 and the negative feedback voltage 101 is set.
6 is determined, and the reference voltage 102 is set within a predetermined error range from the standard value. Since the DC voltage 104 is a voltage obtained by dividing the reference voltage 102, it has much higher accuracy than the stabilized voltage 101. Therefore, the circuit scale of the adjustment circuit 24 is
It is smaller than the adjustment circuits 12 and 14 shown in the figure, and the required number of bits of the circuit is about half, and the reference voltage 107 has the required precision.
is obtained.

Next, one of the two reference voltages is set as the first reference voltage (102 in this example), and the other reference voltage is set as the second reference voltage (107 in this example), and the conventional method shown in FIG. The required circuit scale will be compared in detail with this embodiment.

Now, consider a reference voltage generation circuit in which the first reference voltage is 2.5v±10mV and the second reference voltage is 2.0v±10mV. As the stabilized power supply to be used, for example, a bandgap type with a stabilized voltage of 1.2V±0.3cm is considered. The scale of the adjustment circuit is determined by the number of values that the output reference voltage can take, that is, how many bits can be adjusted.If the number of bits is B, it can be evaluated using the following formula.

(Reference voltage tolerance)・2B-1; (Stabilized voltage fluctuation width)...(1) First, for the conventional method in which the first adjustment circuit and the second adjustment circuit are independent, calculate the required number of bits. Melt.

Substituting numerical values into equation (1) for the first reference voltage adjustment circuit yields 1,',B#7...(3), and 7-bit adjustment is required.

When the number of bits is calculated using equation (1) for the second reference voltage adjustment circuit, it becomes ', B s 7, and 7 bits of adjustment are also required.

Next K, 1c of the nine invention shown in Figure 3? Calculate the required number of bits for the embodiment. The first reference voltage K requires 7 bits, which is the same as in the conventional example. Second reference voltage adjustment circuit 24
varies depending on the value of the first reference voltage 102.

Now, the standard value of the second reference voltage 107 is 2. OV,
Since the standard value of the first reference voltage 102 is 2.5V, the ratio of both voltages is 0.8.

However, it is not always possible to achieve a precision of 0.8 times, and if you try to achieve 0.8 times with a dividing circuit using diffused resistors, etc., it is possible to achieve a dividing precision of 0.8 ± 0.02 times. be.

, °, Bζ3 (7). Therefore, the adjustment circuit 24 for the second reference voltage 107 requires only a very small number of bits, resulting in a small circuit scale.

. Figure 4 shows ΔVT that can be used as the stabilized power supply ll in Figure 3.
FIG. 3 is a circuit diagram of a stabilized power supply. The stabilized power supply in this diagram is N
The difference between the two types of threshold values of the channel type MO8) transistor is taken as the stabilizing voltage 101. M.O.
S) The transistor 33 is an enhancement type! ? ,
MOS transistor 35 is of depletion type. M
08 transistors 33 and 35 load 36 and 37
Together with the current source 34, it constitutes a differential amplification stage.

Terminal 31 is a positive power supply terminal, terminal 32 is a negative power supply terminal,
-t' is shown. The amplifier 38 operates as an error amplifier and controls the gate voltage of the MOS transistor 33 to a DC stable point. The terminal 39 becomes a ΔvT type reference reference voltage power supply terminal.

FIG. 5 is a circuit diagram of a band gap type stabilized power source used as the stabilized power source 11 of FIG. The stabilized power supply in this figure is NPN) transistor 43.44, resistor 45.46
．． 47 and an error amplifier 48 to output a bandgap voltage to the terminal 39.

FIG. 6 is an equivalent circuit diagram of a circuit that further embodies the first embodiment of the present invention shown in FIG. In this specific example, stabilized power source 11 is isometrically represented as battery 60 .

The series-connected resistance group 22 in FIG. 3 is a resistance element R.

This is realized by connecting R1 in series.

13- The negative feedback circuit 23 in Fig. 3 is a MOS) transistor S.
1 to S1 and a control circuit 61. The adjustment circuit 24 in FIG. 3 is a MOS) transistor SIB to Ss.
This is realized by a and a control circuit 62. Control circuit 61.
62 is generally realized by a method of cutting aluminum wire using laser trimming technology, or a method of cutting necessary fuses using a fuse element made of borish or recon.

In the specific example of this figure, after the control circuit 61 adjusts the reference voltage 102 by making any one of the MOS) run raster 81 to Sf0 conductive, the control circuit 61 adjusts the reference voltage 102.
By making any one of the transistors StS to StS conductive (MOS), the reference voltage 1 with a predetermined accuracy is set by K.
Get 07. Resistance element R0, vR representing series connected resistance group
1 is used in common to obtain the reference voltage 102 and the reference voltage 107, and after adjusting the reference voltage 102, the reference voltage 10 is
7 adjustment method.

Therefore, the number of circuit elements required for the adjustment circuit 240 is extremely small, and the area occupied by the chip can be significantly reduced.

14- FIG. 7 is a block diagram of a second embodiment of the present invention. In this embodiment, the output voltage 102 in the embodiment of FIG. 3 is applied to the input terminal of the buffer amplifier 71, and the output voltage of the buffer amplifier 71 is guided to the output terminal 25 as the first reference voltage. The output voltage 107 of the adjustment circuit 24 of FIG. 3 is applied to the input terminal of the buffer amplifier 73, and the output voltage of the buffer amplifier 73 is guided to the output terminal 26 as a second reference voltage.

Using the embodiment of FIG. 7, both reference voltages are connected to the buffer amplifier 7.
1 and 73, the crosstalk characteristics of CODEC are improved. Moreover, since both reference voltages can be supplied with low impedance, digital noise and power supply noise are less likely to be added to the reference voltages, and C0
The AC characteristics of DBC are improved. Note that when buffer amplifiers are connected to both reference voltages as shown in FIG. It is sufficient if it is included in the adjustment scale of the circuit 23 and adjustment circuit 24.

FIG. 8 is a block diagram of a third embodiment of the present invention. This embodiment is a circuit in which a circuit with amplification gain consisting of an amplifier 82 and feedback resistors 83 and 84 is provided in place of the buffer amplifier 73 in the embodiment of FIG.

In the embodiment of FIG. 8, a circuit for obtaining gain is added to the second reference voltage, but it is clear that a similar circuit can be provided on the first reference voltage side to obtain amplification gain.

FIG. 9 is a block diagram of a fourth embodiment of the present invention, and this embodiment is a circuit constructed by converting the connections of feedback resistors 83 and 84 and adjustment circuit 24 in FIG. 8. In the embodiment shown in FIG. 8, the voltage is adjusted by the adjustment circuit 24 and then amplified. On the other hand, in the example shown in Figure WI9,
A conditioning circuit 94 is incorporated into the amplifier circuit. This amplifier circuit includes a resistor 93, an adjustment circuit 94, a resistor 95, and an amplifier 92. The voltage 115 applied to the + (plus) terminal of the amplifier 92 is one of the DC voltages generated by being divided by the series-connected resistor group 22. The embodiment shown in Fig. 8 is the same as the embodiment shown in Fig. 8 in that an amplified reference voltage, which is the output voltage of the series-connected resistor group 22, is obtained, but the embodiment shown in Fig. 9 is suitable for application depending on the voltage ratio of both reference voltages. In some cases.

Adjustment circuit 94 divides input voltage 117 to generate a plurality of DC voltages, and guides one of them to amplifier 92 as output voltage 118 .

FIG. 1θ is a block diagram of a fifth embodiment of the present invention.

In this embodiment, the series-connected resistance group includes resistance elements 112 to 1.
27 and 106, and the first reference voltage 126 is taken out from approximately the midpoint of the resistance elements 112-127. The switch group 103 is composed of MOS transistors like 81 to S7 in FIG.
Like 18 to 816, it is composed of MOS transistors. Control circuits 104 and 107 operate similarly to control circuits 61 and 62, respectively, of FIG. 6.

In the embodiment shown in FIG. 3, the first reference voltage 102 is the output voltage of the DC amplifier 21, but as in the embodiment shown in FIG. A similar reference voltage generation circuit can be obtained by modifying the embodiment of FIG. Furthermore, in the embodiments shown in FIGS. 7 and 8, even if the voltage applied to the + (plus) terminal of the buffer amplifier 71 is one of the divided DC voltages of the series-connected amplifier 22, a similar reference voltage is generated. Of course, the circuit can be realized.

Although the embodiment shown in FIG. 10 does not include a buffer amplifier, if a buffer amplifier is used as shown in FIG. 7, a reference voltage generation circuit with excellent crosstalk characteristics can be realized.

(Effects of the Invention) As described above in detail with reference to the drawings, the present invention allows two highly accurate DC voltages that can be set to mutually independent values to be combined into one stabilized power supply. It can occur in series connected resistors. Therefore, according to the present invention, it is possible to provide a DC voltage generation circuit which generates two highly accurate DC voltages having mutually independent values and which requires a small circuit scale.

18-

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of conventional CODIC,
Fig. 3 is a block diagram of the first embodiment of the present invention, Fig. 4 is a circuit diagram of a ΔvT type stabilized power supply used as a stabilized power supply in this first embodiment, and Fig. 5 is also a block diagram of the first embodiment. A circuit diagram of a bandgap type stabilized power source used as a stabilized power source in the embodiment, FIG. 6 is a circuit diagram of a specific example of the first embodiment of the present invention shown in FIG. 3, and FIG. 7 is a circuit diagram of a specific example of the first embodiment of the present invention shown in FIG. FIG. 8 is a block diagram of the second embodiment of the invention, FIG. 8 is a block diagram of the third embodiment of the invention, FIG. 9 is a block diagram of the 9!44th embodiment of the invention, and FIG. 10 is the block diagram of the third embodiment of the invention. FIG. 3 is a block diagram of a fifth embodiment of the present invention. l...Analog input terminal, 2...Digital output terminal, 3...Analog output terminal, 4...
...Digital input terminal, 5...Encoder,
6...Decoder, 11.13...Stabilized power supply, 12.14.24.94...Adjustment circuit,
21... DC amplifier, 22... Series connected resistance group, 23... Negative feedback circuit, 25.26.
...Reference voltage output terminal, 33, 35...
MOS) transistor, 36.37...Load, 3
8.48...Error amplifier, 39...Stabilized voltage output terminal, 71.73.82.92...
・Buffer amplifier. 4 - 6 top Y / 謬

Claims (1)

[Scope of Claims] (1) A stabilized power supply that receives DC power and outputs a stabilized DC voltage, a DC amplifier that receives the stabilized voltage, and the output voltage of this DC amplifier is divided to have different magnitudes. a plurality of resistive elements connected in series that generate a plurality of DC voltages;
a plurality of negative feedback circuit connection means each having one end connected to the output terminal of the DC voltage different from each other and the other end connected to the negative feedback voltage input terminal of the DC amplifier; 2') of the DC voltage, only one of the plurality of negative feedback circuit connection means becomes conductive, and the negative feedback circuit connection means that becomes conductive is connected to the DC voltage. A DC voltage generation circuit characterized in that the DC voltage that makes the output voltage of an amplifier within a predetermined range is guided to the negative feedback voltage input terminal. (2. The DC voltage generation circuit according to claim 1, wherein the voltage outputted by the voltage output means is outputted through first and second buffer amplifiers, respectively. Circuit. (3) In the DC voltage generating circuit according to claim 1 or 2, the stabilized power supply includes a first M08) transistor having a first threshold voltage and a second threshold voltage. and a Δ■1 type stabilized power supply having a second M08) transistor in its differential input stage, the stabilized voltage being the difference between the first threshold voltage and the second threshold voltage. Characteristic DC voltage generation circuit. (4) In the DC voltage generation circuit according to claim 1 or 2, the DC voltage generating circuit is characterized in that the stabilized power source is a bandgap type stabilized power source that utilizes the bandgap voltage of a bipolar transistor. Voltage generation circuit. (5) In the DC voltage generating circuit according to claims 2 to 4, the gain of either one of the first and second buffer amplifiers is 1 or more. DC voltage generation circuit. (=) In the DC voltage generating circuit according to claims 2 to 5, the plurality of resistance elements are connected to the negative feedback circuit, and the first series-connected resistance group and the negative feedback circuit are connected to each other. The connecting means is a series-connected resistor network with a second series-connected resistor group that is not connected, and the voltage output means outputs the DC voltage obtained from approximately the midpoint of the first series-connected resistor group to the first buffer amplifier. , and receives a plurality of the DC voltages from the first series-connected resistor group, and guides one of the DC voltages to the input terminal of the second buffer amplifier. (7) The DC voltage generation circuit according to any one of claims 2 to 6, wherein the output voltages of the first and 's2 buffer amplifiers are equal.