JPS60140777A - Buried type semiconductor laser - Google Patents
Buried type semiconductor laserInfo
- Publication number
- JPS60140777A JPS60140777A JP25013883A JP25013883A JPS60140777A JP S60140777 A JPS60140777 A JP S60140777A JP 25013883 A JP25013883 A JP 25013883A JP 25013883 A JP25013883 A JP 25013883A JP S60140777 A JPS60140777 A JP S60140777A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- mesa
- semiconductor
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
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- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電流狭窄をほどこした埋め込み型半導体レー
ザに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buried semiconductor laser with current confinement.
これまでの埋め込み型半導体レーザの構造としては第1
図に示す様な構造が考えられてきた。すなわち、第1図
において、lはn !!!! GaAs基板、2はn型
Ato、 Ga0. As層、3けAjoo5Ga0.
、As活性層、4はP型At04Gao6As層、5は
P型GaAs層、6はAto3.Ga、6. A s高
抵抗層、7はP型不純物拡散層、8は5i02膜、9は
P型電極、10はn型電極をそれぞれ示す。This is the first structure of an embedded semiconductor laser to date.
The structure shown in the figure has been considered. That is, in FIG. 1, l is n! ! ! ! GaAs substrate, 2 is n-type Ato, Ga0. As layer, 3 digits Ajoo5Ga0.
, As active layer, 4 a P-type At04Gao6As layer, 5 a P-type GaAs layer, 6 Ato3. Ga, 6. 7 is a P-type impurity diffusion layer, 8 is a 5i02 film, 9 is a P-type electrode, and 10 is an n-type electrode.
この構造においてはP型電極9.n型電極10KM方向
電圧を印加し、Atoo、Gao、5As活性層3に電
流を注入して発光再結合させてレーザ動作を可能にする
ものであり、前記Ato、、Ga o6.As高抵抗層
6によりメサ領域以外に流れる電流を阻止し、効率よく
メサ部分に電流注入してレーザ発振の効率を高める様に
かされている。In this structure, the P-type electrode 9. A voltage in the direction of 10 KM is applied to the n-type electrode, and a current is injected into the Atoo, Gao, 5As active layer 3 to cause light emission recombination to enable laser operation. The As high resistance layer 6 blocks current flowing outside the mesa region and efficiently injects the current into the mesa region to increase the efficiency of laser oscillation.
しかしながら、電流阻止層となるAtoおGa065A
s高抵抗層6け通常、アンドープのn型層にして050
−6n程度、低濃度のP−型層にしても数Ω−m程度の
抵抗率のものしか得られず、従がって第1図に示した様
にP型不純物拡散層7がAI。350a、6.As高抵
抗層6側にも形成されてしまうため忙、メサ部領域以外
にも電流が流れ易く、発振しきい値電流が高くなるか、
もしくはレーザ発振が困難になる欠点があった。さらに
、発振しきい値電流がP型不純物拡散層7幅に依存する
ために低発振しきい値電流で高効率のレーザ発振を再現
性良く得ることが困難であった。従がって、これを改良
すべく第2図に示す様な構造が提案されており、電流阻
止層がn型At06Gao4As埋め込み層11、P−
型Ato、a 5 Ga o65 A S高抵抗層12
(通常〜1o16t7n1オーダの低濃度)、n型At
o3.Gao65As埋め込み層13を順次積層した3
層構造とからなり、第2図に示す様にメサ部領域以外の
P型不純物拡散層7部分から流れる電流成分をn型At
o、5Gao、A、s埋め込み層13とP−型ALo、
s 5Ga065A s高抵抗層12とのn −P逆バ
イアス接合面と、かつP−型AtO,35GaO,66
As高抵抗層12と禁制帯幅の大きいn型Ato6Ga
o4As埋め込み層11との拡散電位差の大きい接合面
を形成することによって阻止しようとするものである。However, Ato or Ga065A, which becomes the current blocking layer,
s6 high resistance layers, usually undoped n-type layers with 050
Even if the P- type layer has a low concentration of about -6n, a resistivity of only a few Ω-m can be obtained. Therefore, as shown in FIG. 1, the P-type impurity diffusion layer 7 is made of AI. 350a, 6. Since As is also formed on the side of the high resistance layer 6, current tends to flow in areas other than the mesa region, resulting in a high oscillation threshold current.
Alternatively, there was a drawback that laser oscillation became difficult. Furthermore, since the oscillation threshold current depends on the width of the P-type impurity diffusion layer 7, it has been difficult to obtain highly efficient laser oscillation with a low oscillation threshold current with good reproducibility. Therefore, in order to improve this, a structure as shown in FIG. 2 has been proposed, in which the current blocking layer is an n-type At06Gao4As buried layer 11, a P-
Type Ato, a5 Ga o65 A S high resistance layer 12
(usually low concentration on the order of 1o16t7n1), n-type At
o3. 3 in which Gao65As buried layers 13 are sequentially laminated
As shown in FIG.
o, 5 Gao, A, s buried layer 13 and P-type ALo,
s 5Ga065A s n-P reverse bias junction with high resistance layer 12 and P-type AtO, 35GaO, 66
As high resistance layer 12 and n-type Ato6Ga with large forbidden band width
This is attempted to be prevented by forming a junction surface with a large diffusion potential difference with the o4As buried layer 11.
しかしながら、P−型Ato3.Gao65As高抵抗
層12に形成されるP型不純物拡散層7部分から流れる
電流成分は前記P−n接合での拡散電位差だけでは完全
に阻止することは困難であり、特にメサ幅が狭くなりメ
サ部領域に加わる電圧が高くなる程、電流阻止効果が損
なわれるととKなる。さらに、2回目の結晶成長工程に
おいて、n型Ato35Gao65As埋め込み層13
の成長層表面を第2図に示す様にP型GaAs層5メサ
部側面に接する形状に再現性良く成長形成することはむ
つかしく、むしろP型GaAs層5メサ部側面から離れ
た位置に形成されることの方が多い。これは、F型A、
to350ao6’、As高Jん
抵灰層12を成長形成する場合、一般にkt工Ga 、
−8As層メサ部側面と該高抵抗層12の成長溶液と
の濡れを良くし良好な埋め込み成長を達成するためには
、過飽和度の大きな成長溶液を用いなければならず、従
がって結晶成長層厚を制御性良く形成することが困難と
なり、P−型Ato35Gao、As高抵抗層12の埋
め込み形状が第2図に示す様な形状に再現性良く形成で
きないことによる。However, P-type Ato3. It is difficult to completely prevent the current component flowing from the P-type impurity diffusion layer 7 portion formed in the Gao65As high-resistance layer 12 by the diffusion potential difference at the P-n junction. The higher the voltage applied to the region, the more the current blocking effect is impaired. Furthermore, in the second crystal growth step, the n-type Ato35Gao65As buried layer 13
As shown in FIG. 2, it is difficult to grow the surface of the growth layer in a shape that is in contact with the side surface of the mesa portion of the P-type GaAs layer 5 with good reproducibility. There are many things. This is F type A,
To350ao6', when growing the As high J ash resistant layer 12, generally kt, Ga,
-8 In order to improve wetting of the side surface of the mesa part of the As layer with the growth solution of the high-resistance layer 12 and achieve good buried growth, it is necessary to use a growth solution with a high degree of supersaturation. This is because it becomes difficult to form the growth layer thickness with good controllability, and the embedded shape of the P-type Ato35Gao, As high resistance layer 12 cannot be formed with good reproducibility as shown in FIG.
従がって、P−型Ato、、Gao、、 A、s高抵抗
層12部分に形成されるP型不純物拡散層7領域が広く
なり、メサ部領域以外に流れる電流成分が多くなし、レ
ーザ発振が困難になる欠点があった。Therefore, the region of the P-type impurity diffusion layer 7 formed in the P-type Ato, Gao, A, s high-resistance layer 12 is widened, and there is no large current component flowing outside the mesa region, and the laser The drawback was that oscillation was difficult.
本発明の目的は、前記従来の埋め込み型半導体レーザの
欠点を除去し、確実な電流狭窄効果を有し、かつ製作が
容易で、再現性が良好な埋め込み型半導体レーザを提供
するものである。An object of the present invention is to provide a buried semiconductor laser which eliminates the drawbacks of the conventional buried semiconductor laser, has a reliable current confinement effect, is easy to manufacture, and has good reproducibility.
本発明の半導体レーザは、第1導電型の半導体基板上に
1少なくとも第1導電型の第1半導体層と#第1半導体
層よシも禁制帯幅の小さい活性層と該活性層よりも禁制
帯幅の大きい第2導電型の第2半導体層と第2導電型の
第3半導体層を順次積層して成るストライプ状の多層構
造を備え、前記第3半導体層のストライプ幅が第2半導
体層のストライプ幅よりも小さい幅を有し、少なくとも
前記活性層と第1、第2半導体層の側面には該活性層よ
りも禁制帯幅の大きい第2導電型の半導体層を備え、前
記第3半導体層の側面には第1導電型の半導体層を備え
たことに特徴がある。The semiconductor laser of the present invention has at least one first semiconductor layer of the first conductivity type on a semiconductor substrate of the first conductivity type, and an active layer having a narrow bandgap width than the first semiconductor layer; The stripe-shaped multilayer structure is formed by sequentially laminating a second conductivity type second semiconductor layer having a large band width and a second conductivity type third semiconductor layer, and the stripe width of the third semiconductor layer is the same as that of the second semiconductor layer. a second conductivity type semiconductor layer having a width smaller than the stripe width of the active layer and having a larger forbidden band width than the active layer on at least the side surfaces of the active layer and the first and second semiconductor layers; A feature is that a semiconductor layer of the first conductivity type is provided on the side surface of the semiconductor layer.
以下、本発明に係る実施例について図面を参照分と同一
部分は同記号で示しである。Hereinafter, in the embodiments according to the present invention, the same parts as those in the drawings are indicated by the same symbols.
先ず、第1の液相エピタキシャル成長工程において、n
型G a A s基板!上に順次、n型AtGa04
06
As層2、Ato、、Gao、5As活性層3.P型、
klα4Gao。First, in the first liquid phase epitaxial growth step, n
Type G a As substrate! Sequentially on top, n-type AtGa04
06 As layer 2, Ato, , Gao, 5As active layer 3. P type,
klα4Gao.
As層4、P型Ato、 Gao5As層14を形成す
る。An As layer 4 and a P-type Ato, Gao5As layer 14 are formed.
各層厚は、各々1,5μm% 0.1μm、1.5μr
n、1.0μmとした。従来の多層構造と異なる点は、
上記P型11o4 G a 06As層4上にAtの組
成比の大きいP型k10. Ga oB As層14が
積層していることである。The thickness of each layer is 1.5 μm%, 0.1 μm, 1.5 μr, respectively.
n was set to 1.0 μm. The difference from the conventional multilayer structure is that
On the P-type 11o4 Ga 06As layer 4, a P-type k10. The GaoBAs layer 14 is laminated.
すなわち、P型AttGa 、−tA s層4上に積層
するP型At、 Ga 、 −、As層14のλを組成
比yがy>xとなる様に成長形成する。That is, the P-type At, Ga, -, As layer 14 stacked on the P-type AttGa, -tAs layer 4 is grown such that the composition ratio y satisfies y>x.
しかる後、H20□+H,PO4+30H,OHj−y
f ヤ7トを用い、n型GaAs基板1に達するまで
ストライプ状にメサエッチングを行ない、活性領域を有
するメサ部を形成する。次に、HFfiを用いて数秒間
エツチングすると、P型Ato5Gao、 As /i
t I 4のみが選択的にエツチングされて、第3図に
示す様にP型At0. Ga0. As層4のストライ
プ幅よりも0.6μm程幅の狭くなったP型Ato、
Ga0. As層14が形成される。すなわち、第3図
に示す様な層4゜14との間に幅〜0.3μm程度のス
トライプ状の段差部15をメサ部の両側に形成する。次
に1第2の液相エピタキシャル成長工程により上記メサ
部を包囲する様に、n型Ato6Ga o4As埋め込
み層11、P−型Ato35Gao6.As高抵抗層1
2、n型Ato35Ga、65As埋め込み層13を順
次形成する。ここで、ド型Ato3.GaO,,As高
抵抗層12は従来と同様、P型不純物のGeを0.01
at%添加した成長溶液を用いることによって、0.5
Ω−m程度の比抵抗を有するものを形成する。After that, H20□+H, PO4+30H, OHj-y
Mesa etching is performed in a stripe pattern using an f-layer 7 until it reaches the n-type GaAs substrate 1, thereby forming a mesa portion having an active region. Next, by etching for a few seconds using HFfi, P-type Ato5Gao, As /i
Only tI4 is selectively etched to form P-type At0. Ga0. P-type Ato whose width is about 0.6 μm narrower than the stripe width of the As layer 4,
Ga0. As layer 14 is formed. That is, as shown in FIG. 3, striped step portions 15 having a width of about 0.3 μm are formed on both sides of the mesa portion between the layer 4 and the layer 14. Next, in a second liquid phase epitaxial growth step, an n-type Ato6Gao4As buried layer 11, a P-type Ato35Gao6. As high resistance layer 1
2. Sequentially form n-type Ato35Ga and 65As buried layers 13. Here, the de-type Ato3. The GaO,,As high resistance layer 12 contains 0.01 Ge as a P-type impurity, as in the conventional case.
By using a growth solution doped with at% 0.5
A material having a specific resistance of approximately Ω-m is formed.
また、メサ部に段差部15があるため、第2の液相エピ
タキシャル成長工程の2番目に形成するi型AZos5
G3o、6.A S高抵抗層12は段差部15より上
部には成長せず、必らず段差部15部分に止めることが
できる。従がって第3図に示す様に、続いて成長するn
型At0.、Gao、、As埋め込み層13をP型At
o50ao、 As層14メサ部側面に接する形状に形
成できる。In addition, since there is a step part 15 in the mesa part, the i-type AZos 5 formed in the second step of the second liquid phase epitaxial growth process is
G3o, 6. The AS high resistance layer 12 does not grow above the step portion 15 and can always be stopped at the step portion 15 portion. Therefore, as shown in Figure 3, the n
Type At0. , Gao, , the As buried layer 13 is P-type At
o50ao, the As layer 14 can be formed in a shape that is in contact with the side surface of the mesa portion.
これは、段差部を有する各種メサ形状を、種々の過飽和
度を有する成長溶液を用いて結晶成長実験を行なった結
果、段差部分において結晶成長が阻止される液相エピタ
キシャル成長工程に特徴的表性質があり、再現性良く埋
め込み成長を可能ならしめることが判った。As a result of crystal growth experiments using growth solutions with various degrees of supersaturation on various mesa shapes with stepped portions, it was found that the characteristic surface properties of the liquid-phase epitaxial growth process, in which crystal growth is inhibited in the stepped portions, were observed. It was found that it was possible to perform implantation growth with good reproducibility.
しかる後、P型不純物拡散層7をP型AL05Ggo、
sAs層14及びn型Ata、、Ga06.As埋め込
み層13中に形成し、P型電極11、n型電極ioを形
成して本発明に係る埋め込み型半導体レーザが形成さ
′れる。本構造においては、メサ部領域以外のP型不純
物拡散層7部分から流れる電流成分がn型At0BS
Ga6.s5 A S埋め込み層13とP−型Ato3
5Ga o6.As高抵抗層12とのn−P逆バイアス
接合によって完全に阻止されるため、低発振しきい値電
流で高効率のレーザ発振を可能にできる。After that, the P-type impurity diffusion layer 7 is made of P-type AL05Ggo,
sAs layer 14 and n-type Ata, Ga06. The embedded semiconductor laser according to the present invention is formed by forming As in the buried layer 13, and forming the P-type electrode 11 and the n-type electrode io.
´Reru. In this structure, the current component flowing from the P-type impurity diffusion layer 7 portion other than the mesa region is n-type At0BS.
Ga6. s5 A S buried layer 13 and P-type Ato3
5Ga o6. Since this is completely blocked by the n-P reverse bias junction with the As high resistance layer 12, highly efficient laser oscillation can be achieved with a low oscillation threshold current.
第4図は、本発明に係る第2番目の実施例を示す。前述
の実施例と異なる点は、第4図に示す様KP型Ato、
Ga05As層14上にP型Ga A s層5を積層
していることである。これを前述の実施例と同様なエツ
チング工程によって、P型Alo、a Ga asAs
層14部分のみ選択的にエツチングし、段差部15を形
成する。次に、第2の液相エピタキシャル成長工程によ
り、メサ部を包囲する様に各層11,12゜13を +
[次形成する。従がってn型A4+3.Ga o65A
、s層13はP型AZo5 Ga o、B As層14
とP型Ga A s層5メサ部側面に接する形状に形成
される。FIG. 4 shows a second embodiment of the invention. The difference from the above embodiment is that the KP type Ato, as shown in FIG.
The P-type GaAs layer 5 is laminated on the Ga05As layer 14. This was etched into P-type Alo, a Ga as As
Only the layer 14 portion is selectively etched to form a stepped portion 15. Next, by a second liquid phase epitaxial growth process, each layer 11, 12, 13 is grown so as to surround the mesa part.
[Next formation. Therefore, n-type A4+3. Ga o65A
, S layer 13 is P-type AZo5 Ga o, B As layer 14
The P-type GaAs layer 5 is formed in a shape that is in contact with the side surface of the mesa portion.
しかる後、P型不純物拡散層7、P型!M1t。After that, P type impurity diffusion layer 7, P type! M1t.
n型電極10を形成する。この構造においては、前述の
実施例同様に低発振しきい値電流で高効率のレーザ発振
を可能処し、さらKP型GaAs層5をキャップ層とし
て用いているために電極抵抗を低減でき、またP型At
o5Ga、5As層14を薄層化できるために熱抵抗を
も低減でき高温下においてもレーザ発振を充分性なわせ
ることができる。An n-type electrode 10 is formed. This structure enables highly efficient laser oscillation with a low oscillation threshold current as in the above-mentioned embodiments, and furthermore, since the KP-type GaAs layer 5 is used as a cap layer, the electrode resistance can be reduced. Type At
Since the o5Ga, 5As layer 14 can be made thinner, thermal resistance can also be reduced, and laser oscillation can be achieved with sufficient efficiency even at high temperatures.
第5図は、本発明に係る第3番目の実施例を示す。本構
造は、第2図に示した多層構造と同じ層構造を順次形成
した後、これをH2o2+H3Po4十30I(30H
エツチヤントを用い、n型G a A s基板lに達す
るまでストライプ状にメサエッチングを行ない、活性領
域を有するメサ部を形成する。次に1NI(40H+2
0H20□工2チー?ントを用いて、10秒間エツチン
グすると、P型G a A s層5とn型0aAs基板
1のみが選択的にエツチングされて、第5図に示す様l
CP型G a A s層5とP mkl−o4Gao6
As層4との間に段差部15を形成する。さらに、n型
G a A s基板1とn型Ato、 Ga06As層
2との間にも段差部15が形成される。従がって、次の
液相エピタキシャル成長工程によって、上記メサ部を包
囲する様に層11,12.13を順次形成すると、第1
番目に成長するn型Ato6Ga o、4As埋め込み
層11は段差部15があるために、n型GaAs基板1
部のみに確実に形成される。また同様にして、第2番目
に成長するド型AZo、35 Gacis5 A S高
抵抗層12も段差部15部分に止めることができるため
、第5図に示す様Kn型Ato、、Gao、、As埋め
込み層13をP型GaAs層5メサ部側面忙接する形状
で形成できる。FIG. 5 shows a third embodiment of the invention. In this structure, after sequentially forming the same layer structure as the multilayer structure shown in Fig. 2, this is
Using an etchant, mesa etching is performed in a stripe pattern until reaching the n-type GaAs substrate 1, thereby forming a mesa portion having an active region. Next, 1NI (40H+2
0H20 □ Engineering 2 Chi? When etching is performed for 10 seconds using an etching agent, only the P-type GaAs layer 5 and the n-type 0aAs substrate 1 are selectively etched, resulting in a pattern as shown in FIG.
CP type GaAs layer 5 and P mkl-o4Gao6
A step portion 15 is formed between the As layer 4 and the As layer 4 . Further, a step portion 15 is also formed between the n-type GaAs substrate 1 and the n-type Ato, Ga06As layer 2. Therefore, when layers 11, 12, and 13 are sequentially formed to surround the mesa portion in the next liquid phase epitaxial growth step, the first
The n-type Ato6Gao,4As buried layer 11, which grows second, has a stepped portion 15, so the n-type GaAs substrate 1
It is reliably formed only in the area. Similarly, since the second do type AZo, 35 Gacis5 A S high resistance layer 12 can be stopped at the stepped portion 15, the Kn type Ato, Gao, As shown in FIG. The buried layer 13 can be formed in such a shape that it is in direct contact with the side surface of the mesa portion of the P-type GaAs layer 5.
しかる後、P型不純物拡散層7、P型電極9、n型電極
10を形成する。この構造においては、従来と同様の多
層構造であってもキャップ層となるP型G a A s
層5メサ部側面に接する形状にn型Ato、5sGa(
16,As mめ込み層13を形成できるため、前述の
2実施例よりも簡便にかつ再現性よく埋め込み成長を可
能ならしめ、低発振しきい値電流で高効率のレーザ発振
を可能にする。Thereafter, a P-type impurity diffusion layer 7, a P-type electrode 9, and an n-type electrode 10 are formed. In this structure, even if it is a multilayer structure similar to the conventional one, P-type GaAs serves as the cap layer.
N-type Ato, 5sGa (
16. Since the As m embedded layer 13 can be formed, embedded growth can be performed more easily and with better reproducibility than in the above two embodiments, and highly efficient laser oscillation can be achieved with a low oscillation threshold current.
また、第1〜3番目の実施例に示した様に、本発明の構
造においては、P型不純物拡散層及びP型電極幅を従来
構造よりも広くしても電流狭窄効果を損なうことがない
ため、放熱特性も改善され高温下においてもレーザ発振
を充分性なわせることができる。Furthermore, as shown in the first to third embodiments, in the structure of the present invention, the current confinement effect is not impaired even if the P-type impurity diffusion layer and the P-type electrode width are made wider than in the conventional structure. Therefore, the heat dissipation characteristics are also improved, and laser oscillation can be performed satisfactorily even at high temperatures.
以上、述べた様に本発明によれば、従来の半導体レーザ
の欠点を除き、メサ領域以外へ流れる電流を有効に阻止
でき、低発振しきい値電流、高効率のレーザ発振を可能
とするばかりでなく放熱特性及び再現性、量産性にも優
れた半導体レーザを形成することができる。As described above, according to the present invention, the drawbacks of conventional semiconductor lasers can be eliminated, current flowing to areas other than the mesa region can be effectively blocked, and low oscillation threshold current and high efficiency laser oscillation can be achieved. In addition, it is possible to form a semiconductor laser with excellent heat dissipation characteristics, reproducibility, and mass productivity.
尚、−以上の実施例では、At、Ga、−fAs −G
aAs系半導体を用い九例について述べたが、他の化合
物半導体、例えばInGaAsP −In系等の半導体
を用いても良いことは言うまでもない。In addition, - in the above embodiments, At, Ga, -fAs -G
Although nine examples have been described using an aAs-based semiconductor, it goes without saying that other compound semiconductors, such as InGaAsP-In-based semiconductors, may also be used.
第1図及び第2図は従来の埋め込み型半導体レーザの構
造断面図、第3図、第4図及び第5図は本発明による実
施例の構造断面図をそれぞれ示す。
図において、1・・・n型Oa A s基板、 2・・
・n型A2o4Ga o、 As層、3・・・Atoo
5Gao1.As活性層、4−P型Ato4Ga o、
a As層、5・・・P型GaAs層、6 ”’ At
0,5Ga0.l、As高抵抗層、7 ・P型不純物拡
散層、8・・・5in2膜、9・・・P型電極、 10
・・・n型電極、11 ・−n型Ato、6 (Ja6
.4 As埋め込み層、12 ・P’型Ato ss
G a O,65A s高抵抗層、13− n型At0
.、Gaoj5As mめ込み層、14−P型At0゜
オ 1 図
72 図
オ 3 図
;+ 4 図1 and 2 are structural sectional views of a conventional buried semiconductor laser, and FIGS. 3, 4, and 5 are structural sectional views of embodiments of the present invention, respectively. In the figure, 1... n-type OaAs substrate, 2...
・N-type A2o4Ga o, As layer, 3...Atoo
5Gao1. As active layer, 4-P type Ato4Gao,
a As layer, 5...P-type GaAs layer, 6''' At
0.5Ga0. l, As high resistance layer, 7 - P type impurity diffusion layer, 8...5in2 film, 9... P type electrode, 10
... n-type electrode, 11 ・-n-type Ato, 6 (Ja6
.. 4 As buried layer, 12 ・P' type Ato ss
GaO, 65A s high resistance layer, 13-n type At0
.. , Gaoj5As m inset layer, 14-P type At0゜O 1 Figure 72 Figure O 3 Figure; + 4 Figure
Claims (1)
第1半導体層と該第1牛導体層よりも禁制帯幅の小さ、
い活性層と該活性層よりも禁制帯幅の大きい第2導電型
の第2半導体層と第2導電型の第3半導体層を順次積層
して成るストライプ状の多層構造を備え、前記第3半導
体層のストライプ幅が第2半導体層のストライプ幅より
も小さい幅を有し、少なくとも前記活性層と第1、第2
半導体層の側面には該活性層よりも禁制帯幅の大きい第
2導電型の半導体層を備え、前記第3半導体層の側面に
は第1導電型の半導体層を備えたことを特徴とする埋め
込み型半導体レーザ。on a semiconductor substrate of a first conductivity type, at least a first semiconductor layer of a first conductivity type and a band gap smaller than that of the first conductor layer;
a striped multilayer structure formed by sequentially stacking a thin active layer, a second semiconductor layer of a second conductivity type having a larger forbidden band width than the active layer, and a third semiconductor layer of the second conductivity type; The stripe width of the semiconductor layer is smaller than the stripe width of the second semiconductor layer, and at least the active layer and the first and second semiconductor layers have a stripe width smaller than that of the second semiconductor layer.
A semiconductor layer of a second conductivity type having a larger forbidden band width than the active layer is provided on a side surface of the semiconductor layer, and a semiconductor layer of a first conductivity type is provided on a side surface of the third semiconductor layer. Embedded semiconductor laser.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25013883A JPS60140777A (en) | 1983-12-27 | 1983-12-27 | Buried type semiconductor laser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25013883A JPS60140777A (en) | 1983-12-27 | 1983-12-27 | Buried type semiconductor laser |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60140777A true JPS60140777A (en) | 1985-07-25 |
Family
ID=17203384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25013883A Pending JPS60140777A (en) | 1983-12-27 | 1983-12-27 | Buried type semiconductor laser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60140777A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0272096A2 (en) * | 1986-12-15 | 1988-06-22 | Sharp Kabushiki Kaisha | A semiconductor laser device |
NL9300850A (en) * | 1992-05-14 | 1993-12-01 | Mitsubishi Electric Corp | SEMICONDUCTOR LASER AND METHOD FOR MAKING THEREOF |
EP1134858A1 (en) * | 2000-03-06 | 2001-09-19 | Agilent Technologies Inc. a Delaware Corporation | Buried mesa semiconductor device |
-
1983
- 1983-12-27 JP JP25013883A patent/JPS60140777A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0272096A2 (en) * | 1986-12-15 | 1988-06-22 | Sharp Kabushiki Kaisha | A semiconductor laser device |
NL9300850A (en) * | 1992-05-14 | 1993-12-01 | Mitsubishi Electric Corp | SEMICONDUCTOR LASER AND METHOD FOR MAKING THEREOF |
EP1134858A1 (en) * | 2000-03-06 | 2001-09-19 | Agilent Technologies Inc. a Delaware Corporation | Buried mesa semiconductor device |
WO2001067570A3 (en) * | 2000-03-06 | 2002-09-12 | Agilent Technologies Inc | Buried mesa semiconductor device |
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