JPS60140600A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE:To reduce testing time substantially by providing a selective nonvolatile memory cell at the time of carrying out a test as well as a using nonvolatile memory cell. CONSTITUTION:A gate in a nonvolatile memory is connected to a word line WD, a drain is connected to either plural number of bit lines B1, B2,..., Bm, and its source is connected to a common grounding power source VSS. When a voltage >=ten-V is impressed to an input terminal 50, a nonvolatile memory cell connected to a word line W2 and that connected to the word line WD are simultaneously selected. However, since the nonvolatile memory cell connected to the word line W2 is in the written condition, only for the nonvolatile memory cell connected to the word line WD writing and reading operations are carried out. The writing process at the time of carrying out a test of a nonvolatile memory is finished by one time; therefore testing time can be shortened substantially.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a nonvolatile memory device, and particularly to a nonvolatile memory area thereof.

(Prior Art) Conventionally, nonvolatile devices are capable of writing input data, arbitrarily erasing the written input data, or arbitrarily reading the written input data. A memory device consists of only peripheral circuits and a nonvolatile memory area that can be used by the user of the nonvolatile memory device, and is tested for write or read operations on all memory cells in the nonvolatile memory area. was running.

However, in only the nonvolatile memory area of the nonvolatile memory device, a write or read test must be performed on all nonvolatile memory cells, so the data write or read test takes an extremely long time. Unless executed twice, AC tests such as accurate access time and write tests for all non-volatile memory cells cannot be performed, and after writing to all the non-volatile memory cells mentioned above, This method has the disadvantage that it is impossible to check whether pit lines or the like are broken or not.

(Object of the invention) The object of the invention is to obtain a simple circuit for solving the above-mentioned problems recognized in the prior art.

(Summary of the Invention) The main point of the present invention is that in addition to nonvolatile memory cells provided in a nonvolatile memory area of a nonvolatile memory device and used in a normal state, selection is made when a test is performed on nonvolatile memory cells. The present invention provides a non-volatile memory cell capable of

(Embodiments of the invention) Examples of the invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a nonvolatile memory region and its vicinity in a conventional FAMO8 (floating gate avalanche injection metal oxide semiconductor) type nonvolatile memory device.

In the figure, lO indicates a non-volatile memory area, 1 1
, 12 , ・= , I n , 21 , 22
,-,2n.

..., ..., ml, m2. ..., mn are nonvolatile memory cells.

- The non-volatile memory cell has approximately 1.5
It has a threshold voltage value of V and is changed to a threshold voltage of about 6V by applying a write voltage of about 21V to its gate and about 15V to its drain.

Next, the operation of the above device will be explained.

In the nonvolatile memory device, the nonvolatile memory cells in which no input data has been written operate with the input data 11'', and the nonvolatile memory cells that have already been written operate with the input data 10''.

The gates of nonvolatile memory cells are word lines W, ,
The drain of the memory cell is connected to any one of the bit lines Bl+B2+...,Bn. , the sources of the memory cells are connected to a common ground power supply Vsa, and selection of nonvolatile memory cells is performed by word lines and bit lines.

D, , D, ,...1. ..., Dn indicates a word decoder block that selects a word line, and 91 word decoders are selected according to the input address buffer output and predecoder output, and write to nonvolatile memory is performed. In operation, like 21V1,
It is configured with a circuit that outputs a voltage of 5v% during a read operation, and a voltage of 0v when no word decoder is selected. Any one word line out of the word lines and any one bit line out of the plurality of bit lines are selected, and when the input data 11'' is written, from the bit line No write voltage is applied. Further, the operation of writing input data 10 is performed by applying a write voltage to the drain of the nonvolatile memory cell and causing a current of about 1 mA to flow.

In addition, in a read operation from a non-volatile memory, the selection of a non-volatile memory cell is executed in the same way as a write operation to a memory cell, and input data is not yet written to the gate voltage of 5V in the non-volatile memory cell. A non-volatile memory cell in a state where input data is not present is in an ON state, and a non-volatile memory cell in a state in which input data has already been written is in an OFF state, and that state is output from the selected focus line.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

In the figure, 2o indicates a nonvolatile memory area provided according to one embodiment of the present invention. The gate of the nonvolatile memory is connected to the word line WD,
In addition, the train has multiple bit lines BI + B
2r...,..., Bm is connected to one, and its source is connected to the common ground power supply V8g.

DD is a word decoder block that selects the word line WD, and has the same input and shape as the word decoder D.

Next, the operation will be explained.

The input terminal 50 is an input terminal for controlling the memory state of the non-volatile memory, and is used by applying a voltage of OV to 10 V when the non-volatile memory is normally operating.

Reference numeral 40 indicates a high threshold buffer, which outputs 'HIGH' (
Voltage 5V) level (hereinafter abbreviated as 'HII),
@LOW' (voltage OV) level (hereinafter abbreviated as 1L) is output.

30 is an inverter, and the state of the terminal 80 is H level (5
V), L level (Ov) is inverted and LL/ is connected to the terminal 90.
Outputs Pel (OV) and H level (5V).

Transistors 60, 70 are N-channel enhancement type transistors with a threshold of about IV. The configuration of other parts is the same as the conventional example shown in FIG.

In the normal operation of the nonvolatile memory device, since a voltage lower than IOV is applied to the input terminal 5C), the terminal 80 is at L level and the terminal 9o is at H level. Correspondingly, transistor 6° is turned off and transistor 7o is turned on. Therefore, the word line WD remains 1 unselected regardless of the address input.
The same operation as the conventional example shown in the figure is performed.

Next, when a voltage of 10 V or more is applied to the input terminal 50, the high threshold buffer 4°ldH level,
Since the output from the inverter 30 is at L level, the transistor 60 is in the ON state and the transistor 70 is in the OFF state.
The state will be as follows. In this case, the word line W is in the "1 unselected" state regardless of the address, and the word decoders D2 and DD are configured with the same input and the same shape, so the word decoders D2 and DD are configured with the same input and the same shape. When the selected address is input, the word decoder DD is selected and the nonvolatile memory cells 12, 22, . . . , m
2 is a non-volatile memory cell ID, 2D,...,...
It works after being replaced by mD.

When all nonvolatile memory cells connected to word line W2 are written, MOS (metal oxide semiconductor)
The transistor 60 consisting of the above can be omitted.

In the above case, when a voltage of 107 or more is applied to the input terminal 50, the nonvolatile memory cells connected to the word line W2 and the nonvolatile memory cells connected to the word line WD are simultaneously selected, but the word Since the nonvolatile memory cells connected to line W2 have already been programmed, write or read operations are performed only on the nonvolatile memory cells connected to word line wD.

Although this embodiment is an example in which a test memory cell corresponding to one word line is provided, the transistors 60 and 70 made of MOS (metal oxide semiconductor) are used as a pre-decoder circuit or an address in the decoder circuit input. It is obvious that test word lines or test memory cells can be provided by inserting them into a buffer circuit or by providing a predecoder or an address buffer.

(Effects of the Invention) As described above, according to the present invention, in a nonvolatile memory device, in addition to the nonvolatile memory area available to the user, it is possible to apply an unrated voltage to the input terminal. Since we have provided a non-volatile memory area that can be selected by ) or the already written state ('0''), the input data writing process during nonvolatile memory testing can be completed in one go, reducing the testing time. It has the advantage that it can be significantly shortened.

Furthermore, by providing a non-volatile memory area at the far end of all bit lines, it is possible to read the ON state of the non-volatile memory cells after performing a write test on all non-volatile memory cells. Another advantage is that it is possible to inspect all pit lines, etc. for disconnections.

Furthermore, since a non-volatile memory area is provided in addition to the non-volatile memory area available to the user, it is not possible to write input data to non-volatile memory cells after assembly into a package. Even in the case of a one-time EFROM, etc., which cannot be erased, it is possible to perform a write test on the memory cell using the non-volatile memory area provided after assembling the package. It has a number of outstanding advantages, such as improving the reliability of memory devices (such as memory devices and programmable read-only memories).

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a memory area and its vicinity in a conventional nonvolatile memory device, and FIG. 2 is a circuit block diagram showing a memory area and its vicinity in a nonvolatile memory device according to an embodiment of the present invention. . DESCRIPTION OF SYMBOLS 10... Nonvolatile memory area, 20... Newly provided nonvolatile memory area, 30... Inverter, 4
0...High threshold buffer, 50...Input terminal for controlling the state of non-volatile memory, 60.70...Transistor, 80.90=...Terminal, Bl r B2+"'
J river p Bm... bit line, W,, w,,...
,..., Wn, WD...word a, D,
, D2,...,..., pD... Word decoder block. Procedural amendment July 16, 1980 Manabu Shiga, Commissioner of the Patent Office1, Indication of the case 1982 Patent Application No. 2452292, Name of the invention Non-volatile memory device3, Person making the amendment Relationship to the case Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order: 1925, Month, Day (voluntary) 6, Column 7 for detailed explanation of the invention in the specification to be amended, Contents of the amendment attached. Correct 7 Correction details 1) On page 7, line 6 of the specification, "Used with an applied voltage of 1 oV." is corrected to "A voltage of 1 oV is applied." 2) On page 8, line 1, "1oV or less" is corrected to "Normally 10V or less."

Claims (1)

[Claims] (1) In a nonvolatile memory device that is capable of writing or reading input data for input information input from a plurality of input terminals,
A nonvolatile memory area is provided that is selected when the nonvolatile memory device is operating normally, and at least one input terminal is connected to the nonvolatile memory device when the nonvolatile memory device is operating normally. The bit line is characterized in that at least one nonvolatile memory cell is provided on every bit line and is driven by a word line that is selected only by applying a voltage higher than the input voltage applied to the bit line. Non-volatile memory device.