JPS60137061A - Semiconductor integrated circuit device and manufacture thereof - Google Patents
Semiconductor integrated circuit device and manufacture thereofInfo
- Publication number
- JPS60137061A JPS60137061A JP25048683A JP25048683A JPS60137061A JP S60137061 A JPS60137061 A JP S60137061A JP 25048683 A JP25048683 A JP 25048683A JP 25048683 A JP25048683 A JP 25048683A JP S60137061 A JPS60137061 A JP S60137061A
- Authority
- JP
- Japan
- Prior art keywords
- base
- electrode
- film
- melting point
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002844 melting Methods 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 27
- 230000008018 melting Effects 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 230000007423 decrease Effects 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 Boron ions Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路特に高密度、高速、低消費電力
な半導体集積回路装置及びその製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuits, and particularly to high-density, high-speed, low-power consumption semiconductor integrated circuit devices and methods of manufacturing the same.
従来例の構成とその問題点
バイポーラＬＳＩを、高速、低消費電力化するだめには
種々の方法かあるが、その中でも一番効果のある方法は
ベースとコレクタ間の容量を小さくすることである。特
に、トランジスタの動作に関係しない不活性ベース領域
を小さくして容量を下げることが重要である。しかしな
がら従来の方法では電極の形成方法による制限のだめ、
不活性ベース領域を小さくすることができなかった。そ
の例を第１図をもとに説明する。第１図は従来のバイポ
ーラトランジスタの断面構造を示す。１はｐ形基板、２
はｎ＋埋込、３は絶縁分離層、４はｐ形ベース、６はｎ
形エミソク、６けエミッタ電極、７−１．７−２．はベ
ース電極である。またａ領域はエミッタ部、ｂ領域は不
活性ベース部、Ｃ領域はベース部である。第１図かられ
かるようにベース部Ｃにおいて不活性ベースｂがかガり
の領域を占有しているのがわかる。例えば通常のトラン
ジスタでは不活性ベース領域はベース領域の％以上を占
めている。その理由としてはエミッタ電極ａとベース電
極すが接しないように間隔をあけねばならず、そのため
余分な領域が生じる。それで不活性ベース領域が大きく
なるわけである。Conventional configurations and their problems There are various ways to make bipolar LSIs faster and with lower power consumption, but the most effective method is to reduce the capacitance between the base and collector. . In particular, it is important to reduce the capacitance by reducing the size of the inactive base region that is not related to the operation of the transistor. However, conventional methods are limited by the method of forming electrodes;
It was not possible to reduce the inert base area. An example of this will be explained based on FIG. FIG. 1 shows a cross-sectional structure of a conventional bipolar transistor. 1 is a p-type substrate, 2
is n+ buried, 3 is insulating isolation layer, 4 is p-type base, 6 is n
Type emitter, 6 emitter electrodes, 7-1.7-2. is the base electrode. Further, the a region is an emitter portion, the b region is an inactive base portion, and the C region is a base portion. As can be seen from FIG. 1, in the base portion C, the inert base b occupies the overcast area. For example, in a typical transistor, the inactive base region occupies more than % of the base area. The reason for this is that the emitter electrode a and the base electrode must be spaced apart so that they do not come into contact with each other, which results in an extra area. Therefore, the inactive base area becomes larger.
当然ながら上記に述べた方法では、バイポーラＬＳＩの
高密度化、高速化、低消費電力化に対して大きな問題が
生じるわけである。Naturally, the method described above poses a major problem in achieving higher density, higher speed, and lower power consumption of bipolar LSIs.
ところで本発明は、不活性ベース領域を小さくするとい
う観点から、高融点金属又はそのシリサイド膜をエミッ
タ電極に用い、ベース電極と多層構造にすることにより
、ベース電極とエミッタ電極の間隔を小さくしてベース
領域の縮小を図ったものである。However, from the viewpoint of reducing the size of the inactive base region, the present invention uses a high melting point metal or its silicide film as the emitter electrode, and forms a multilayer structure with the base electrode, thereby reducing the distance between the base electrode and the emitter electrode. This is intended to reduce the base area.
発明の目的 本発明はこのような従来の問題に鑑み、高密度。purpose of invention In view of these conventional problems, the present invention has been developed to provide a high-density system.
高速、低消費電力を実現することのできる半導体集積回
路装置及びその製造方法を提供することを目的とする。An object of the present invention is to provide a semiconductor integrated circuit device that can achieve high speed and low power consumption, and a method for manufacturing the same.
発明の構成
本発明は、高融点金属又はそのシリサイド膜をエミッタ
電極として用い、ベース電極と多層構造にすることによ
りベース電極とエミッタ電極の間隔を小さくしてバイポ
ーラトランジスタのベース領域の縮小を実現し半導体集
積回路装置の高密度。Structure of the Invention The present invention uses a high melting point metal or its silicide film as an emitter electrode and forms a multilayer structure with the base electrode to reduce the distance between the base electrode and the emitter electrode, thereby reducing the base area of a bipolar transistor. High density of semiconductor integrated circuit devices.
高速、低消費電力化の達成を可能とするものである。This makes it possible to achieve high speed and low power consumption.
実施例の説明
第２図は本発明のバイポーラトランジスタの構造の一例
を示すものである。同図において、８はｐ形基板、９
ｉｊ： ｎ十埋込でコレクタ領域の一部、１０はｎ形エ
ピタキシャル層でコレクタ領域の一部、１ｌ−１ｐ形の
不活性ベース領域でベースのコンタクト領域、１２はｐ
形の活性ベース領域、１３はｎ十エミッタ領域、１４は
ｎ十エミツク領域で多結晶シリコン層、１６は高融点金
属膜又はそのシリサイド膜でエミッタ電極、１６は絶縁
膜、１７は１ｇ金属配線でベース電極となっている。DESCRIPTION OF EMBODIMENTS FIG. 2 shows an example of the structure of a bipolar transistor of the present invention. In the figure, 8 is a p-type substrate, 9
ij: n0 is a part of the collector region, 10 is an n-type epitaxial layer and is a part of the collector region, 1l-1 is a p-type inactive base region and is a base contact region, 12 is a p-type inactive base region and a part of the collector region.
13 is an n0 emitter region, 14 is an n0 emitter region with a polycrystalline silicon layer, 16 is a high melting point metal film or its silicide film as an emitter electrode, 16 is an insulating film, and 17 is a 1g metal wiring. It serves as the base electrode.
第２図において、ベース電極１７は絶縁膜１６を介して
エミッタ電極１５と２層構造になっている。当然なから
、ベース電極１７とエミッタ電極１６は電気的に絶縁さ
れているわけである。平面的には、ベース電極とエミッ
タ電極の間隔は絶縁膜１６の厚みのみである。そのため
不活性ベースの長さｂが非常に狭くなり、その結果ベー
ス長さＣも狭くなっている。これは、第１図と比較する
と釣機になっている。エミッタに高融点金属（又はその
シリサイド）１６を用いる理由はエミッタ引き出し部の
抵抗を下げるためと、高温で熱処理しても多結晶シリコ
ン１４や絶縁膜１６と反応しないからである。通常のム
ｌ配線をエミッタに用いると高温の熱処理を行なうと、
多結晶５ｉ１４や絶縁膜１６と反応し、ム４が侵入して
いく。そのためエミッタ・ベースの接合を破壊したり、
絶縁膜１６の絶縁性が悪く々るからである。In FIG. 2, the base electrode 17 has a two-layer structure with the emitter electrode 15 with an insulating film 16 in between. Naturally, the base electrode 17 and the emitter electrode 16 are electrically insulated. Planarly, the distance between the base electrode and the emitter electrode is only the thickness of the insulating film 16. Therefore, the length b of the inert base becomes very narrow, and as a result, the base length C also becomes narrow. This is a fishing machine compared to Figure 1. The reason for using the high melting point metal (or its silicide) 16 for the emitter is to lower the resistance of the emitter lead-out portion, and also because it does not react with the polycrystalline silicon 14 or the insulating film 16 even when heat treated at high temperature. When ordinary mulch wiring is used as an emitter and subjected to high-temperature heat treatment,
It reacts with the polycrystalline layer 5i14 and the insulating film 16, and the layer 4 invades. This may destroy the emitter-base junction,
This is because the insulating properties of the insulating film 16 are poor.
次に第３図をもとに本発明によるトランジスタの製造方
法を示す。Next, a method for manufacturing a transistor according to the present invention will be described based on FIG.
（Ａ’） ｔず、ｐ形基板８にｎ 埋込層９、絶縁分離
層１０、ｎ形エピタキシャル層１１を順次形成する０
（Ｂ） 全面にｎ にトープされた多結晶シリコン膜１
４を堆積し熱処理してｎ 層１３を形成する。(A') An n-buried layer 9, an insulating separation layer 10, and an n-type epitaxial layer 11 are sequentially formed on a p-type substrate 8. (B) A polycrystalline silicon film 1 doped with n on the entire surface.
4 is deposited and heat treated to form an n layer 13.
この部分はエミッタとなる。次に高融点金属膜１６、絶
縁膜１６を堆積する。エミソタノ々ターンをフォトレジ
スト１８で形成する。高融点金属膜１６の替りにそのシ
リサイド膜を堆積してもよい。高融点金属膜としては、
Ｔ １＋ Ｍ ｏ ＋Ｗ７等が上げられる。This part becomes the emitter. Next, a high melting point metal film 16 and an insulating film 16 are deposited. Emi-striped turns are formed using photoresist 18. Instead of the high melting point metal film 16, a silicide film thereof may be deposited. As a high melting point metal film,
T 1 + M o +W7 etc. are raised.
（Ｇ） エミッタパターンフォトレジスト膜１８をマス
クとして、絶縁膜１６、高融点金属膜１６、多結晶シリ
コン膜１４、ｎ十層１３を異方性のドライエツチングに
より同時に除去する。(G) Using the emitter pattern photoresist film 18 as a mask, the insulating film 16, high melting point metal film 16, polycrystalline silicon film 14, and n+ layer 13 are simultaneously removed by anisotropic dry etching.
（Ｄ） 次に、全面に約２０００〜３ＱＯＯ＾の絶縁膜
１９を堆積する。この工程で高融点金属膜１６多結晶シ
リコン膜１４、ｎ＋層１３の側面及びｎ形エピタキシャ
ル層１１の表面が絶縁膜１９で被覆されることになる。(D) Next, an insulating film 19 of approximately 2000 to 3 QOO^ is deposited over the entire surface. In this step, the high melting point metal film 16, the polycrystalline silicon film 14, the side surfaces of the n+ layer 13, and the surface of the n-type epitaxial layer 11 are covered with the insulating film 19.
（Ｅ） ボロンを全面にイオン注入して、活性ベース領
域１２、不活性ベース領域１１を形成する。(E) Boron ions are implanted into the entire surface to form an active base region 12 and an inactive base region 11.
エミッタ部には多結晶シリコン１４、高融点金属電極１
６、絶縁膜１９が被覆されているので活性ベース領域１
２にはボロンがあまり入らない。しだがって低濃度で浅
く形成される。不活性ベース領域１１上は絶縁膜のみが
形成されているので高濃度で深くなる。ボロンをイオン
注入した後、高温でアニールしても高融点金属１６は融
解しないのでプロセス上問題ヲ生シない。Polycrystalline silicon 14, high melting point metal electrode 1 in the emitter part
6. Since the insulating film 19 is covered, the active base region 1
2 does not contain much boron. Therefore, it is formed shallowly with low concentration. Since only an insulating film is formed on the inactive base region 11, it is highly doped and deep. After boron ion implantation, even if annealing is performed at a high temperature, the high melting point metal 16 does not melt, so there is no problem in the process.
（Ｆ） 異方性のドライエツチングを用いて、絶縁膜１
９を除去する。この時、垂直方向のみ絶縁膜１９がエツ
チングされるので、ｎ 工ζツタ１３多結晶シリコン１
４、高融点金属膜１６の側面には絶縁膜１９が残る。高
融点金属膜上には、先に絶縁膜１６が堆積しているので
、絶縁膜１９けエツチングされるが絶縁膜１６は残るこ
とになる。また不活性ベース１１上の表面は露出する。(F) Insulating film 1 using anisotropic dry etching
Remove 9. At this time, since the insulating film 19 is etched only in the vertical direction,
4. The insulating film 19 remains on the side surface of the high melting point metal film 16. Since the insulating film 16 has been deposited on the high melting point metal film first, the insulating film 19 is etched, but the insulating film 16 remains. Further, the surface on the inert base 11 is exposed.
（Ｇ） ＡＡ等の金属を用いて、ベース電極１７を形成
する。このベース電極１７は絶縁膜１６を介してエミッ
タ電極１５と多層構造をなしている。(G) Form the base electrode 17 using metal such as AA. This base electrode 17 has a multilayer structure with the emitter electrode 15 with an insulating film 16 in between.
平面的にみると、ベース電極１７とエミッタ電極１５の
間隔は絶縁膜１９の厚さく ２０００〜３０００Ａ ）
のみである。したかってベース長さＣが小さくなる。ま
だエミッタ電極として高融点金属又はそのシリサイド膜
を用いるとエミッタ電極形成後でも高温の熱処理か可能
となる。When viewed from above, the distance between the base electrode 17 and the emitter electrode 15 is the thickness of the insulating film 19 (2000 to 3000 A).
Only. Therefore, the base length C becomes smaller. However, if a high-melting point metal or its silicide film is used as the emitter electrode, high-temperature heat treatment can be performed even after the emitter electrode is formed.
以上のように、本実施例によれば、簡単な製造方法で、
不活性ベース領域を小さくすることが出き、トランジス
タのサイズを縮小出来る。As described above, according to this embodiment, with a simple manufacturing method,
The inactive base region can be made smaller and the size of the transistor can be reduced.
発明の効果
以上のように本発明はエミッタ電極として高融点金属膜
又は高融点シリサイド膜を用い、エミッタ電極とベース
電極配線とを多層構造にすることによりエミッタ電極と
ベース電極の間隔を絶縁膜の厚み程度（２０００〜３０
００Ａ）に小さくすることが出来る。さらにエミッタ電
極として高融点金属膜を用いると、電極形成後も高温の
熱処理が可能となる。エミッタ電極とベース電極の間隔
が小さくなると、トランジスタのベース面積が縮小され
る。そのだめベースとコレクタ間の容量が下がるので、
バイポーラ集積回路の高速化、低消費電力化が可能とな
る。例えばベースコレクタ間の容量が半分になると集積
回路のスピードは約３０％改善される。さらにトランジ
スタサイズも小さくなるので高密度化も同様に達成され
る。このように本発明により特性のすぐれた半導体集積
回路装置を実現することかできる。Effects of the Invention As described above, the present invention uses a high-melting point metal film or a high-melting point silicide film as the emitter electrode, and forms the emitter electrode and base electrode wiring into a multilayer structure, thereby reducing the distance between the emitter electrode and the base electrode by increasing the distance between the emitter electrode and the base electrode. Thickness (2000~30
00A). Furthermore, if a high melting point metal film is used as the emitter electrode, high temperature heat treatment is possible even after the electrode is formed. As the distance between the emitter electrode and the base electrode becomes smaller, the base area of the transistor is reduced. As a result, the capacitance between the base and collector decreases,
This makes it possible to increase the speed and reduce power consumption of bipolar integrated circuits. For example, if the base-collector capacitance is halved, the speed of the integrated circuit will be improved by about 30%. Furthermore, since the transistor size becomes smaller, higher density can be achieved as well. As described above, according to the present invention, a semiconductor integrated circuit device with excellent characteristics can be realized.
第１図は従来の半導体装置の構造を示す断面図、第２図
は本発明の半導体装置の構造を示す断面図、第３図Ａ〜
Ｇは本発明の半導体装置の製造工程を示す断面図である
。
０・・・・・・コレクタ領域、１１・・・・・・不活性
ベース領域、１２・・・・・・活性ベース領域、１３・
・・・・・ｎ エミッタ領域、１４・・・・・・多結晶
シリコン層、１６・・・・・・高融点金属膜、１６・・
・・・・絶縁膜、１７・・・・・・ベース電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第３図FIG. 1 is a sectional view showing the structure of a conventional semiconductor device, FIG. 2 is a sectional view showing the structure of the semiconductor device of the present invention, and FIGS.
G is a sectional view showing the manufacturing process of the semiconductor device of the present invention. 0... Collector region, 11... Inactive base region, 12... Active base region, 13.
......n emitter region, 14... polycrystalline silicon layer, 16... high melting point metal film, 16...
...Insulating film, 17...Base electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3
Claims (2)
リサイド膜を用い、上記エミッタ電極上にある絶縁膜を
介して上記エミッタ電極上にベース電極金属膜が配線さ
れていることを特徴とする半導体集積回路装置。(1) A semiconductor integrated circuit characterized in that a high melting point metal film or a high melting point silicide film is used as an emitter electrode, and a base electrode metal film is wired on the emitter electrode via an insulating film on the emitter electrode. circuit device.
高濃度領域を形成する工程、上記高濃度領域上に高融点
金属膜及び第１の絶縁膜を形成する工程、上記第１の絶
縁膜上に形成されたエミッタパターンをマスクとして上
記第１の絶縁膜、上記高融点金属膜、上記高濃度領域を
同時にエツチングする工程、全面に第２の絶縁膜を形成
する工程、上記第１の絶縁膜及び上記高融点金属膜及び
上記高濃度領域の側面のみに第２の絶縁膜を選択的に残
し、ベースコンタクト部を露出させる工程、ベース電極
配線を形成し上記高（３）高融点金属膜として高融点シ
リサイド膜を用いることを特徴とする特許請求の範囲２
項記載の半導体集積回路装置の製造方法。(2) A step of forming a high concentration region to serve as an emitter on the selectively formed semiconductor substrate, a step of forming a high melting point metal film and a first insulating film on the high concentration region, and a step of forming the first insulating film. a step of simultaneously etching the first insulating film, the high melting point metal film, and the high concentration region using the emitter pattern formed above as a mask; a step of forming a second insulating film on the entire surface; a step of etching the first insulating film; A step of selectively leaving a second insulating film only on the side surfaces of the film, the high melting point metal film, and the high concentration region to expose the base contact portion, forming a base electrode wiring and forming the high (3) high melting point metal film. Claim 2 characterized in that a high melting point silicide film is used as the
A method for manufacturing a semiconductor integrated circuit device as described in 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25048683A JPS60137061A (en) | 1983-12-26 | 1983-12-26 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25048683A JPS60137061A (en) | 1983-12-26 | 1983-12-26 | Semiconductor integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60137061A true JPS60137061A (en) | 1985-07-20 |
Family
ID=17208572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25048683A Pending JPS60137061A (en) | 1983-12-26 | 1983-12-26 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60137061A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760870A (en) * | 1980-09-29 | 1982-04-13 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS582065A (en) * | 1981-06-25 | 1983-01-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5886761A (en) * | 1981-10-27 | 1983-05-24 | フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン | Polysilicon mutial connector for bipolar transistor flip-flop |
-
1983
- 1983-12-26 JP JP25048683A patent/JPS60137061A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760870A (en) * | 1980-09-29 | 1982-04-13 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS582065A (en) * | 1981-06-25 | 1983-01-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5886761A (en) * | 1981-10-27 | 1983-05-24 | フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン | Polysilicon mutial connector for bipolar transistor flip-flop |
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