JPS6013360B2 - remote control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a remote control device that performs multiple operations using three frequencies.

When performing multiple operations on a remote control device such as a TV receiver, conventionally various operations were performed by changing the frequency of the operation signal such as ultrasonic waves or by changing the number of pulses to be transmitted. . However, as the number of operations increases, operations that change the frequency require a large number of frequency discrimination circuits as the frequency used increases, and operations that change the number of pulses have disadvantages such as requiring a long transmission time. there were. Furthermore, these operations may cause malfunctions due to various noises present in our living environment. In order to eliminate the drawbacks of the above-mentioned conventional example, the present invention has the following three points:
To provide a remote control device capable of performing a large number of operations by sending one frequency as a clock signal at every other time and two other frequencies at other times. It is something.

Embodiments will be described in detail below with reference to the drawings. Figure 1 shows 1
This is a table representing ~8 as a 3-bit binary number, and it is well known that data from 1 to n can be changed to binary numbers, but in this case, in order to further increase the number of operations n,
It is sufficient to add 4 or more bits, and in this embodiment, the number of operations is 8.

FIG. 2 shows an embodiment of the present invention, in which the reference oscillator 1 is composed of an unstable multipipulator or a CR oscillation circuit, and the counter 2 is composed of a plurality of flip-flops. , 22, 23, 24, 259 and 26 output terminals. 3, 4, 5, 6, 7, 8 are 2
There is an input AND circuit, and 9 is a 6-input OR circuit.

Counter output terminal 22 is input to AND circuits 3 and 6,
24 is connected to the inputs of AND circuits 4 and 7, and 26 is connected to the inputs of AND circuits 5 and 8, respectively. Counter output terminals 2, 22, 23, 249, 25, and 26 are also connected to the inputs of OR circuit 9. Each is connected. '2 is octal - binary 3
It is a bit conversion encoder and has ~8 switch boxes 2-,
Vine turtle 2-2, amount 2-39 12-4......・12
-8 is connected and these switches are closed, outputs A, B, and C of the encoder turtle 2 output "0" or "1" as shown in FIG. 13, second 4, 15
This is an inverter circuit, and these inputs are encoder turtle 2.
are connected to outputs A, B, and C, respectively.

The outputs of inverter 13, force 4, and wing 5 are AND circuits 3 and 4
; outputs A, B, and C of encoder 2 are connected to other input terminals of AND circuits 6, 7, and 8, respectively. The outputs of the AND circuits 3 and 9-5 are connected to the three input terminals of the OR circuit 1, and the outputs of the AND circuit 6 and T9-8 are connected to the 3 input terminals of the OR circuit T9-8. The output of the OR circuit 9 is connected to the oscillation instruction terminal 6a of the oscillation circuit 16. It is a capacitive circuit, and the oscillation frequency change terminal 16b of the oscillation circuit 16 is a capacitor circuit.
Each is connected to the turtle 6c. The output of the OR circuit 10 is connected to the capacitive circuit 7, and the output of the OR circuit 18 is connected to the capacitive circuit SI.
A speaker, a light emitting diode, or the like that converts an electric signal into ultrasonic waves, light, or the like is connected to d. Next, the operation of this embodiment will be explained.

As shown in Figure 3, the reference oscillator 1 is an oscillator that oscillates at a constant period, and for example, the period is 20 s
Let it be ec. When this oscillation output signal is released to the counter 2, "in synchronization with the period of the oscillator 1, the output terminal 21722
923, 24, 25, 26 are the specified 4 high potentials "1" in sequence
``Other times, the specified low potential is ``0''. This is shown in Figure 3, Figure 3. Note that the counter 2 is configured to start from terminal 2 even when any of the switches 12- and 12-8 is closed. In addition, each cycle time is t, ra, ra, t4, t5, as shown in Figure 3.
t6, and when any of the switches 12-, to 12-8 is closed, the output shown in FIG. 1 is A of the encoder 12,
It appears on the B and C terminals, but an example is "Switch 12".
-4 will be explained below when it is closed. The same applies when closing the other switches, so we will omit the explanation of these.Now, when switch turtle 2-4 is closed,
The A, B and C terminals of the decoder tatami 2 are
”, “0” appears.

Therefore, the outputs of AND circuits 3 to 8 appear as shown in FIG.
The outputs of i are output as shown in the third diagram, respectively. Here, an example of the oscillation circuit 6 and the capacitor circuits 17 and 18 is shown in FIG.

The oscillation circuit quantity 6 includes transistors TR, TR2, resonance capacitor C, and resonance coil 1 "feedback capacitor C".
2~Bias resistor R, , R2 "Composed of power supply BAT.

In addition, the capacitor circuits 87 and 18 are additional capacitors C3 and C4.
, transistors TR3, TR4, diodes D,, D2,
It is composed of resistors R3 and R4. When a voltage is applied to the oscillation instruction terminal 6a, the oscillation circuit 16 turns on the transistor T.
R2 becomes conductive, and the resonant coil Z "resonant capacitor C,
It oscillates at the frequency Na3 that resonates with. Also, capacitive circuit turtle ^
Even when a voltage is applied to the turtle 8, the transistor TR3 or TR4 becomes conductive and the oscillation frequency change terminals 6b and 6c are turned on.
Since additional capacitors C3 and C4 are added to the oscillation frequency, the oscillation frequency oscillates at a frequency Na determined by L and (C, 10C3), and a frequency Na2 determined by 1 and (C, 10C4). When the switch 2-4 is closed, the voltage shown in FIG.
8, the voltages shown in the 3rd diagram force and y are released. That is, the time t and time t during which voltage is applied to one sickle terminal
3, t5, the oscillation circuit 16 oscillates at 3 (for example, about 42k), and this is expressed as a clock signal by the C signal. oscillates at ``, (for example, about 40k), and this is expressed as the A signal as a data signal.Also, when voltage is applied to the 1& terminal, the oscillation circuit 16
oscillates at a ratio of 2 (for example, 38k ratio), and this is expressed as a B signal as a data signal. That is, when the switch 12-4 is closed, oscillation occurs as shown in FIG. 3, this signal is applied to the speaker 9, and an ultrasonic wave is emitted into the air as an operation signal. FIG. 5 shows an embodiment of the receiver.
An electrical signal conversion element 30 that converts a signal propagating in the air, such as a microphone or a light receiving element, into an electrical signal is connected to an amplifier 31 and amplified to a predetermined size, and is amplified to a predetermined size by a tuned detector 32, 33, 3.
4' are connected, and these outputs are connected to Z waveform shaping circuits 35, 36, and 37, respectively.

The outputs of the waveform shaping circuits 35, 36, and 37 are connected to a 3-input OR circuit 38, and the waveform shaping circuit 3
The output of the waveform shaping circuit 36Z is connected to the clock terminal of the shift register 39, and the output of the waveform shaping circuit 36Z is connected to the input terminal of the shift register 39. Further, the output of the OR circuit 38 is connected to a reset terminal of a counter 41 through a differentiating circuit 40. This shift register 39 is a serial-in, parallel-out shift register, and has three outputs A and B.
, C, and are connected to the input terminal of a decoder 42, which performs binary-octal conversion. Waveform shaping circuit 35
The output of is also connected to the input of a counter 41, the output of which is connected to the gate terminal of a decoder 42. Note that this embodiment is a remote control receiver that can operate up to 8 operations, but in order to increase the number of operations, the 3-bit shift register should be changed to a 4-bit or more shift register, and the decoder should also be changed to a 4-bit or more shift register. It is sufficient to adopt a decoder having an input of Next, the operation of this embodiment will be explained. First, a signal such as ultrasonic wave or light is applied to the electrical signal conversion element 30, and after this signal is amplified to a predetermined magnitude by the amplifier 31, the tuned detectors 32, 33,
34. These tuned detectors 32, 33, 3
4 are tuned to frequencies Na 3, Na 2, and P, respectively, and are configured to be detected. These detection outputs are applied to waveform shaping circuits 35, 36, and 37, respectively, to absorb impulse noise and sharpen the rise and fall characteristics to form a pulse waveform. Moreover, the waveform shaping circuit 35
The structure is such that the fall time is slightly delayed (about 2 seconds). When a signal such as an ultrasonic wave or light as shown in FIG. produces the output shown. As mentioned above, the falling edge of FIG. 6A is somewhat delayed with respect to the signal at the beginning of FIG.
Further, the output of the OR circuit 38 is as shown in FIG. 6-2. The shift register 39 responds to the rising edge of the waveform applied to the clock terminal by changing the "0" value applied to the input terminal at that time.
” or “1”. The output of the OR circuit 38 is differentiated by a differentiating circuit 40', and at the rising edge, a counter 41
Reset. The output waveform of the differentiating circuit 40 is shown as a tree in FIG. The counter 41 outputs an output signal to the output terminal for a time TB after the time T^ only when three rising signals are applied to the input terminal during a predefined time T^ after being reset. Roll out "1". The time tA is measured to be larger than the time (t. 10 to 10 t3 to t4 to t5 to t6), and the time tB is set here to be approximately equal to t. Note 2
When the binary number is 3 bits, the output is output when there are 3 falling signals as described above, but when the binary number 4 bits or more is used as the operation signal, the output is output when there are 4 or more bits of each binary number. The configuration may be such that the output appears when the falling edge of E is reached. Also, this counter 4
The output waveform of No. 1 is shown in FIG. Now, as shown in FIG. 6A, when the shift register 39 falls, the signal applied to the input terminal is "1" as shown in FIG.
, and when x, the signal applied to the input terminal is "1".
”, and since the signal applied to the input terminal is “0” at y, the 0 time t when the operation signal has finished being applied
From 6 onwards, "1↓"1" and "0" appear on the parallel out output terminals "C", "B", and "A". This A, B,
The waveforms of C are shown in Figure 6. When the signal "1" shown in FIG. 6 is applied to the input terminal of the signal decoder 42 and the signal "1" shown in FIG. 1”, “1”, “0”
'' is restored according to the table in FIG.
1" appears. By connecting the outputs of the decoders 42 to respective terminals (not shown) for predetermined operations such as switching on and off the power supply, switching channels, etc., predetermined operations can be performed by remote control. In the above explanation, switch 12-
Although the explanation has been made regarding the case when switch 4 is closed, the same operation can be performed when other switches are closed.

[Brief explanation of the drawing]

Fig. 1 is a table showing 8-2 conversion data, Fig. 2 is a block diagram showing an embodiment of the transmitter of the present invention, and Fig. 3 is a representative diagram of each part of the transmitter. 4 is a diagram showing details of an oscillation circuit and a capacitance circuit, FIG. 5 is a block diagram showing an embodiment of the receiver of the present invention, and FIG. 6 is a diagram showing waveforms. 1 is a diagram showing typical waveforms of each part of the receiver. 1...Reference oscillator, 2...Counter, 3~
8...2 input AND circuit, 9...6 input OR circuit, 10,11...3 input OR circuit,
12... Octal-binary 3-bit conversion encoder,
13, 14, 15... Inverter circuit, 16.
...Oscillation circuit, 17,18...Capacity circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 Three frequencies f_1, f_2, f_3 are used as transmission signals, and times t_1, t_3, t_5..., t_
2_n_-_1 (or time t_2, t_4, t_6,...
..., t_2_n), the transmission signal f_1 is used as a clock signal.
is generated, and at times t_2, t_4, t_6, ..., t_2
_n (or time t_1, t_3, t_5, ..., t_2
_n_-_1), according to the binary signal n bit data according to the operation content, if the value of each bit is "0", f_2
A transmitter that emits a data signal of f_3 if it is "1", a receiving element that receives ultrasonic waves, light, etc. signals emitted from this transmission, and amplifies this to a predetermined size. an amplifier and each frequency f amplified by this amplifier
A detector tuned to these frequencies discriminates _1, f_2, f_3, and among the detected three signals, time t_1, t_3, t_5..., t_2_n_-_1 (or time t_2, t_4, t_6,... ..., t_2_n) at times t_2, t_4, t_6.
, ..., t_2_n (or time t_1, t_3, t_5
, ..., t_2_n_-_1), and a decoder that discriminates the output of the shift register into predetermined operation contents after the final data is processed. 2 Data signals f_2, f_3 and clock signal f_1
The patent is characterized in that the clock signal f_1 is alternately oscillated and received, and the receiving side uses the rising or falling edge of the clock signal f_1 to determine the data signals f_2 and f_3, and writes the data signals to a shift register. A remote control device according to claim 1.