JPS60133492A - Encoder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a code converter for data secrecy.

Code converters have traditionally been used as a way to prevent data from being decoded by third parties. As a method of scrambling, combining data transliteration and substitution makes it more resistant to decoding; for example, Scientific American (Sci
Entific Amer 1can) Magazine 228
Volume 5, pages 15 to 23 describe a method of dividing data into blocks and repeating transliteration and substitution. However, this method has the drawback that when a transmission error occurs on the transmission path, the error propagates thickly. Furthermore, the length of the key is fixed and cannot be freely changed depending on the purpose.

On the other hand, as a method of freely changing the length of the key, there is a method of using a ranking key generated from a random number generator and taking exclusive logical interest on the ranking key and message for each bit. This method does not cause error propagation. However, this method has the drawback that once the pair of plaintext and ciphertext is known, the key for that part is known, and using that as a clue, all the keys are known and other parts can also be deciphered.

The object of the invention is to provide a code converter using a conversion method that does not have these drawbacks.

According to the present invention, a transposition means for changing the order of a human data series of a code converter, a random number generation means for generating random numbers, a predetermined digital pattern is stored, and a signal output from the transposition means and the random number are stored. A code converter is obtained, comprising a storage means for outputting, as an address, a digital pattern stored at the address.

Further, according to the present invention, a random number generating means for generating random numbers, a storage means for storing a predetermined digital pattern 2, and outputting the digital pattern stored at the address using input data and the random number as an address; A code converter is obtained, comprising transposing means for permuting the bit order of a plurality of digital patterns output from the storage means.

The operating principle of the present invention will be explained in detail below using block diagrams showing embodiments.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, an interleaver 101 swaps the IIM order of the bit sequence, a serial/parallel converter 102 blocks the bit sequence with the swapped order m (mfJ positive integer) bits at a time, and a memory 103 stores the IIM order in advance. A random number generator 10 stores a predetermined m-bit pattern.
4 is generated, and the n (n is a positive integer) bit random number and the output m bits of the serial/parallel converter 102 are combined, m ten n bits, as an address, and the m bit pattern stored at the address is output. do. Hereinafter, in order to simplify the explanation, it will be explained assuming that m = 2.

FIG. 2 shows an example of patterns stored in the memory 103.

In the figure, the 2 bits at the intersection of the 2 bits of random number and the 2 bits of human input data are the 2 bits of output. In this embodiment, the random number generator 104 is a device that generates random numbers, such as a pseudorandom number generator or a device that stores true random numbers in memory. You can also store it in and output it.

This random number sequence serves as a key, but the length of the key can be determined freely. Furthermore, if the contents of the memory 103 and the random numbers are kept secret, even if the pair of plaintext and ciphertext is known, the key will not be known. Moreover, if the interleaver 101 transposes the bit order of the data manually and the method of transposition is kept secret, it will be even more difficult to know the key. Furthermore, in the present invention, even if an error occurs during transmission, error propagation is extremely small. In the example shown in FIG. 2, errors are only magnified by a factor of 1.25 on average. This becomes clear from the following considerations.

-Tt The probability that both of the two received bits will be erroneous is much smaller than the probability that only one bit will be erroneous, so it can be ignored when evaluating error expansion. Therefore, only the case where 2 bits are received and 1 bit is erroneous will be considered.

Consider the case where the random number is (0,0) in FIG.

For example, if the transmitted 2 bits are (1, 1) and a 1-bit error occurs, then (0, 1) or (1, 0) will be received. Then, according to Figure 2, the transmitted signal becomes (1, 1)
In the case of , the decoded value is (1, 0), but (0, 1),
If (1,0) is received, the signal value of lI- is respectively (
1,1), (0,0), which is 7 inches. This shows that when the random number is (00)-transmission (,1M is (1,1), even if a line error occurs, the error propagation is only 1 digit.A similar consideration can be applied to the random number If you do this for other transmitted signals in the case of (0,0), and for all transmitted signals in the case of random numbers (0,1), you will get random numbers (0,0), (0
, 1), it can be seen that the error propagation remains at one digit. Next, consider the same thing for random numbers (X, 0) (1, 1). For example, if the random number is (1, 01) and the 2 bits that were sent are (1,, 1), if a 1-bit error occurs, the number will be (0, 1) or (1, 0).
) is received. Then, according to Fig. 2, the transmitted signal -,1)
The decoded value for is (0,0), but (0,1),
If (1, 0) is not received, the decoded values are (1, 0) respectively.
0), (1, 1). i.e. (0,1)
is received, the error propagation remains at 1 (1
, 0) is received, the number is expanded to 1-i2. At this time, the probability that the transmitted signal (1,1) makes (0,1)K errors is (
1,0) It can be considered that the probability of making an error is equal to Ic, so in the end, the random number is (1,0) and the transmitted signal is (1,1)
It can be seen that in the case of , the error propagation is on average 1.5 digits.

The same thing can be done if the transmission signal of other values and the random number is (1, 1)
For all transmitted signals in the case of , random numbers (1,
In the case of 01, (1°1), a 1-bit error occurs. Considering that the error frequency is the same, in the example shown in Figure 2, the transmission error is on average. 1.25
It is shown that Interleaver <-101 is a device that changes the focus order. Regarding the configuration of this device, please refer to patent application No. 16412/1986.
Interleaver” or patent application number 1982-70
482 [Serial Interleaver].

The memory 103 is, for example, a read-only memory (ROM).
) or random access memory (RAM).

FIG. 3 is a block diagram showing a second embodiment of the invention. In the figure, the data is manually entered two bits at a time, or one bit (for example, the lower bit) is rearranged by an interleaver 101. That is, when the manually entered data is arranged and attention is paid to the lower bits, the order of the first bit is changed. The remaining high-order bits are delayed by a predetermined amount by the delay circuit 301. The delay is determined so that the total delay caused by the interleaver for transmission and reception is the sum of the delays on the receiving side. If this condition is satisfied, the delay circuit 301 can be omitted so that there is no delay, and the total delay can be executed on the receiving side, or conversely, the total delay can be - J < on the transmitting side. can. The other parts of this embodiment are the same as those of the first embodiment, so their explanation will be omitted.

FIG. 4 is a block diagram showing a third embodiment of the present invention. In the figure, the input data is composed of two bits, which are divided into upper bits and lower bits and input to interleaver 401 and interleaver 402, respectively, and the bit order is changed independently. . The other parts of this embodiment are the same as those of the second embodiment, so further explanation will be omitted.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention. In the figure, memory 103 is added to 2
The bit pattern is memorized and the 4-bit [i-
Outputs the 2 bits stored in the atsys as the address. A parallel/serial converter 501 converts a 2-bit series into a serial series using the output of the memory 103, and interleaver 101 switches the bit order of the serial series for output. According to this embodiment, the length of the random number, that is, the length of the key can be freely set.
As in the first embodiment, since the contents of the random number memory 103 are kept secret, the second embodiment is more resistant to decoding and has less error propagation. Further, this example IX1i can be used as the test cranker of the first example. Roughly reversing the roles, this embodiment can be used as a scrambler and the first embodiment can be used as a descrambler.

Instead of using the converter 501, the interleaver V may be used to convert the data in units of 2 bits. Furthermore, in the second embodiment and the third embodiment, the memory J03 can also be moved forward. That is, the order of the bits may be changed after converting the data in the memory 103. These variations (il-) are included within the scope of the present invention.

The present invention can be repeated 401 times using a serial/parallel converter or parallel/serial converter 4 as required, so 7'l'? a K becomes even stronger. Even if an interleaver for changing the bit order is added after the first, second, or third embodiment of the present invention, the decoding VC becomes stronger.

These are examples of applications of the present invention.

As explained in detail above, the present invention can be used to store data in Cheetara communications or files without letting a third party know the contents of the data, and can be extremely effective when applied to data communications or files. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure shows an example of a digital pattern stored in the memory used in the present invention, and FIGS. 3, 4, and 5 show second, third, and fourth embodiments of the present invention, respectively. It is a block diagram. In the figure, 101, +01,402 is an interleaver, 1102 is a serial/parallel converter, 10
3 is a memory, 104 is a random number generator, 301 is a delay circuit, and 501 is a parallel/serial converter.

Claims (1)

[Claims] 1. Transposing means for changing the order of a human data series, random number generating means for generating random numbers, storing a predetermined digital pattern, and transposing the signal output from the transposing means and the random numbers. 1. A code converter comprising: storage means for outputting, as an address, a digital pattern stored at the address. 2. Random number generation means for generating random numbers, storage means for storing a predetermined digital pattern, regarding human data and random numbers as addresses, and outputting the digital patterns stored at the addresses; and the output of the storage means. and transposing means for transposing the order of a plurality of digital patterns.