JPH04115616A - Random code generating device - Google Patents

Abstract

PURPOSE:To shorten the time required for generating a code by reading in every NS piece of the codes of length (k) generated sequentially from a code converting means, and outputting them after rearranging every NS pieces of the codes in random order by an address generated not from a logical system. CONSTITUTION:A shift register sequence generator 131 consists of k-pieces of registers and coefficient multipliers and adders less than k-pieces, and generates shift register sequence whose period (n) is longer than NC. The code converting means 123 takes out the required signal sequence from the shift register sequence generator 131, and converts it into the code of the length (k). A code parallel substituting means 133 takes in every NS pieces of the codes of the length (k) generated sequentially from the code converting means 132 in the memory, and rearranges them by every NS pieces in the random order by a means equivalent to the retrieval of a table not by the logical system, and outputs them. But NS is selected so that an integer (m) to satisfy NS <=mXNS <=n exists. Thus, the time required for generating the code can be shortened.

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to a random code generator that can be used for packet transmission, data communication, data broadcasting, paid broadcasting, etc. (Prior Art) In systems that require a high level of security, data packets are often encrypted when they are transmitted. As shown in FIG. 16, such a data packet Dp includes a header Hd for identifying services such as paid broadcasting and data broadcasting, and an individual identification number 1 for identifying the recipient.
d is added to the encrypted area O8, and a data packet Dp having such a structure is transmitted through the transmission path. Thereby, the data packet Dp can be reliably received by the destination recipient. FIG. 17 is a block diagram showing a communication system through which data packets having the above data structure are transmitted. In FIG. 17, the individual identification number 1d and the encryption key code Key are used as follows. The transmitting device 2 ioo is connected to the receiving device 3 via the transmission path 200.
Data packet DI from 00 (0) to 300 (Nc-1)
) is sent. The transmitting device W100 has a table 101 that associates individual identification numbers Id with encryption key codes Key. For example, when transmitting a data packet to the receiving device 300(0), the transmitting device 100 generates the individual identification number 1d(0) and the encryption key code Key(0) from the table 101.
is extracted, the transmission information If is encrypted in the encryption circuit 102 using the encryption key code Key (0), and the encrypted data is placed in the encryption area Ds and encrypted as shown in FIG. It is sent to the transmission path 200 with an individual identification number Id added thereto. Note that this table 101
The encryption key code Key that corresponds to the individual identification number Id is obtained from the random code generator 103. On the receiving devices 300(0) to 300(Nc-1) side, in the above case, the multiple code and 3301(0) are the individual identification numbers I
d(0) match, so decryption is performed, but the other decoders 301(1) to 301(Nc -1) have individual identification numbers Id(1) to Id(Nc -1) that do not match. Unable to decipher the code. For decoding, each receiver W30
0(0) to 300(Nc-1) require the same encryption key code Key. This encryption key code Key is stored in the internal memory (not shown) of the decoders 301 (0) to 301 (NC-1) as individual identification numbers 1d (0) to Id.
(NC-1) and cannot be read easily. By the way, for those who intentionally try to steal someone else's information, even if the individual identification number 1d can be retrieved relatively easily from the transmission path 200, the code cannot be decoded without the encryption key code Key. By creating a system like this, we have taken security measures to make it impossible to steal someone else's information. That is, in such a system, the individual identification number 1d only plays the role of decryption action, and the encryption key code Key has an important role in terms of security measures. However, in associating the encryption key code Key with the individual identification number 1d, it is necessary to pay attention to the following points. (i) The relationship between the individual identification number 1d and the encryption key code Key must not be expressed by an easily obvious linear combination or the like. The reason for doing this is that the individual identification number Id is
This is because it can be retrieved relatively easily from above 0, so once the individual identification number 1d is known, the encryption key code Key can be found by a certain calculation. In this case, a high level of security cannot be achieved. <rr> The individual identification number 1d and the encryption key code Key should have a one-to-one correspondence, and the same encryption key code Key should not be paired with a different individual identification number 1d. The reason for doing this is to prevent the possibility of someone else's information having the same encryption key code being stolen by intentionally changing the individual identification number 1d of the packet monitor that is input to the decoder. be. Also, coincidentally, the transmission line 20
0, the individual identification number 1d part makes an error and becomes someone else's individual identification number 1d, and the encryption key code Key for that garbled individual identification number 1d happens to be the same as your own, and your information is This is because the information may be leaked to others. Now, regarding the above item (i), it is desirable to implement it by using a random code sequence. For example, the individual identification numbers 1d are arranged in order, and random code sequences are successively generated, which are then made to correspond to each other as the encryption key code Key. Furthermore, in order to satisfy the condition (ii) above, it is necessary to write codes that have occurred in the past into a memory, and to perform successive comparisons so that the codes that have occurred do not overlap with codes that have occurred in the past. FIG. 18 is a flowchart for explaining the operation of generating the encryption key code Key described above, and this flowchart is processed by the random code generation means 103. In FIG. 18, when the random code generating means 103 starts operating, step 2001), initial setting (1=0°tc=
O) is performed (step 2002). Next, the random code generating means 103 generates a random code C (tC) (step 2003). Next, the constant j is reset and set to j-O (step 2004 >. Then, it is determined whether the constant j=t or not (step 2005 ),
If the constant j-I=t, it is determined whether the code C (tC) is the encryption key code Key (j) or not.Step 200
6), unless C(tC)≠Key(j), increment j (j=j+1) and then (step 2007
), the process returns to step 2005. Also, it is determined whether the constant j=t (step 2005)
, if the constant j=t, the code C (tC) is the encryption key code K
It is output as ey(j) (step 2008). Next, after incrementing t (t=t+1) (step 2009), it is determined whether +t is the required number of codes Nc (step 2010), and if t≠Nc, tc is incremented (tC=tC+1) (step 2010). step 2011). In addition, in the case of the above increment (step 2011), c (tc)=
It is also processed when Key(j) is detected. When this increment process (step 2011) is completed, the process returns to the random code C(tc) generation process (step 200).
3). Note that the process ends when t=Nc (step 2012). Through such a processing flow, for example, the encryption key code Key(5) corresponding to the sixth individual identification number 1d(5) is
), the code C(tc) generated by the random code generation means 103 (here, tc≧5) is the same as the previously generated encryption key codes Key(0) to ey(4). When (steps 2003 to 2011)
, writes and outputs the encryption key code Key(5)=C(tc) to the memory (steps 2008 to 2010.2).
012), if C(tc) is Key (0) ~K
If it matches any of ey (4), generate the next random code C(tc+1) and combine it with Key(
0) to Key(4). Repeat this until there are no discrepancies. In this way, different random codes are generated sequentially. Note that the random code generation means 103 discussed here
Specifically, it refers to a means of generating a code that does not have a theoretical system; for example, it refers to a code generating means in which the code is determined by the number that appears when a die is rolled. Hereinafter, the term "random code" refers to a code generated by such a generating means. (Problem to be Solved by the Invention) By the way, a problem occurs when the number of required codes Nc is very large. For example, the above individual identification number Id is 30 (b
it), the encryption key code Key is
2" = 1.1 billion pieces are required. In such a case, in order to generate the (1 billion + 1)th encryption key code Key, at least 1 billion pieces are required so as not to overlap with the past 1 billion codes. For example, if the time required for each comparison is 10 [μS], it will take 10' C3) to compare 1 billion times, which is The present invention has been made in view of the above-mentioned problems, and aims to reduce the number of comparisons and shorten the time required for code generation. [Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention provides a random code generator that can generate codes of different lengths k by NC. In a random code generator that generates
To generate a shift register sequence with a period n greater than NC, extract the next shift register sequence generator and the required signal sequence from the shift register sequence generator, and set the length k.
A code conversion means converts the code into a code, and a code conversion means takes NS codes of length k sequentially generated from the code conversion means into the memory, and randomly converts each NS code using the generated addresses instead of a theoretical system. The present invention is characterized by comprising a code rearrangement means for rearranging the codes in order and outputting the rearranged codes. However, N.C.
NS so that there is an integer m that satisfies 5mXN5≦n
Choose. Further, the code rearranging means may be changed every time the search number NS is rearranged. (Operation) In the above-mentioned conventional technology, ey(t
) was made to correspond to the occurrence of Id(t). Generally, if Id is a serial number, the argument t of Key(t) and Id(t) will be the same. It does not matter whether the relationship between t and Id(t) is random or not. If the relationship between Key(t) and t is random, and t and Id(t) are also random independently of this, then the relationship between Key(t) and Id(t) is also random. Of course, even if t and Id(t) are in a linear combination relationship, if Key(t) and t are random, Key(t) and Td(t) are also random. Therefore, the object of the present invention is to generate a code that satisfies the following conditions in a short time. Code unrelated to the order of occurrence of the 0th term t (random code RC(t))
To be. When the number of codes required for the 0th term is Nc, (t-1)≦He and R
c(1) does not have the same items (does not overlap). (Example) The present invention will be described below based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, a transmitting device 1 transmits data buckets 1 to receiving bags W 3 (0) to 3 (Nc −1) via a transmission path 2.
-Dp is transmitted. The transmitting device 1 has an individual identification number 1d and an encryption key code K.
It has a table 11 that corresponds to ey. For example, when transmitting a data packet to a receiving device 3(1) (i is an arbitrary integer), the transmitting device 1 uses the table 11
, the individual division number 1d(i) and the encryption key code Key(i
) is extracted, and the transmission information If is encrypted in the encryption circuit]2 using the encryption key code ey(i), and this encrypted data is placed in the encryption area O8, and the data is sent to the unencrypted individual identification number. is added and sent to transmission line 2. The encryption key code Key associated with the individual identification number 1d in this table 11 is obtained from the random code generator 13. Here, the random code generator 13 has different lengths k
This device generates NC codes of , and is composed of a shift register sequence generator 131, code converting means 132, and code rearranging means 133 as follows. The shift register sequence generator 131 includes k registers, one or more coefficient units and one or more coefficient units, and one or more and one or less adders, and generates a shift register sequence whose period n is greater than NC. The code conversion means 132 extracts a desired signal sequence from the output of the shift register, the output of the coefficient unit, or the output of the adder of the shift register sequence generator 131 and converts it into a code of length k. The code rearranging means 133 fetches the codes of length k sequentially generated from the code converting means 132 into the memory, NS pieces at a time, and uses a means similar to a table search not based on a theoretical system to divide the codes into NS pieces. output in random order. However, NS is selected such that there is an integer m that satisfies N05mXN5';n. The random code generator 13 is configured as described above. FIG. 2 is a block diagram showing an example of the shift register sequence generator 131, which is constructed from a linear feedback shift register circuit. The shift register series generator 131 constituted by this linear feedback shift register circuit includes a register in which -1 is connected in series to two registers RE10 to RE1 provided with a clock input terminal CT, and a coefficient (-). -hk-1), (k+1) adders AD11 to AD1, and switches SW, and the adder AD1k has an input terminal TI.
is connected, and the output terminal TO is connected to the output of the register RE11. Each output of each register RE 10 to RE Ik-1 is a
t+ is indicated by -1~at, and the output of 1i is written to the coefficient multiplier.
h・at++), and the output of the adder AD1i is (-
It shows the value obtained by adding hi·at+i) from O to i. In such a shift register sequence generator 101,
First, the switch SW is opened when the initial value is first input from the input terminal TI, and when clocks are input from the clock input terminal CT, each register RE10 to RE
An initial value is set to Ik-1. Thereafter, the input signal at the input terminal TI is set to 0'', the switch SW is closed, and the clock signal is input from the clock input terminal CT.As a result, the contents of each register RE10 to RE Ik-1 can be transferred one after another. By repeating , the shift register series is output from the output terminal TO.Then, at the (n-1)th clock, the contents of -1 in each register REIO to RE1 are returned to their original initial values.At this time, The next shift register series is said to have a period n. Fig. 3 is a block diagram showing another example of the shift register series generator 131, which is configured with a linear shift register circuit. The shift 1 register sequence generator 131, which is configured with a shift register circuit, has a register formed by connecting registers RE21 to RE2k in series each provided with a clock input terminal CT, and a register having coefficients (-ho to -hk-1). 20~K for coefficient multipliers, -1 for 2, and k adders AD20~A
, -1 to D2, and a switch SW, and the adder A
An input terminal TI is connected to D20, and an output terminal TO is connected to the output of the register RE2. Note that the switch SW is initially opened when the initial value is input from the input terminal TI. The next shift register series can also be obtained by the shift register series generator 131 constituted by such a linear shift register circuit in the same manner as shown in FIG. By the way, in each of the shift register sequence generators 131, if the codes handled are composed of binary symbols ("O"°'1°"), these will be multiplication and addition modulo 2. Also, If it is a 9-element symbol (01, ..., q-1), it will be multiplication and addition modulo q. Therefore, for example, if q = -3, a k = 3rd order shift register series will be generated. Figure 4 shows the shift register sequence generator 1 when q=3.
31, which shows a three-dimensional M-sequence code generation circuit. Shift register sequence generator 131 for this ternary M sequence code
a is a register formed by connecting three registers RE30 to RE32 in series, one coefficient unit for coefficients (-ho or -h1), and two adders AD31 to AD.
32 and a switch SW, and an adder A D 3
2 is connected to the input terminal TI. Each register RE 3
0~RE 32 output Q

[0] to Q[2]. This embodiment generates a sequence (M sequence) with the same number of stages and the maximum period among the shift register sequences. Generally, the period of the M sequence is n=qk-1. From the next shift register sequence generator having such a period n, a code of length k can be obtained with a period n by appropriately extracting the code.For example, as in the example shown in FIG. 4, CI= In the case of 3, from the third-order shift register sequence generator 131a, n(3'-1) - (27-1) =
26 is obtained, and a shift register sequence with a period of 26 will be generated. Here, 30 in the coefficient unit is (-ho-(-1 mod 3)
=2), or (-hl = (-2mod 3)1)
becomes. Further, mod 3 means an operation modulo 3, and the shift register sequence generator 131a satisfies the generator polynomial H(X)=x'+2x+1. A shift register sequence obtained by such a shift register sequence generator 131a is shown in FIG. FIG. 5(a) is an explanatory diagram of the shift register series obtained from the shift register series generator 131a when the initial values ("O"1°""O") are set in the registers RE30 to RE32. Each register RE 30 as time passes
~RE 32 output Q [2], Q [1], Q
[01 value and decimal (ma) value are shown. Here, the output Q[2 of each register RE30 to RE32
], Q [1], Q [01 values in decimal notation (g+a
), 1a=3” XQ[2] +3XQ[1] +Q[O]
You can use . FIG. 5(b) shows that when the initial values ("2""o"'"O") are set in the registers RE 30 to RE 32,
FIG. 3 is an explanatory diagram of a shift register sequence obtained from a shift register sequence generator 131a. Output Q[2] of each register RE 30 to RE 32 with respect to the passage of time (mouth me) in case of such an initial value
The values of Q[1], Q[0] and the decimal (ma) value are shown. The feature of this code series is that the state of the shift register series is
This point is uniquely determined by the combination of the internal states of each register RE 30 to RE 32. Therefore, in this example, as shown in FIG. 5(a) or FIG. 5(b), (Q[2], Q[1], Q[0]) - (200 ), the next time slot of (Q [2], Q [1
], Q [01) (020). Next, a configuration example of the code conversion means 132 will be explained. The simplest configuration of the code conversion means 132 may be a circuit configuration in which the outputs of each register RE 30 to RE 32 in the circuit shown in FIG. 4 as a specific example of the shift register sequence generator 131 are taken out as they are. . With such code converting means 132, n consecutive code sequences output sequentially do not overlap with each other (no two code sequences are the same). These code sequences satisfy the above condition 0 by setting n≧Nc. In addition, in order to satisfy this condition 0 term, comparison with codes generated in the past, which was conventionally necessary, is no longer necessary in this embodiment. However, this configuration example does not satisfy condition 0 above. This is because these code sequences are generated by linear operations. Therefore, in order to satisfy the above condition 0 term, the code rearrangement means 1
33 may be used to rearrange the codes. First, the code rearranging means 133 converts the code converting means 132
A set of Ns codes L(t) , L(t+1), . . . L(t+
N sl) into memory in sequence. Next, the code rearranging means 133 extracts the data from the memory and randomly rearranges the data by means of generating a memory address having no theoretical system. This output is expressed as R(t
), R(t+1),..., R( are assumed to be 10N sJ. At this time, the range of codes to be rearranged is NS. Therefore, it is necessary to rearrange the codes so that they do not overlap with codes that occurred in the past. The number of codes to be compared is maximum at the (1+N5-1)th code occurrence, and is (NS-1).In other words, even in the 100 millionth code occurrence, the number of codes to be compared is (NS-1). Also, the object of the code to be compared is (Ns
−1) or less. FIG. 6 is a flowchart 1 shown to explain the operation of the above configuration. First, the operation starts in the transmitter 1 (step 6
01). Next, the sending bag W1 is reset, and the random code generator W1B is also reset (to, tc =O) (step 601). Next, the shift register sequence generator 131 of the random code generator 13
A shift register series is generated (step 602). Then, for example, the shift register sequence generator 131 in FIG.
code converting means configured by directly extracting the output of each register of a] 32 performs conversion to a code of length k, and outputs Lm, L(t+1), . . . L(
t+N5-1) is obtained (step 604). Then, the code reordering means 133 converts the code converting means 13
A set of NS codes L(t), L(t+1), . . . , L(t+MS
-1) are sequentially written into the memory (step 605). This is done as follows. L (t) to the address 0 of the memory of the code rearrangement means 133, L (t+ 1) to the address i, L (t+i) to the address i, and the address (Ns - 1) Write L(tlNs −1) into each of them. Next, i=0 (step 606). Then, a random address cH is generated by a means for generating a memory address without a theoretical system (step 6).
07). However, the random address C(t) is 0≦c
It is assumed that the relationship H≦(Ns −1) holds true. Then, constant j is reset to j-0 (step 608). Then, it is determined whether or not it is a constant j-j (step 609), and if it is not a constant j-1, L (tl C
(t)) = R(tl j) Step 610) If L(tlC(t))-R(is not 10j), increment j (j=j+1). From (step 611), the process returns to determining whether the constant j=i (step 609). Also, it is determined whether the constant j=t (step 609),
If constant j=t, R(tlj) is L(tl C(t
)) (step 612). Then, after incrementing j (i=i+1) (step, ・71
613) Determine whether -i is the required number of codes.Step 614) If i #NC, increment tc) (tc = tc±1) (Step 615)
. Note that the process of incrementing tc (step 615) is also executed when it is determined that L (C+C(tl)=R(tl J)) (step 610). When the processing is completed, the process returns to the random address C (tC) generation process (
Step 607). Note that if i = Nc (step 614), t = t
Step 616), then process [t
If ≦NC-1,1, step 617), the process returns to the cyst register series generation process (step 602). Also, if [t>Nc-1), step 617)
, all processing ends (step 618). By operating in this manner, a shift register sequence is generated from the shift register sequence generator 131, the code of this shift register sequence is converted by the code converting means 132, and the code-converted output is randomly generated by the code permuting means 133. By rearranging, random codes will be generated. As described above, the random code generated in this embodiment can be obtained in a shorter time than the conventional code. This will be explained below. In the conventional method, as shown in the flowchart of FIG. 18, there were (tl) comparison targets for the t-th output. If we output Ns codes in random order using a flow similar to this, R(tli), C where 0≦
i≦(Ns-1)], (i-1
> items are subject to comparison. In the flowchart shown in FIG. 6, the steps after step 605 are processed by the code rearranging means 133. Assuming that the probability of occurrence of the memory address C(t) is uniform (1/Ns for each), the number of times the memory is read out necessary to generate R(tlNs -1) is N8 on average. Of these, (Ns - 1) times it matches one of the (Ns - 2) codes R(t), R(tl 1) . . . , R(10N5-2). If the codes read at this time are compared in this order, the probability of each matching is equal, 1/NS. Moreover, the number of comparisons (according to steps 607 to 609 in FIG. 6) until a match is detected is 12, . . . , (Ns-1), respectively.
Therefore, the average number of comparisons in this case is (1/(Ns −1)) X (1+2+ (Ns −
1)) Ns/Ns −1 (1). Since the last Ns times are always compared (Ns −1) times, the average number of comparisons N cmp to generate R(tlNs −1) is Ncmp = (Ns −1) x (Ns / (Ns
-1))+ (Ns -7)-2Ns -1...(
2). R(10i), where O≦i<(NS −1)
Since the objects to be compared when generating are (i-1) codes, the average number of comparisons is smaller than N C1ap in equation (2) above. For example, when N5=100, the average number of comparisons from the above equation (2) is about 199 at most, and conventionally (
For the 1 billion + 1)th code output. Compared to the method that required more than 1 billion comparisons, the generation time can be significantly reduced. Comparing the case of the above embodiment with the conventional one, 1
This means that it can be shortened to 99/109-2/107 or less. Note that if NS is fixed every time, the condition that there exists an integer m such that NC6mXN5≦n·=(3) exists with respect to the period n of the register series (see Examples). Further, it is also possible to make the number of rearrangements Ns variable, and in this case, if the first rearrangement is NS1, the above equation (3) becomes as follows. In general, when Nc and n are close numbers, NS may be chosen small so that formula (4) is satisfied in the final m-th rearrangement. For example, NC=250 and n=255
When N sl= N s2= N 53=80, 250-80X 3≦N sm= N s4≦25
5-80x 310≦Ns4≦15
- (5), the above equation (4) will be satisfied. Furthermore, if NS is randomly changed each time, the randomness of R(1) also becomes human. Note that although the code conversion means 132 to a code of length k has been described as a hardware image, and the N code rearrangement means 133 has been described as a software image, both of them can be realized using software or hardware. For example, a k-order soft register series can be generated by creating a program to imitate the contents of the registers. One embodiment of the invention is as described above. Next, other embodiments of the present invention will be described below. FIG. 7 is a block diagram illustrating an example refinement of a shift register sequence generator of length=8. Third-order shift register series generation circuit 811 shown in FIG.
is a modification of the linear feedback Schiff l-register circuit shown in FIG. In this figure, registers 800 to 807 and adder 808
~810, the 8th order shift register series generation circuit 81
1 is configured. This shift register series generation circuit 811 differs from the configuration shown in FIG. 2 in that it omits an input terminal TI for inputting an initial value, a switch SW, and a clock input terminal CT for shifting. Among the signals of this shift register series generation circuit 811, Q [
7], Q [6], Q [5], Q [4], Q
[3], Q [2], Q [11, Q [01], a code of length k can be obtained. At this time, the code conversion means 812 to a code of length 8 is tangible and intangible, but can generally be constructed from a logic circuit shown in FIG. In FIG. 8, the logic circuit 812a includes Q[7], Q[
6], Q[5], Q[4], Q[3], Q[2], Q[
1], Q O, Q' [4], Q' [3], Q' [2]
and the input terminal of L(t) −(b?, b6
, b5 , b4 , b3 , b
2, bl, bo) output terminals,
and a select l to signal input terminal. However, there are certain restrictions on how the signals can be combined. As previously explained, the state of the shift register sequence generator is uniquely determined by the contents of the shift register 811. In order for the generated code L (t) to have period I], there must be a one-to-one correspondence between L (t) and the contents of each register. Therefore, if Q[4] and Q'[4] are selected at the same time, the contents of register 804 will overlap, so one of the other registers will be omitted. -a, if the shift register generation circuit of the type shown in Fig. 2 is used, the first register from the right will be a.
t+i, -hi at+i, Σ(-h・at+
Selecting at least one of i) as the gist of the code L (t) is a necessary and sufficient condition for L(1) to have period n. Also, as a matter of course, if the selection signal is changed during the generation of L (t) in FIG. 8 and the combination is changed, the period [l is not guaranteed. The generation polynomial H(x) using the shift register sequence generation circuit 811 in FIG. 7 is as follows: An example of the generation of a code L([) of length 8 in the case of H(x)=x''+x' +x3+x2+1 will be explained below. In Figures 9 (1) to (3), the initial values are (Q [7],
Q[6], Q[5], Q[4], Q[3], Q[2]
, Q[1], Q[0] ) (10101011), the output Q [7], Q for time (time)
[6], Q [5], Q [4], Q L3]
, Q [2], Q [month, Q [01 value and output Q
The values of '[4], Q'[3], and Q'[2] and the values of hexadecimal numbers na, rnb, and mC are shown. Also, the decimal numbers m a, m b, m C have length 8
As an example of conversion to ma = (Q [7], Q [6], Q [5], Q
[4], Q [3], Q [21Q [1 piece, Q[O
]) mb = (Q[7], Q[6], Q[5], Q'[4
], Q'[3]Q' [2], Q[1], Q[O] >
mc = <Q[7], Q[6], Q[5], Q'[4
], Q' [3] Q'[2], Q[1], Q[0]
). FIG. 10 is a block diagram showing the t2 side in which code conversion means for converting to a code of length 8 is constructed using a serial/parallel conversion circuit. The code conversion means 812b to a code of length 8 is a register 9.
RE 80 to RE 87 are connected in series, and each register RE
Clock can be input to 80 to RE87, register RE
Input the output Q[0] to 88, and input the output Q[0] to each register RE80.
〜RE 88 output L(on one(b7, b
6. b5. b4. b3. b2. bl, bo) are obtained. It's something new. This clock signal is the same as the shift register series generating circuit 811 shown in FIG. In this case, L(t) matches the contents of each register in the shift register series generation circuit 811 of FIG. 7 eight clocks ago. The shift register series is not limited to the M series. FIG. 11 shows an embodiment of an 8th order shift register series generator that is not the M series. 8th order shift l-register sequence generator 811 that is not an M sequence
The shift register sequence generation circuit shown in FIG. 7 is adders 808a, 809a, 810a, and 810b, and
Output QE7], Q [6], Q [4], Q [
1] is added and input to the register 807, and Q'[7
], Q'[6], Q'[4], and Q'[1]. According to this shift register sequence generator 811b, the generator polynomial H(x) is: )−+(x)=(x+1)′(x5+x”
+1. )=x8→-x7+x6+x' +x+1. This sets the initial values in the order of Q[7] to Q[0] (1oo
ooooo), n = 4
31=124...A sequence with a period of (6) is generated. This sequence is converted as follows by code conversion means for a code of length 8.9 In Figures 12 (1) and (2), the initial value is (Q[7] ~
When Q(O] ) = (10000000), the values of outputs Q[7] to Q[0] and outputs Q'[7] and Q'[6
], Q'[4], Q'[1], and the three septal numbers m
The values of amb and mC (values of code conversion means) are shown, respectively. Also, hexadecimal numbers m a, m b, m C have length 8
For example, m a = (Q [7], Q [6], Q [5
], Q [4], Q [3], Q [2], Q
[1], Q [0] ) mb = (Q'[7], Q'[6], Q[5], Q'
[4], Q[3], Q[2], Q' [1], Q[O]
)m c −(Q' [7], Q [6], Q
[5], Q' [4], Q [3]Q[2],
Q" [1], Q[O]). In Fig. 13, the initial value is (Q[7]~Q[O]) = (1
1010000), the output Q[7] to Q[O] for the time (tinge) at -period n=64
and the output Q' [7], Q' [6], Q' [4
], Q' [1] and the three decimal numbers ma, mb,
The value of mc (value of code conversion means) is shown. Also, the decimal numbers m a, m b, m C have length 8
As an example of conversion to m a = (Q [7], Q [6], Q [5
], Q [4], Q [3], Q [2], Q
[1], Q [0] ) mb - (Q'[7], Q'[6], Q[51, Q'[
4], Q[3], Q[2] Q'[month, Q[O]) m c = (Q'[7], Q[6], Q[
5], Q'[4], Q[3]Q[2], Q'[
1], Q[0]'). The above is the same circuit, only the initial values are different. For convenience, if we give the values of the registers that cannot be taken as the initial values in Figs.
Comparing Sa with case 2, it can be seen that there are no matching codes. This is because the state of the shift register sequence generator is represented by the contents of the register, and there are 124 types of A groups and 6 types.
There are two types of B groups, and no matter which initial value in each group is read, a code L (t) with a period of n-124 or n=62 can be generated. Further, by manipulating the initial values, it is possible to obtain L (t) in which codes corresponding to the A group and the B group coexist. For example, starting from the initial value (10000000), the code L(
t), and they generate time (t =
50), when (11010000) is forcibly read, it moves from group A to group B. Now that L(50+61) has been generated from L(50), the initial value is again changed to the time (ti) in FIG. 12(1).
(100100 corresponding to neHt=50)
11), it returns to group A again. In this way, n = 124 + 62 = 186 non-overlapping codes L (t) can be obtained. A major feature of the shift register series is that it is possible to do this by sequential operations without having the data in FIGS. 12 and 13 in advance, and is effective when n is large. Next, FIG. 14 shows an embodiment of the code rearranging means for NS codes. The rearrangement operation is performed according to the flowchart shown in FIG. 6, and this is an example in which N5=30. The sign of L([) is the same as ma in FIG. 9(1) before rearrangement. R(t) indicates the first 90 after sorting. Comparisons within Ns codes were performed using the codes themselves, but it is also possible to compare them with memoria responses that occurred in the past. Randomly permuting Ns pieces of L (t) is 0
This is equivalent to randomly generating ~(Ns -1) addresses without duplication. So, for example, if the address is (7, 0, 11, 10
) has occurred in the past, the next address to occur is (
7, 0, 11, 10) may be used. For this reason, in the flowchart of FIG. 6, the comparison in step 610 can be performed by comparing addresses (that is, assume that C(t)-i); in this case, if N5=30, then Since J satisfies 0≦j≦29, it can be expressed using 5 bits, and the comparison can be performed using 5 bits. If 50 bits are required for R(t), the number of bits for comparison will be 1/10. Furthermore, it is not necessarily necessary to change the generation order of memory addresses every time Ns rearrangements are made, and a fixed set of random addresses may be provided as a table. In this case, in step 601 of the flowchart of FIG. 6, "t←0, tc←0"
and "j←0" in step 608 of the flowchart in the same figure.
” to “j←0, t, C←0”. FIG. 15 shows the same series as L(t) and R(t) in FIG. 14, and is an example of one that does not satisfy NC5mXN5≦n (...Equation (3)). That is, in the above example, when the above equation (3) is not satisfied, as in this example, R (242) = (29) hex
= <00101001) = overlap in R(10). Such an embodiment also makes it possible to realize the code rearrangement means. As described above, the embodiment of the present invention has the effect of shortening the time required for code generation when the number NC of necessary random codes R(t) is large. Furthermore, in this example, R(
The ratio of the time required to generate the code of [) is less than or equal to ((2NS-1>/t i, and if t = 109 and Ns = 100, then 2/107
This can occur in the following time. [Effects of the Invention] As explained above, the present invention has the effect of shortening the time required for code generation when the number NC of necessary random codes R(t) is large. Further, the present invention provides R(t)
The time required to generate the code can be generated in a significantly shorter time than the number of permutations.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall structure of an embodiment of the present invention, Fig. 2 is a block diagram showing a linear feedback type shift register sequence generator of the embodiment, and Fig. 3 is a block diagram showing the linear feedback type shift register sequence generator of the embodiment. FIG. 4 is a block diagram showing a specific example of the ternary M-sequence shift register sequence generator of the same embodiment, and FIG. 5 is a block diagram showing the generator of FIG. 4. 6 is a flowchart shown to explain the operation of the embodiment, and FIG. 7 is a specific example of the shift register sequence generator and code conversion means of the embodiment. FIG. 8 is a block diagram showing an example of the code conversion means of the same embodiment, and FIGS. FIG. 10 is a block diagram showing another specific example of the same code conversion means, FIG. 11 is a block diagram showing still another specific example of the same code conversion means, and FIGS. 12 (1) and (2) are the same shift registers. Explanatory diagram showing an example of sequence occurrence and code conversion example, 1st
FIG. 3 is an explanatory diagram showing an example of generation of another shift register series and an example of code conversion. FIG. 14 is an explanatory diagram showing an example of random code generation R(t). FIG. 15 is an explanatory diagram showing an example of conversion. ,
FIG. 16 is a diagram for explaining a basic configuration example of a data packet, FIG. 17 is a block diagram of a conventional example, and FIG. 18 is a flowchart for explaining the operation of the conventional example. DESCRIPTION OF SYMBOLS 1... Transmission device, 2... Transmission path, (0)-3(Nc-1) Receiving device, 2... Encryption circuit, 3 Random code generator, 31... Shift register sequence generator, 32... code conversion means, 133... code rearrangement means. Q (1 near 6543210 Q gol; 7641 sb sc (h@xl Figure 12 (2)

Claims (2)

[Claims] (1) In a random code generator that generates NC codes of different lengths k, in order to generate a shift register sequence with a period n greater than NC, a next shift register sequence generator and the shift register sequence generator are used. Take the required signal sequence from and have length k
a code converting means for converting the code into a code; and a code converting means that takes NS codes of length k successively generated from the code converting means into a memory, and randomly converts each NS codes using the generated addresses instead of a theoretical system. 1. A random code generator comprising code rearranging means for rearranging the codes in order and outputting the codes. However, NS is selected so that there is an integer m that satisfies NC≦m×NS≦n. (2) A random code generator characterized in that the reordering means changes the search number NS each time it is reordered.