JPS6013203B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved sequence controller with a microprocessor.

Conventional sequence controllers have been made using ICs and MSIs as elements.

That is, among the functions of minicomputers made of ICs and MSIs, they have been configured to efficiently execute sequence functions, reduce unnecessary functions, and reduce the number of ICs and MSIs used. In recent years, advances in electronics technology have led to the emergence of highly integrated, reliable, and highly functional LSI microprocessors. Microprocessors have functions comparable to or similar to minicomputers, but are often slightly slower in terms of speed. Therefore, if a microprocessor can be used as a sequence controller, some of the functions may be unnecessary, but it is desirable in terms of cost and reliability. However, since microprocessors are designed to implement the functions of minicomputers, if they are used as is, it is usually extremely difficult to efficiently execute sequences due to the following reasons. That is, the logic elements AND and OR in 'word' units can be processed at high speed, but the AND and OR in bit units takes several times as long.
'o It is not possible to store multiple calculation results in pit units and use them efficiently. One command is one word, one word.
8 bits out of 6 bits are used for the instruction code, and 2 4 bits are used for register specification and index specification, so if a new sequence instruction is defined and added, it will consist of 2 words, which will eat up memory. It will be too much.
The present invention can process general-purpose instructions of a microprocessor, sequence instructions using non-contact diagram symbols, and two series of instruction words, and can also efficiently execute sequence instructions, with each sequence instruction consisting of one word. It is an object of the present invention to provide a sequence controller that does not have the above drawbacks.

The present invention will be described below based on an embodiment shown in the drawings.
FIG. 1 is a block diagram showing the general configuration of the present invention.
For convenience of explanation, we use our microprocessor TOSB.
We will proceed with the discussion using AC-4 blood (hereinafter abbreviated as MP) as an example. When a general microcomputer is configured with MP, read-only memory ROM
22, 3, switch SW4, decoder DEC12, and blocks 17 to 26 are removed. In other words, since this embodiment is a micro-programmable MF, it includes a read-only memory ROM, 1 that stores a micro program, an arithmetic control unit ACU 6, a memory M7, and an input/output unit 1/1 that is controlled according to the micro program and performs arithmetic control. 08 and a path control unit BCU6 that controls them. Since the switch SW4 is removed, the ROM address signal lines RM14 and RM15 specifying the address of the read-only memory ROM,1, the output data signal line RD13 of the read-only memory ROM,1, and the arithmetic control Unit ACU5 and pass control unit BCU
6 Signal line CBUSI 1 for mutually exchanging data,
and the output data signal line RD13 that transmits microcommands to the path control unit BCU6, and the signal line M that specifies the address of the memory M7 and input/output unit 1/08.
A9 and the write request data signal line MDIO are connected to the path control unit BCU6.

In this embodiment, the input/output unit 1/0 is also connected to the write/read data signal line MDI, but it may be connected to the signal line of another input/output unit 1/0 coming out from the path control unit BCU6. There is also. Although not shown, there are interrupt signal lines and other control signal lines. It is desirable that an instruction for executing a sequence be composed of one word so as to use as little memory as possible.

Therefore, in the present invention, the instruction code is configured in one word with 4 or 5 bits as shown in FIG. Become. Therefore, two independent instruction systems, a general purpose instruction and a sequence instruction, are provided, and the read-only memories ROM, 1 and ROM 22 are selected by switching the switch SW4 using the switching instruction provided by each instruction. If the sequence instruction microprogram stored in the read-only memory ROM 22 is efficient and the instruction execution speed is fast, there will be no problem, but as mentioned above,
Bitwise operations are slow, and typical microprocessors do not have status flip-flops to easily store the results of these operations. (This flip-flop means something that can be saved even when an interrupt occurs.) On the other hand, bit operations are simpler than word-based operations and can be implemented in hardware. Therefore, in the present invention, (i) a read-only memory ROM for sequence operations and necessary information are provided separately from the MP; , a register that specifies the address of input/output unit 1/0, a circuit that specifies the necessary bits, and a register that specifies the address of input/output unit 1/0.
It has a mask circuit for changing bits, a status register, etc., and (ii) most of these hardware are connected to the signal line CBUSI I, and the signal line CBUS1
The read-only memory ROM3 for hardware control in which data input/output and sequence calculations with the read-only memory ROM22 are added to the decoding circuit DEC1.
2 and is controlled by this signal.

The above will be explained in more detail below with reference to FIGS. 1 and 2.

In other words, SQR18 (sequence register)...second
When a sequence instruction in FIGS. a and b is fetched, it is stored in the arithmetic control unit ACU5 and also stored in SQR, which is used for sequence calculations.

When performing bit operations such as AND and OR, it is necessary to specify not only the word address of input/output unit 1/0 but also the bit within that word. Figure a represents this. Furthermore, when handling numerical values, such as in a timer, bit designation is not necessary as shown in FIG. '.

- CR17 (control register)...Figure 2C
- Since the word specification in the sequence register SQR18 is a relative address, it is necessary to specify the start address of the input/output unit 1/08, and this is done using this CR.

During the first scan after the power source is turned on (PON is "1"), unlike a normal scan, the output is initialized first, so the sequence calculation is different. Furthermore, when the output is simulated (SIM is "1"), the sequence calculation result is not modified and is left as it is, so the sequence calculation becomes normal as well.
PON and SI areas create conditions for sequence operations in this way. 1 OADRI9 (1 address register)...Specifies the address of input/output unit 1/08 defined on the memory address space d in Figure 2.

Control register 17 and sequence register SQR
Using data from 18.

The data length from the sequence register SQR18 is different depending on whether there is a bit specification such as a timer or not.
The switching is also performed. 8 SSTR20 (sequence status register): This is a register that holds calculation inputs and intermediate calculation results necessary for sequence calculations.

The status (C, V.
G, L) correspond to FF1, FSFF, FF○,
FF, and these four bits are also saved as necessary, along with one bit of the program status word indicating the instruction system. For example, when an interrupt occurs, these 4 bits (original program status word) are OLDPS.
It is held as the status of W instead of C, V, G, and L. This allows sequence operations to continue immediately upon return from an interrupt. INV becomes "1" when FFI and FFO are in different states, indicating that the output state is reversed.

DFF is used when counting with a timer counter, etc., and the state of the counting pulses (FF, It becomes "1" when the counting pulse FF,

In other words, INV and DFF are different from the above four statuses, and are simply statuses for ease of sequence calculation, and can be reproduced without being saved at the time of an interrupt. FF1
(Input flip-flop) stores the bit state of the designated input/output unit 1/05 and inputs it from M circle X21.

When FSFF (first sequence flip-flop) is set to "1" in an instruction other than an instruction used at the end of a sequence, such as an output OUT instruction, it indicates that the instruction is at the beginning of the sequence.

In other words, the command used at the end of the sequence becomes "1",
For other instructions, it becomes "0" and identifies the beginning of the sequence. At the beginning of the sequence, unlike normal processing, AND or OR simply brings the state and does not perform any calculations. FF◯ (output flip-flop) is a flip-flop that stores calculation results including intermediate results.

FF (NOI's flip-flop) is an auxiliary flip-flop that temporarily stores FFO.

For example, when using an AND/OR instruction, it is used to save the results of the previous calculations to FF○, FF. ■ MP×(
Multiplexer 21)...Fig. 2 e When the specified 10 words are transmitted, only one specified bit is FFIed.
This is a selection circuit for sending to.

M MR22 (mask register)...Fig. 2 fmV is “1”
”, that is, when it is necessary to transfer the state of the specified bit of the specified word, the exclusive OR (E
XOR) generates a mask word that can be reversed.

For example, when reversing the MSB, the following occurs. (toe
SROM 23 (sequence ROM) This is a main part of the present invention, and can be executed in a short period of one microstep of sequence calculation. Sequence operation is performed using FSFF of sequence status register SSTR20.
, FFo, FF, and INV are the main tasks. FSFF, FFo, FF,, NV is the instruction code (including N) FSFF, FFo, FF,, FF1
, PON, and SIM as variables. Therefore, FSFF,FFo,FF,,IN for all combinations of variables
If V is specified, the calculation will be executed. In SROM23, R
Set the address of OM to these variables and read output to FSF
F,FFo,FF,,MV. Next, the contents of the ROM will be specifically explained. Example of AND instruction Here, the following operation is performed.

In other words, when FSFF is “0” FF.

・(FF1・N+FF1・N)→FF. FSFF is “1”
”, FF1・N+FF1・N→FF.

From the above, the relationship between variables (addresses) and outputs in ROM is expressed as shown in Table 1.

In Table 1, the x mark indicates that the output is the same whether it is "0" or "1". Actually, including the instruction code,
The above ROM output is obtained as the ROM address. Table 1 Examples of AND/OR commands AND/OR involves ORing the result of AND with the previous step.
However, the instruction can be AND/ORed from other instructions.
Since the operation is different depending on whether the previous instruction is AND/OR or the previous instruction is AND/OR, it has two instruction codes: A/OR・S and A/OR.

However, the sequence representation is the same as shown in FIG. Table 2 shows the state of storage in memory of the sequence of FIG. 3, and Table 3 explains the sequence instructions of the sequence of FIG. Address in Table 2
Volume I A ・ 2 A N2 3 0R 3 4 A/OR. S 4 5 A/OR 5 6 00T 16 7 A 6 8 PR RIO 9 T RII 10 0UT 17 11 A 7 12 RST 8 13 PR R12 14 0 R13 15 0UT 18 Table 3 A (And) All inputs OR (OR) which takes AND) A/OR (AND/OR) which takes OR of all inputs (AND/OR) ORs the result of AND with the previous stage ○UT Output) Output A/OR. S (and/oah)
Same as A/OR, but oPR indicating the beginning of the A-OR block (preset) Setting of timer, counter, etc. Current value of delay timer RST (Reset) AND does not hold and Counter reset ○ (Counter) Up force counter A/OR. In S, FFO→FFI FFI. N+FF1, N-naFF.

In A/OR FFI+FF.

-FFI-N+FFI-N)→FF. The above calculations are performed. As with the AND, it is sufficient to create a ROM for all conditions. The contents of the ROM are omitted. By using ROM as described above, {
11 Highly integrated LSI allows solid logic operations with one IC to be performed using one or two ROMs.

For example, in this embodiment, if the instruction code (including N) is 5 bits, all variables are 11 bits, so IK×
This can be realized using two 4-bit ROMs. '2' operations can be performed at the same speed regardless of the complexity of the operation. Also, the speed is high, for example, bipolar R
If you use OM, the access time will be 60 to 7 seconds. In the case of an IC, it is the decoding time of the instruction code, and the number of chips used varies depending on the logic, so the operation speed is determined by the logic with the lowest speed.

'31 Logic can be easily corrected, changed, and added.

Note that programmable logic array P is used instead of ROM.
By using LA (Progamma uses e-gicNray), unnecessary logic can be removed. For example, in the AND example, FFo is “1” as the ROM output.
” is meaningful, so all you have to do is create logic for the AND conditions for the six cases and logic for ○R for those six cases.PLA has a ROM for AND and a RO for OR.
Since it is a combination of M, it can be realized even with two types of ROM. Function: SRAM 24 (Sequence RAM) As mentioned above, the SRAM 24 stores the state of the current value of the counting pulse for counting by a counter, timer, etc., and the selector SEL 26 stores FF when it is a counter and FF when it is a timer. Select CLK of CR17, set it as FF and X, and store it in SRAM at the required timing.

The address to store is memory M7 where the current value is stored.
Match one word. Timer and counter are 1024
If up to 1024 words x 1 bit RAM is used. The contents of the SRAM24 are stored in the SRAM by the state change detection unit CD25 in order to check the rising edge of the next pulse.
- Perform calculations on FF and X, and this becomes DFF.

If DFF is "1", it is the rising edge of a pulse, and therefore a count-up is performed. The hardware of the above-mentioned ``E~'' is the ROM of the three parts of ROM2.
It is controlled by microinstructions created by decoding with 12.

This microinstruction is expressed as follows.・CBUS
→Memory to CR.

・Memory from CBUS to SQR.

・Output from lOADR to CBUS.

・Memory from CBUS to SSTR.

・Output from SSTR to CBUS.

- Select one content of CBUS using MPX and store it in memory using FFI of SSTR.

・MR → Output to CBUS.

- Performs SROM calculations and stores them into 4 bits of SSTR, and also stores counter. For timer, FF, X is SR
Memory to AM.

It is controlled by the above eight types.

Needless to say, at the same time, the normal microinstructions of the arithmetic control unit ACU5 are utilized. This concludes the explanation of the configuration of the present invention, and next, the operation will be explained based on FIGS. 3 and 4.

FIG. 3 shows a sequence drawn with temperature and temperature symbols, which are stored in a memo and executed sequentially as described above (Table 2). In the figure a, the negative AND of device 1 and device 2 is performed, the result is ○Red for device 3, the result is ○Red for the AND result of devices 4 and 5, and the result is ○Red for device 16. Output as shown in Table 3. Expressed in pool algebra, it becomes (1.2) 130 (4.5) → 16.

Figure b is a timer, and when device 6 becomes "1",
After a period of time until the current value in word 11 becomes equal to the set value stored in word 101, device 17 outputs (becomes ``1'').

C in the figure is a counter, and if device 8 is "1", it counts up every time device 7 becomes "1",
Word 13 stores the current value. The set value is stored in word 12, and when the current value reaches the set value, device 18 becomes "1". When device 8 becomes "0", the counter is reset and the current value becomes "0". The output is also "0".This will be explained using FIG. 3a as an example (Table 2) and FIG.

... At address 50, the sequence A is fitted and stored in the arithmetic control unit ACU5, as well as in the sequence register SQR18.

At step 51, the word indicated by the 10 address register lOADRI 9 is sent to the path control unit BCU6.
The state of 0 is leaked. When the device is divided by 16, the quotient is 0 and the remainder is 1, so word 0 is read. (Here, word 0 represents the number of words starting from the 1/0 starting address). Next, the first bit of the extracted state is stored in the FFI through the multiplexer Mx21. At 52, the SROM 23 performs an operation and stores the result in the sequence status register SSTR20.

Addresses 2 to 5 are executed in the same way. At address 6, the sequence OUT16 is fetched at 53 and stored in the arithmetic and control unit ACU5, as well as in the sequence register SQR18.

At 54, like 51, the flesh customer of device 16 is exposed,
Stored in FFI.

At 55, set FSFF and FF using SROM23.
It is determined whether or not to invert the device 16 from I and FFo, and INV etc. are calculated.

At 56, a mask word is created in the mask register MR22 according to mV, and stored in the arithmetic control unit ACU5, EXORed with the word 1 set at 54, and sent to the pass control unit BCU6 at 57. Written to word 1 in spots.

Next, the timer shown in FIG. 3b will be explained.

However, address 7 has the same operation as above.

At address 8, first, PRR at 60. are taken out, and the arithmetic control unit ACU5 and sequence register S
It is stored in QR18. At step 61, the word indicated by the 10 address register lOADR19 is sent to the path control unit BCU6, and the state of 1/0 is revealed.

This is word 10, a preset value, and a general register GR (not shown) of the arithmetic control unit ACU5.
14. FF by SROM23 at 62
.

An operation such as saving the FF to the FF is performed. ■ At address 9, the instruction is first fetched at 65 as in 60, and the current value is set in 66 instead of the preset value as in 61, and stored in the general register GR15 (not shown) of the arithmetic control unit ACU5. do. Next 67
Then, the sequence status register SSTR20 is discussed, inputted into the arithmetic control unit ACU6, and it is determined whether FFo is "1" (that is, whether the timer can be operated), and if it is "1", the current value is incremented at Iso (DFF, If necessary, increment the current value general register GR15 at 69, compare the current value with general register GR14 at 70, and if the current value is greater than or equal to the preset value, increment the current value at 72. is the same as the preset value.

If FFo is "0" after 67, the current value general register GR15 is set to "0" at 75.

And in 71, 74, 76, arithmetic control unit ACU5
FF from to sequence status register SSTR20
Write so that o becomes "1" or "0". FFo “
1" is set only in the case of 74. Then, in 73, FF, is stored in the SRAM 24. N address 1
0 is omitted because it is the same as {row.

The execution status of each sequence has been explained above, but at the time of an interrupt, not only the instruction system is stored as the program status word W, but also the sequence condition code FF1, FSFF is used instead of a condition code such as CVGL. ,FFo,FF,
Use according to the command system. In other words, if an interrupt occurs while a sequence is being executed, the condition code of the sequence is saved as a code W, and when returning from the interrupt,
These are returned to the sequence stator register SSTR20. As described above, in the present invention, (i) a microprogrammable microprocessor is used, sequence execution hardware is added, and this hardware is controlled by microinstructions.

(ii) In the sequence execution hardware, the sequence is executed at high speed using ROM. The side sequence execution hardware is characterized by having a sequence condition code, and by adding the W sequence execution hardware, the sequence can be executed at high speed.

'. }In order to control the sequence execution hardware with microinstructions, we handle numerical values such as timers and counters.
The part executed within the microprocessor and the sequence execution part can be successfully integrated and executed. However, it is possible to create a sequence instruction system that uses less memory and is unrelated to the instruction system of a microprocessor. Both hardware microinstructions for 0 sequence execution and normal microinstructions can be used, allowing high-speed operation.

Arbitrary interruptions during the execution of a physical sequence are allowed. N.R.O.
Since the sequence calculation is performed using M, it is possible to provide a sequence controller that has many remarkable effects, such as high speed and easy addition and modification.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing a general configuration of the present invention, FIG. 2 is a detailed explanatory diagram of sequence execution hardware, FIG. 3 is a sequence example diagram, and FIG. The figure is a sequence execution flowchart. ROM1,2...Read only memory, SW・
...Switch, DEC...Decoder, SEL
...Selector, SRAM... Read/write memory for sequence, SROM... Read only memory for sequence, ACU... Arithmetic control unit, BCU... Path control unit, M...Memory, 1/0...Input/output unit, SQ
R... Sequence Regis Yu, CR.・・・・・・
Control register, lOADR...1/0
Address register, SSTR...Sequence status register, MPX...Multiplexer, M circle...Mask register, CD...
State change detection section. Figure 3 Figure 1 Figure 4 Figure 2 Figure 4

Claims (1)

[Claims] 1. In a sequence controller equipped with a microprogrammable microprocessor, a general-purpose instruction microprogram and a sequence instruction microprogram equipped with a general-purpose instruction word and a sequence instruction word, a switching circuit thereof, and a sequence instruction word execution A sequence controller comprising: a read-only memory for sequence calculations; a register for holding calculation results; and a register for providing conditions to the read-only memory for sequence calculations.