JPS6013196B2 - Gas discharge panel drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a gas discharge panel that reduces power consumption and facilitates integration.

A gas discharge panel placed facing or adjacent to a discharge gas filled space of a plurality of electrodes covered with a dielectric layer prints a sustain pulse at a discharge point formed between the electrodes, and writes a sustain pulse at a selected discharge point. This panel is called an AC type gas discharge panel, and a discharge spot generated by applying an inrush pulse is continuously generated by a sustain pulse.

Various drive circuits for such gas discharge panels have already been proposed, and as the voltage of drive circuits for gas discharge panels has been reduced, integration of drive circuits has been developed. 1st
The figure shows a diagram of a conventional X-side or Y-side drive circuit.

This is a driver DRV in which a plurality of line drivers corresponding to electrodes LII to Lmn on the X side or Y side of a gas discharge panel (not shown) are integrated on one chip.
When I to DRVm are provided and the number of electrodes is 512, for example, m = 32 and n = 16, the address information has a 9-bit configuration, and the upper 5 bits are the shift register SRI.
Furthermore, the lower 4 bits are stored in the shift register SR2 according to the clock cl, and are applied from the shift registers SR1 and SR2 as a parallel information signal to the pulse transformer circuits PTC1 and PTC2 through the AND circuit in response to the strobe signal st. shift register SRI
The output of the shift register SR2 is applied to the decoder DEC via the pulse transformer circuit PTCI, the decoded output becomes the chip select signal csl to csm to select the drivers DRVI to DRVm, and the output of the shift register SR2 is applied to the decoder DEC via the pulse transformer circuit PTC2. Driver DRVI~DRV
m at the same time, and are decoded by decoders in drivers DRVI to DRVm to select electrodes LI I to Lmn.

Further, pulse voltages ASD and SU are applied to the drivers DRVI to DRVm from a pulse generation circuit described later, and during the sustain period, sustain pulses are applied to the electrodes LII to Lmn via the drivers DRVI to DRVm, and during the write or erase period. In this case, the pulse voltage ASD has a waveform including a write pulse or an erase pulse, and the write pulse or erase pulse is applied from the driver to the selected electrode as described above. Driver ORVi (i:1, 2,...
......m) has the configuration shown in Figure 2, and Q
Transistors that constitute the line driver ul~Q skin, Qcl~Qcn, RI~Rn are resistors for base current supply and pulse voltage bypass, DECi is a decoder, and si is "1" in the chip select signal. When the transistor Qcl corresponding to the “1” output of the decoder DECi
Qcn is turned off, transistors Qul to Qun corresponding to the turned off transistors are turned on, and pulse voltage ASO is applied to the electrodes.

3 and 4 show the X-side and Y-side pulse voltage generation circuits, and FIG. 5 is a waveform diagram illustrating its operation.

As shown in FIG. 3, the pulse voltage generation circuit on the × side is composed of transistors QXI to QX6 and a floating power supply FPx of voltage Vax, and pulse voltages ASD-X, S
As shown in FIG. 4, the pulse voltage generating circuit on the Y side outputs U-
It is composed of a floating power supply FPy of y and outputs pulse voltages ASD-Y and SU-Y. To briefly explain the operation of this pulse voltage generating circuit, with reference to FIGS. 3 and 5, during the sustain period, the transistor QX
I is turned on and the pulse of the peak value of Vs rises, then transistors QX2 and QX4 are turned on and Vs
Next, transistors QX3 and QX5 are turned on and the pulse falls, and the pulse voltage ASD is set to the peak value of N.
-X and SU-X have a two-stage waveform of peak values Vs and VM.

During the write period, transistor QXI is turned on and a pulse with the peak value of Vs rises, and then transistors QX2 and QX4 are turned on and transistor Q
X6 is turned on, and then transistors QX3 and QX5 are turned on. Therefore, the pulse voltage ASD-× is the peak value Vs
It becomes a two-stage waveform with (VM+Vax), and the pulse voltage SU
-X has a two-stage waveform of peak values Vs and VM. In the erase period, transistors QX6 and QX5 are turned on, and then transistor QX3 is turned on, so that only the pulse voltage ASD1x has a narrow waveform with a peak value Vax. Also, to explain with reference to FIGS. 4 and 5, during the sustain period, transistor QYI is turned on and the pulse of the peak value of Vs rises, and then transistor QY3 is turned on and the pulse falls. Therefore, the pulse fin pressure AS
DY and SU-Y have waveforms with a peak value Vs.

Also, during the write period, transistors QY3 and QY4 are turned on, then transistor QY2 is turned on,
Pulse voltage ASD-Y is zero, pulse voltage SU-Y is Va
This is the waveform of the peak value of y. In the erasing period, the transistor QY2 is turned on a short time after the transistors QY3 and QY4 are turned on, and only the pulse voltage SU-Y has a waveform with a peak value of one Vay. During the sustain period, since the chip select signal csi is "0", the transistors Qcl to Qc of the driver DRVi
n is turned on, transistors Qul to Qun are turned off, and pulse voltage SU (SU-X, SU-Y) is applied to all electrodes Lil to Lin via diodes. Also, during the write period, in the X-side driver selected by the chip select signal csi and the output of the decoder DECi, the selected transistors Qcl to Qcn are turned off, and the corresponding transistors Qul to Qcn are turned off. Qun is turned on, and in unselected X-side drivers, all transistors Qcl to Qcn are turned on and transistors Qul to Q are turned off. The Y-side driver is configured such that transistors Qcl to Qcn selected by the output of the decoder DECi are turned on. Therefore, X
A pulse voltage ASD-X is applied to the selected electrode on the side, and a pulse voltage ASD-X is applied to the selected electrode on the side.
A pulse voltage SU-Y is applied to the selected electrodes on the side through diodes, and the waveform indicated by VA in Fig. 5 is applied to the selected discharge point, and the waveform shown by VB in Fig. 5 is applied to the non-selected discharge point. The waveforms shown are respectively applied, and VM+Vax+Vay=
A write pulse of Vw is applied to the selected discharge point to perform writing. Also, in the erase period, the same operation as in the write period is performed, and an erase pulse is applied to Vax+Vay according to the selective discharge rule to perform erasing. In the write operation described above, in the X side driver, transistors other than the transistors Qcl to Qcn corresponding to the selection electrodes are turned on, and the voltage of (ASD-X)-(SU-X)=Vax becomes the voltage of the resistors RI to Rn. current flows through the transistor that is turned on.

For example, when one electrode is selected out of 51Z electrodes, and assuming that the current flowing through the resistor R (RI to Rn) is 1, a power loss of 511·P·R=W will occur.
In order to reduce this power loss W by 4.
) increases, the base current of the transistors Qul to Q will not be sufficiently supplied, resulting in a decrease in their operating speed. The present invention has been made to improve the above-mentioned drawbacks, and its purpose is to significantly reduce the power loss due to the resistance of the above-mentioned driver from the viewpoint of the overall configuration.

Examples will now be described in detail. FIG. 6 shows a driver according to an embodiment of the present invention, and the same reference numerals as in FIG. 2 indicate the same parts. In this embodiment, photodiodes DPI to DPn as light-receiving elements are connected in series with resistors RI to Rn, respectively, and a light-emitting diode LEDi as a light-emitting element is driven by a transistor Qsi operated with si in response to a chip select signal. is the driving voltage of the light emitting diode LEDi. This light emitting diode LE
Di and the photodiodes DPI to DPn are optically coupled to form a photocoupler, and the photodiodes DPI to DPn are arranged around the light emitting diode LEDi, or an optical fiber is provided between them. Optical coupling means can be employed. Figure 7 is the 6th
2 is a block diagram of main parts of the driver DRVj shown in the figure, in which the same reference numerals as in FIG. 1 indicate the same parts. FIG.

As shown in FIG. 6, each of the drivers DPVI to DRVm' is equipped with a light emitting diode LEDi that is turned on by chip select signals csl to csm', and the output of the decoder DEC and the strobe signal st are connected. Chip select signals csl to csm are formed under the AND condition. The reason why the pulse transformer circuit PTCI in FIG. 1 is not provided is that the output of the decoder DEC is applied to the photocoupler, so electrical isolation between the logic circuit and the relatively high voltage driver is achieved. This is because it is achieved with a photocoupler. Also, pulse transistor circuit PT
Instead of not providing C2, the output of shift register SR2 is sent to the decoder D of each driver via a bell conversion circuit LC.
Added to FCj. In the above-mentioned configuration, if we consider the case where only one of the 512 electrodes on the x side (for example, electrode Li2 in FIG. 6) is selected, the selected driver DRvi is determined by the chip select signal csi'. The light emitting diode LEDi emits light, the corresponding photodiodes DPI to DPn are turned on, and the driver D
As mentioned above, the current due to Vax flows through the 16 resistors RI to Rn of RVi, but when the selected electrode (sixth
The resistor (R2) corresponding to the electrode Lj2) in the figure is the decoder DE
Since the transistor (Qc2) is turned off by the output of Ci, the current does not flow, and therefore, in reality, the resistor (R1) corresponding to the 15 non-selected electrodes (Lil, Li3 to Lin)
, R3 to Rn).

Note that since the photocouplers of unselected drivers are not driven by the chip select signal, the current is not supplied to the resistor of each driver at all. Therefore, according to the configuration of the present invention, power loss is reduced by 15/511 compared to the conventional example. Note that since the pulse voltages ASD and SU have the same waveform during the sustain period, no problem occurs even if the photodiodes DPI to DPn are in the on state.
In the above embodiment, photodiodes DPI to D corresponding to electrodes Lil to Ljn are provided for one light emitting diode LEDi.
In the case of combining Pn, the light emitting diode LEDi
A plurality of light emitting diodes and photodiodes are provided and driven in parallel or in series to form a 1:k (k=1, 2, 3...
) can also be combined.

FIG. 8 shows a driver DRVi according to another embodiment of the present invention, in which the same reference numerals as in FIG. 6 indicate the same parts, and the LED c
1 to LE and DPcl to DPcn are light emitting diodes and photodiodes constituting a photocoupler, and perform operations corresponding to transistors Qcl to Qcn in FIG.

Further, RD and RLI to RLn are resistors connected in series with the light emitting diodes, respectively. Information signal decoder DEC
A light emitting diode, for example, an electrode Li2, is connected to the output line that is decoded by i and the decode output becomes "1".
When selecting , current does not flow only to the light emitting diode LEDc2, and the other light emitting diodes LEDcl, LE ratio 3 to LE
Dcn has resistors RL1, RL3 to RL depending on the fin pressure Vcc.
A current flows through the photodiodes DPcl, DP
When c3 to DPcn are turned on and si becomes "1" in the chip select signal, a current flows through the light emitting diode LEDi through the resistor ○, and the photodiode DPI to
DPn is turned on. Therefore, the pulse voltage ASD is applied only to the electrode Li2 via the transistor Qu2,
For the other electrodes Lil, Li3 to Lin, the pulse voltage ADS is applied to the photodiodes DP1, DP3 to DPn, the resistors R1, R3 to Rn, and the photodiodes DPcl, DPc.
3 to DPcn. That is, the pulse voltage ASD corresponding to the write or erase operation is applied only to the selected electrode Li2. FIG. 9 shows an embodiment in which photodiodes DPcl to DPcn constituting a photocoupler are connected to the bases of transistors Qcl to Qcn. The same reference numerals as in FIG. 8 indicate the same parts, and Rc
1 to Rcn are resistances.

The output logic level of the decoder DECi is opposite to that shown in FIG. 8 and is opposite to the embodiment shown in FIG. 8. For example, when electrode Li2 is selected, current flows only to the light emitting diode LE ratio 2, thereby turning on the photodiode DPc2. The transistor Qc2 is in an off state and the transistor Qu2 is in an on state. FIG. 10 shows that the photodiodes DPcl to DPcn in FIG.
It is connected between the line to which D is applied and the bases of the transistors Qcl to Qcn, and the output logic level of the decoder DECi is similar to that shown in FIG.

In other words, no current flows through the light-emitting diodes LEDcl-LEDcn of the photocoupler corresponding to the selected electrodes Lil-Lin, current flows through the other light-emitting diodes and they emit light, and the photodiode DPcl corresponding to the light-emitting diode
~DPcn turns on and transistors QI~Qc
On and off of n are controlled, transistors Qcl to Qcn corresponding to the selected electrode are turned off, and transistors Qul to Qcn are turned off.
Q Blood turns on. FIG. 11 shows a main part of the X side or Y side when the driver DRVi of the embodiment shown in FIGS. 8, 9 and 10 is used.

This is a diagram showing the same reference numerals as in FIG. 7 indicating the same parts. In this embodiment, the level conversion circuit LC in FIG. 7 is omitted, and the output of the decoder DECi for driving the line driver is optically connected between the pulse voltage side and the logic level side by a photocoupler. By being coupled symmetrically, there is no need for a pulse transformer circuit or a level conversion circuit. Also, chip select signal cs
This is the same as the embodiment shown in FIG. 7 in that the drivers DRVI to DRVm are selected and operated by l to csm. FIG. 12 shows an embodiment in which the driver DRVi does not have a built-in decoder, and the electrodes Lil to L
The data DAT that selects in is transmitted through transistors Q1i to Q
1n to the base of these transistors Q1i
~Q1n controls the light emitting diodes LEDcl~LEDcn that constitute the photocoupler.

For example, when selecting electrode Li2, transistor QI1
, Q13 to Q1n are turned on and only the transistor Q12 is turned off.
When si is applied to the base of transistor QSi, only transistor Qu2 is turned on, so the pulse voltage AS
D is applied to the electrode Li2. Note that the same reference numerals as those shown in FIG. 10 indicate the same parts. In this embodiment, if n=10m=32, the address information will be 21 bits consisting of 5 bits for forming the chip select signal csi and 16 bits for electrode selection, and All electrodes Lil
~Lin can be selected at the same time to apply the pulse voltage ASD.

In each of the above-mentioned embodiments, it is of course possible to use photodiodes DPI to DPn, DPcl to DPcn constituting the photocouplers using light receiving elements such as phototransistors, or the photocouplers can be mounted on the chip of the driver DRVi which is an integrated circuit. It is also possible to form

As described above, in the present invention, a plurality of line drivers corresponding to electrodes are grouped together to form drivers DRVI to DRVm, and a pulse voltage ASD corresponding to a sustain period, write period, erase period, etc. is generated from a pulse voltage generation circuit. , SU are applied to the drivers DRVI to DRVm, and the pulse voltage applied to the selected electrode, such as a write pulse or an erase pulse, is applied by controlling the transistors Q cores 1 to Q, and the pulse voltage at that time is applied to the selected electrode. Transistors Qcl to Qcn or photodiodes D are connected to the electrodes via resistors RI to Rn.
It is omitted through elements such as Pcl to DPcn, and resistors RI to
Photodiode DPI~D of photocoupler in series with Rn
By connecting a light receiving element such as Pn, the chip select signal cs
Photocoupler light emitting diode LED emitted by i
Only in drivers compatible with light emitting elements, such as i, bypassing of pulse voltages to non-selected electrodes is performed by resistors RI to Rn;
Since I to DPn are in the off state, the resistances RI to R
The power loss caused by n can be reduced to zero.

Therefore, the overall power loss is significantly reduced, resulting in an economical configuration.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of the drive circuit for the X or Y side of a conventional gas discharge panel, Figure 2 is an explanatory diagram of a conventional driver, and Figures 3 and 4 are for the × side of the gas discharge panel. and the pulse voltage generation circuit on the Y side, FIG. 5 is an explanatory diagram of the pulse voltage,
FIG. 6 is an explanatory diagram of a driver according to an embodiment of the present invention, FIG. 7 is a block diagram of an embodiment of the present invention using the driver shown in FIG. 6, and FIGS. 8, 9, and 10. are explanatory diagrams of drivers of different embodiments of the present invention, and FIG.
FIG. 12 is a block diagram of an embodiment of the present invention using the driver shown in FIGS. DRVI~DRVm are drivers, LII~Lmn are electrodes, DEC, DECi are decoders, SR1, SR2 are shift registers, LEDi, LEDcl~LEDcn are light emitting diodes, DPI~DPn, DPcl~DPcn are photodiodes, Qul~ Q plate, Qcl~Qcn, QSi
are transistors, RI to Rn' are resistors, ASD and SU are pulse voltages, and csl to csm are chip select signals. Figure 1. Figure 2 Figure 3 L Figure 4 Figure 5 Figure 7 Figure 6 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] 1 A pulse voltage corresponding to a sustain period, a write period, an erase period, etc. is applied from a pulse voltage generation circuit to a driver configured by combining a plurality of line drivers corresponding to electrodes of a gas discharge panel, and the line driver ,
a transistor for applying the pulse voltage to a selected electrode; a resistor connected to the base of the transistor; and a transistor for bypassing the pulse voltage through the resistor so that the pulse voltage is not applied to non-selected electrodes. In a drive circuit for a gas discharge panel, each driver is provided with a photocoupler consisting of a light emitting element that emits light in response to a chip select signal, a light receiving element that receives light from the light emitting element, and A drive circuit for a gas discharge panel, characterized in that a light receiving element is connected in series with the resistor.