JPS60130989A - High resolution television receiver - Google Patents

Abstract

PURPOSE:To obtain a picture with high resolution by forming an interpolation signal for non-interlace from a video signal of the interlace system and conducting non-interlace display from the interpolation signal and the present video signal to detect surely the movement of pattern. CONSTITUTION:A video signal S0 subject to video image detection at a terminal 7 is fed to the 1st delay circuit 8 having a delay time of one field and the 1st delay video signal S1 is formed. This is fed to an average value interpolation circuit 13 to form an interpolation signal SBl from two adjacent line video signal in one field. The interpolation signal and the 1st delay video signal are fed to a subtractor 11 and also the 1st delay video signal is fed to the 2nd delay circuit 16, where the 2nd delay video signal S2 having the delay time of one field is formed. A frame difference signal SX is formed at a subtractor 17 by the signals S2 and S0. A forming circuit 20 detects the movement between frames based on the frame difference signal. These signals are fed to a picture tube via a time axis compressor 2 and an amplifier 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a high-resolution television in which a non-interlace interpolated signal is formed from an interlaced video signal and non-interlaced display is performed from this interpolated signal and the current video signal. Regarding John's receiver.

BACKGROUND ART AND PROBLEMS Non-interlaced television receivers have been proposed as a means of obtaining single-resolution images (high-quality images) from current interlaced video signals.

In order to realize the non-interlace method, the problem is how to generate a video signal (interpolation signal) in the other field scanned within the same field. To date, the following three interpolation signal forming methods have been proposed.

(2) A method of using the sum signal of two adjacent lines in the same field as an interpolation signal.

⑶ When using the sum signal of two adjacent lines in the other field as an interpolation signal, use this method depending on the frequency component.

A method of using the interpolation signals of ■ and ■ and the corresponding signals of the other field depending on the movement of the screen.

Among these interpolation signal forming means, the method (2) inserts a signal with poor vertical resolution for every other line and interpolates it, resulting in a signal with lower resolution as a whole, so it is difficult to expect a high-resolution image. I can't.

With the method (2), a double image may be output depending on the frequency component of the signal, so there is a risk that the resolution may deteriorate depending on the picture.

The method (2) can be used as long as it can detect screen movement with high accuracy, but in the case of a signal with low contrast or a signal with a high S/N ratio, screen movement cannot be detected reliably, so the resolution may deteriorate. Alternatively, there is a drawback that double images may occur.

This invention proposes a high-resolution television receiver that improves the drawbacks of the method (2).

The purpose of the invention is to solve the problem of low-contrast signals and S
Even if a bad /N signal is input, the system reliably detects the movement of the screen and prevents the resolution from degrading or from generating a 2M image, ensuring that a high-resolution image is always obtained. be.

SUMMARY OF THE INVENTION Therefore, in the present invention, a video signal subjected to video detection is supplied to a first delay circuit whose delay time is one field to form a first delayed video signal. is supplied to the average value interpolation circuit to form an interpolation signal from the video signals of two adjacent lines, and this interpolation signal and the first delayed video signal are supplied to the subtraction circuit to form a subtraction signal, and the above-mentioned The first delayed video signal is
The second signal is supplied to the delay circuit of and is delayed by one field.
A delayed video signal is formed, a frame difference signal is formed from this and the current video signal, a motion between frames is detected from this frame difference signal, and a signal obtained by multiplying this motion detection signal by the subtraction signal and the above average is calculated. A summation signal with the value interpolation signal is formed.

This added signal is used as a composite interpolation signal and a signal for 1ζ non-interlacing.

EXAMPLE Next, an example of the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

In FIG. 1, (101 is an example of a non-interlace interpolation signal forming circuit according to the present invention, this time @QO), the current video signal So and interpolation signal SZ in the field output from the time axis compressor (2), the respective time axes are compressed into A, and are sequentially and alternately taken out. The time-base compressed current video signal So and interpolation signal SZ are supplied to a picture tube (4) via a video amplifier (3). A vertical deflection signal PV with a vertical frequency fv is supplied to a deflection coil (5) provided in a picture tube (4), and 2
A horizontal deflection signal pl having a double horizontal frequency of 2fH is supplied to perform horizontal and vertical deflection for non-interlacing.

The non-interlace interpolation signal forming circuit aω is configured as follows.

The terminal (7) is supplied with the current video signal So in the field that has been detected. The current video signal So is supplied to a first delay circuit (8) having a delay time of 1 field to form a first delayed video signal S1, which is then supplied to a first delay circuit (8) having a delay time of l fields to form a first delayed video signal S1. subtracter (1
1).

The current video signal So is further supplied to an average value interpolation circuit (13), and an interpolation signal (first interpolation signal) Ss'i in the current field is formed from the video signals of two adjacent lines in the same field. This average value interpolation circuit (13)
As is well known, it is composed of a delay element having a delay time of one line, a combiner, and a level attenuator that lowers the level to two. The first interpolation signal 5Bjl is supplied to a subtracter (11) to form a subtracted output Sv (-31SBJI), which is supplied to a multiplier (15). Delay circuit (9
) is for compensating for the delay time caused by the average value interpolation circuit (13).

On the other hand, the first delayed video signal S1 is further supplied to a second delay circuit (16) having a delay time of one field, and a second delayed video signal 32 (frame delayed video signal) is supplied. This second delayed video signal S2 and the current video signal S
o is fed to the subtracter (17) to produce a frame difference signal S
x (=So −32) is formed.

The frame difference signal SX and the above-mentioned subtraction signal sY are supplied to a circuit (20) for forming a multiplication signal sM, which is a second interpolation signal. The forming circuit (20) is for detecting motion between frames based on the frame difference signal SX, and in this example is composed of a nonlinear circuit (21) and the above-mentioned multiplier (15). First, the nonlinear circuit (23) is for forming a nonlinear output sK according to the movement of the image, and this nonlinear output sK is used to determine the coefficients of the subtraction signal SY.

Basically, the subtraction signal SY is the second interpolation signal sM.
becomes. Its input/output characteristics are designed to be first-order characteristics as shown by the straight line l in FIG.

That is, when the human power level of the frame difference signal SX is above or below the predetermined level SX0, 5K=o, and when the human power level is zero, 5K=o.
When K=1 and the level is between, it is a straight line! Appropriate primary characteristics are given as shown below.

Since the frame difference signal SX has a level corresponding to the movement on the same line between one frame, if SXO is selected as the lowest detection level for a moving image, the value of the second interpolation signal sM can be adjusted according to the movement of the image. are obtained differently.

Therefore, in the adder (23), the first interpolation signal 5RJ
If a composite of I and the second interpolation signal sM is used as a composite interpolation signal Sz, an interpolation signal SZ corresponding to a moving image, a still image, or a motion in between can be obtained.

That is, the subtraction output SY, the nonlinear output sK, and the composite interpolation signal SZ are expressed as follows: 5y-3z SR (11 SK -k (So 32 )) = +21 is the slope of the straight line i.

SM=SK'5Y -3K (Sl 5sQ) ... (3) S Z =
S K-3y + 3 BB (4), so if the current image is a moving image with fast movement and sKξ1sxol, S becomes -0 and Sz = Ssn
”(51) is used as the composite interpolation signal SZ.

In this way, when the motion information in the preceding and following frames is large, the first
The interpolation signal sex is used as the interpolation signal Sz for interlacing. This is because if a signal formed from a video signal one field before is used as an interpolation signal when there is a large movement, the resolution may deteriorate significantly.

Also, in the case of a still image, since 5K=1, S z
= S y + S RJ2 = St -3ag+5Bi - St (6) is used as the composite interpolation signal Sz.

In this way, when there is no movement between frames, it can be assumed that there is almost no movement in the image in the preceding and following fields, so this is determined to be a still image, and in this case, the interpolated signal S1 based on the video signal of 1 field before is used to form a non-interlaced image.

Next, when the frame difference signal SX is slightly larger than the above case, that is, when it is difficult to distinguish between a moving image and a still image, since Q<Sx<Sxo, in this case, SK = k (So 32) = ni' ... (7) Sz = ni' (St-3B) +5BJI-- ni'5l-
3B laziness (1-ni') ...(8) (second
(see figure), in the case of such an image, an appropriate mix of the first and second interpolation signals sx and SY is used as the interpolation signal SZ.

In the configuration shown in Figure 1, the movement of the image is detected using the frame difference signal SX, so the movement detection accuracy is high, and even when it is difficult to distinguish between a moving image and a still image, an appropriately mixed image can be interpolated. Since it can be used as the signal Sz, interpolation will not result in unnatural movement.

Incidentally, as shown in FIG. 3, a subtracted output sY of the first delayed video signal S1 and the first interpolation signal saR is formed, and this is supplied to the nonlinear circuit (25) with sine wave characteristics as shown in the figure. When the signal sY' (=αsY, α indicates a quadratic characteristic) obtained by The signals have different vertical resolutions.

For this reason, in the case of a fine pattern, it is determined that there is "existence" even if there is no movement in the image, and in this case, the first interpolation signal s is output as the composite interpolation signal Sz.

On the other hand, when controlling the coefficient of the subtraction signal sY, which is the second interpolation signal, based on the frame difference signal S× as shown in FIG.
When the image is 1, the value becomes 1, and the first delayed video signal Sl
is output as a composite interpolation signal Sz. Therefore, erroneous interpolation processing as shown in FIG. 3 is not performed, and detection accuracy is improved.

Now, in the embodiment shown in FIG. 1, the motion of the image is detected based on the magnitude of the frame difference signal Sx, but this frame difference signal SX contains not only the original motion information but also the information contained in the video signal. Also includes noise. Therefore, in the case of a low-level signal that can be considered as a stationary signal, it contains more noise components than the original motion information, and therefore, the magnitude of the frame difference signal SX as it is can change the image. If motion is determined, there is a risk of incorrect motion detection.

Figure 4 shows an example in which motion detection can be performed reliably even in such cases. In this example, orthogonal transformation such as Hadamard transform is used to detect motion information buried in noise. be.

That is, as shown in FIG.
32). (33) is an inverse conversion processing circuit.

FIG. 5 shows a specific example.

Note that the video signal used is a digital video signal obtained by subjecting an analog video signal to PCM modulation in order to facilitate delay and arithmetic processing. Therefore, the color subcarrier frequency rs is input to the input terminal (7) shown in FIG.
A video signal that is sampled at a frequency three or four times as high as a, quantized, and coded to form a digital signal is sequentially supplied in the form of a serial code. Therefore, the subtraction signal S Y + frame difference signal SX are both serial code digital signals.

The subtracted signal S Y r The frame difference signal Sx is supplied to the serial/parallel converter circuits (31^) and (32A), respectively, and as will be described later, the line at the output and the next line are separated by two sampling clocks. 411M picture element points (
Parallel signals regarding the sampling points) appear. These parallel signals are supplied to the orthogonal transform circuits (31B) (32B), and as described later, the pattern of the frame difference image in the area of these four picture element points is determined, and the four levels determined according to the pattern are determined. An output signal is generated, and the orthogonal transform circuit (
These four output signals obtained in step 31B) are supplied to the aforementioned nonlinear circuit (21) ((21^) to (210)). The output is 4 obtained by the other orthogonal transform circuit (32B).
output signal and multiplier (15) ((15^) ~ (150
)), and the output sM8-5tlD is supplied to the parallel-to-serial conversion circuit (34) via the inverse conversion circuit (33), and the output is used as the interpolation signal sM of Shin2.

Figure 6 shows the serial-parallel conversion circuit (31^) and the orthogonal conversion f[
The configuration of an example of 7 circuits (31B>) is shown.

A delay circuit (41) in which the frame difference signal Sx supplied from the input terminal in the form of a serial code is 1H, and a delay circuit (42) in which the frame difference signal Sx is 1H and two sampling clocks are 2τ.

(43) is converted into frame difference data at a total of four pixel points, two pixel points separated by two sampling clocks 2τ of each of two adjacent lines of successive frames. As shown in FIG. 6A, if two adjacent pixel points on the nth line are al+82 and two adjacent pixel points on the next n+1st line are a3+a4, the input terminal (40) is When frame difference data X&4 at pixel point a4 is supplied, data X113 appears at the output of the delay circuit (42) as shown in FIG. 6, data X&2 appears at the output of the 1H delay circuit (41), and the delay occurs. Data Xat appears at the output of the circuit (43).

These frame difference data xai to X&4 are supplied to the orthogonal transform circuit (31B). This orthogonal transformation circuit (31B
) is an arithmetic circuit configured to generate the following conversion outputs x1 to x4 at its output terminals (35a) to (35d), respectively.

The level corresponds to the frame difference video pattern of the (2 x 2) area formed by the picture element points a1 to a4. 7th
For example, add +1 to the shaded area of °ζ in each of Figures B to E.
If the other areas are set to -1, the converted outputs X1 to X4 will be as shown below.

(Figure 7B: Pattern where the entire area is +1) Xz = X4
, X2 =X3 =X4 =0 (Figure 7C: pattern where +1 is vertical)X2 =4. X1=X3=X4=0
(Figure 7C: +1 horizontal pattern) X3 = 4,'
X1 = X2 = X4 = 0 (Figure 7C: +1 is a diagonal pattern) For example, the level-related conversion output X1 according to the frame difference video pattern of the area represented by four pieces of data
~X4 can be formed.

Here, assuming that random dot-shaped noise components exist, such noise has components in all directions, so the levels of each of the output signals X1 to X4 are set to a sufficiently low level. Contains noise.

On the other hand, since the original motion information pattern is a specific pattern, it will appear more often in one of the output signals X l''
The level difference between the motion information contained in the X and the noise becomes clear.

Since the S/N is inherently poor when there is little motion information, it is difficult to detect the motion component of the original image from this motion information if the motion information is simply detected from the frame difference signal. However, by performing orthogonal transformation processing, the S/N
Even if the movement information is bad, the movement information is IF! Since this is perceived as a change in the 1iji pattern, noise is suppressed and the original motion information can be reliably detected.

Therefore, the detection accuracy of motion information included in the frame difference signal SX increases.

The output signals X1 to X4 are respectively supplied to nonlinear circuits (21) ((218) to (210)) having the above-mentioned human output characteristics, and i! ! Nonlinear output N1 corresponding to the movement of the iI image
N4 is formed.

Similarly, the subtraction signal SY is converted to 4 by the serial/parallel conversion circuit (32^).
These are converted into parallel data Vat~Y2L4, which are subjected to orthogonal transformation processing similar to that described above in the orthogonal transformation circuit (32B) to form four parallel data Y1~Y4 with noise dispersed and suppressed. , these four parallel data Y1
~Y4 is a multiplier (15) with nonlinear outputs N1 to N4
((158) to (150)) and nonlinear output N
After the parallel data Y1 to Y4' are weighted by 1 to N4, the respective multiplication outputs sN^ to SMD are supplied to an inverse conversion circuit (33) as shown in FIG.

This inverse transformation circuit (33) has a configuration in which the flow of signals from the input to the output of the orthogonal transformation circuit (31B) is reversed, as shown in the sixth part, and its input terminals (33a) to (33d)
When the H) calculation power sM^~SMD corresponding to each pattern is supplied to the output, outputs 43M, ~45 having a level four times the multiplication output at each of the pixel points a1 to a4 are supplied.
M4 appears.

The output of this inverse conversion circuit IIpI (33) is transmitted to a 1H delay circuit (52) and a delay circuit (53) with a delay amount of 2 sample periods.
).

(54) and three adders (55) to (57), the parallel-to-serial conversion circuit (34) restores the normal order and further attenuates six levels! (58) to the output terminal (59) in the original order.
The interpolated signals sM appear sequentially.

The pattern classification area is not limited to (2×2) but also (2×4)
The process may be performed for a larger area than the above.

In this way, by performing orthogonal transformation processing, motion information is converted into an image pattern and processed, so low-level image information contained in the frame difference signal Sx can be detected, and nonlinearity with respect to motion information can be detected. The accuracy of outputs N1 to N4 becomes higher. Therefore, even with low-level images,
If this is assumed to be indistinguishable between a still image and a moving image, the probability that the nonlinear outputs Ns to N4 will be output becomes extremely low. The detection accuracy is improved to the order of orthogonal transformation.

In the embodiment shown in FIG. 4, an orthogonal transform technique such as Hadamard transform is used to improve the precision of motion detection, but it is also possible to use a combination of complementary low-pass filters and bypass filters.

As described in detail, according to the present invention, even when a signal with low contrast or a signal with poor S/N is input, movement of the screen can be detected reliably, so that it is possible to detect the movement of the screen without degrading the resolution.
Double images do not occur, and high-resolution images are always obtained. In particular, if orthogonal transformation processing is performed, motion information can be accurately detected even with a frame difference signal with a poor S/N ratio, so the results are even more remarkable.

[Brief explanation of drawings]

1 and 4 are system diagrams of essential parts showing an example of a high-resolution television receiver according to the present invention, FIG. 2 is a characteristic diagram of a nonlinear circuit, and FIG.
5 and 6 are system diagrams showing an example of an orthogonal conversion circuit and a serial-parallel conversion circuit, respectively, FIG. 7 is a diagram for explaining the operation, and FIG. FIG. 2 is a system diagram showing an example of a parallel-serial conversion circuit. Ql is a non-interlace interpolation signal forming circuit (4
) is a picture tube, (2) is a switching circuit, (13) is an average value interpolation circuit, (20) is a signal processing circuit, (31^). (32^) is a serial-parallel conversion circuit, (31B), (32
B) is orthogonal transform circuit, (33) is inverse transform circuit, (34)
is a parallel-to-serial conversion circuit, and (81, (16) is a delay circuit. Procedural amendment (Mr. Chief Adjudicator, Japan Patent Office) 1.45 items displayed Patent Application No. 239412, 1982, Title of Invention High Resolution Television receiver 1 Zoki 3, relationship with the case of the person making the amendment Patent applicant address 6-7-35, Kitashinyo, Tokyo Parts Store Name (21
8) Norio Ohga, representative director of Sony Corporation 5, date of amendment order 1935, month, day 6, number of inventions increased due to sleeve correction Claims: The video signal detected by video detection has a delay time of one field. The current video signal is supplied to one delay circuit to form a first delayed video signal, and the current video signal is supplied to an average value interpolation circuit to form an interpolated signal from the video signals of two adjacent lines. and the first delayed video signal are supplied to a subtraction circuit to form a subtraction signal, and the first delayed video signal is supplied to a second delay circuit to form a subtraction signal delayed by one field. A delayed video signal of 2 is formed, a frame difference signal is formed from this and the current video signal, and a motion between frames is detected from this frame difference signal,
A signal obtained by multiplying this motion detection signal by the above-mentioned subtraction signal and an addition signal by the above-mentioned average value interpolation signal is used as a composite interpolation signal, and this composite interpolation is used as a single word non-interlace signal. television receiver.

Claims (1)

[Claims] The detected video signal is supplied to a first delay circuit whose delay time is one field to form a first delayed video signal, and this first delayed video signal is supplied to an average value interpolation circuit. An interpolated signal is formed from the video signals of two adjacent lines, and this interpolated signal and the first delayed video signal are supplied to a subtraction circuit to form a subtracted signal, and the first delayed video signal is 2 delay circuits and 1
A second delayed video signal delayed by a field is formed, a frame difference signal is formed from this and the current video signal, a motion between frames is detected from this frame difference signal, and this motion detection signal and the above subtraction signal are A high-resolution television receiver in which a signal obtained by adding the above-mentioned average value interpolated signal and a multiplied signal is used as a composite interpolated signal, and this composite interpolated signal is used as a non-interlace signal.