JPS60130165A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60130165A
JPS60130165A JP23862683A JP23862683A JPS60130165A JP S60130165 A JPS60130165 A JP S60130165A JP 23862683 A JP23862683 A JP 23862683A JP 23862683 A JP23862683 A JP 23862683A JP S60130165 A JPS60130165 A JP S60130165A
Authority
JP
Japan
Prior art keywords
film
electrode
layer
connection electrode
entire surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23862683A
Other languages
Japanese (ja)
Inventor
Minoru Inoue
実 井上
Haruyoshi Yagi
八木 春良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23862683A priority Critical patent/JPS60130165A/en
Publication of JPS60130165A publication Critical patent/JPS60130165A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

Abstract

PURPOSE:To obtain a connection electrode of high reliability by a method wherein, in mounting a connection electrode to a diffused region provided in a semiconductor substrate, an insulation film is adhered over the entire surface, and a window part is bored by corresponding to the diffused region, where a laminated body of a Pt silicide layer and an Mo film is buried, and an Al wiring layer is adhered over the entire surface including it. CONSTITUTION:An N type region 2 is diffusion-formed in the surface layer part of the P type Si substrate 1, and the following process is taken in mounting the connection electrode to a part of the surface of the region. In other words, a PSG film 3 is adhered over the entire surface including the region 2, and the window part is bored by corresponding to the position of connection electrode mounting, where the connection electrode made of a Pt silicide layer 11 in the lower layer, and an Mo film 12 in the upper layer is buried by making its surface almost even with the film 3. Thereafter, an Al electrode 15 abutting against this electrode is adhered over the entire surface. Or, a Ti nitride film can be adhered on the film 12. Either case produces an electrode generating no contact failure for a long time by decreasing the contact resistance.

Description

【発明の詳細な説明】 +a+ 発明の技術分野 本発明は半導体装置にかかり、そのうち特に半導体基板
(基体)との接続電極の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION +a+ Technical Field of the Invention The present invention relates to a semiconductor device, and particularly relates to the structure of an electrode connected to a semiconductor substrate (substrate).

(I))従来技術と問題点 周知のように半導体集積回路(IC)などの半導体装置
においては、半導体基板上に半導体素子や抵抗等が形成
されて、これらのものから導出する配線層が上面に多数
設けられている。
(I)) Prior Art and Problems As is well known, in semiconductor devices such as semiconductor integrated circuits (ICs), semiconductor elements, resistors, etc. are formed on a semiconductor substrate, and wiring layers derived from these elements are formed on the top surface. There are many.

その配線層には、従前からアルミニウム(AI)膜また
はアルミニウムシリコン合金(Al/Si : Si含
有量1〜2%)膜が用いられており、これはアルミニウ
ムが安価に(Mられる高電導祠料であって、絶縁膜との
接着力が強く、しがもパターンニングが容易な材料であ
るからである。
Aluminum (AI) films or aluminum-silicon alloy (Al/Si: Si content 1 to 2%) films have been used for the wiring layer, and aluminum is inexpensive (M is a highly conductive abrasive material). This is because the material has strong adhesion to the insulating film and is easily patterned.

しかしながら、ICがLSI、VLSIと高築積化され
微細化されてくると、電極窓が小さくなり、電極窓開口
部の側面の段差が急峻になって、電極配線の安定な接続
が困ゲ「になってきた。第1図はそれを説明するための
電極部分の断面図を示し、1はp型シリコン基板、2ば
n型シリコン領域、3は燐珪酸ガラス(P S G)膜
からなる絶縁膜、4は電極窓、5はアルミニウム配線で
ある。
However, as ICs become more highly integrated and miniaturized, such as LSI and VLSI, the electrode windows become smaller and the steps on the sides of the electrode window openings become steeper, making it difficult to make stable connections for electrode wiring. Figure 1 shows a cross-sectional view of the electrode part to explain this, in which 1 is a p-type silicon substrate, 2 is an n-type silicon region, and 3 is a phosphosilicate glass (PSG) film. An insulating film, 4 an electrode window, and 5 aluminum wiring.

図示のように、アルミニウム配線5は電極窓の層部分S
でのくびれがひどく、この部分で断線し易くなる。これ
はスパッタ法の被覆性(カハーレイジ)が良くないこと
にも起因しており、アルミニウム膜は主にスパッタ法で
被着され、化学気相成長(CVD)法での被着が困難な
ためでもある。
As shown in the figure, the aluminum wiring 5 is connected to the layer portion S of the electrode window.
The constriction is severe and the wire is likely to break at this part. This is also due to the poor coverage of sputtering, and aluminum films are mainly deposited by sputtering, and it is difficult to deposit by chemical vapor deposition (CVD). be.

また、第1図のようにシリコン基板に直接、アルミニウ
ムシリコン合金膜を接触させると、ウェハープロセス中
の熱処理によって前記の膜中のシリコン(Si>がアル
ミニウム中を拡散′して、接触面にシリコン層がエピタ
キシャル成長し、異質のシリコン層となって接触抵抗が
大きくなり、コンには、アルミニウムを含むp型エピタ
キシャルシリコン層との接触部にpn接合を生じるため
、接触抵抗が著しく増大する。
Furthermore, when an aluminum-silicon alloy film is brought into direct contact with a silicon substrate as shown in Figure 1, the silicon (Si>) in the film diffuses into the aluminum due to the heat treatment during the wafer process, and the silicon substrate is exposed to the contact surface. As the layer grows epitaxially, it becomes a heterogeneous silicon layer and the contact resistance increases, and a pn junction is formed in the contact with the p-type epitaxial silicon layer containing aluminum, resulting in a significant increase in the contact resistance.

そのため、最近では第2図に示すような断面の電極構造
が用いられるようになってきた。本例の構造では、6が
モリブデンシリサイド(MoSi2 )膜で、このMo
Si2膜6をシリコン領域2とアルミニウム配線5との
間に介在させ、コンククト障害の発生を防止している。
Therefore, recently, an electrode structure having a cross section as shown in FIG. 2 has come to be used. In the structure of this example, 6 is a molybdenum silicide (MoSi2) film, and this Mo
A Si2 film 6 is interposed between the silicon region 2 and the aluminum wiring 5 to prevent contact failure from occurring.

しかしながら、このMoSi2股6のようなシリサイド
膜をシリコン層に直接接触して被着させる去、接触抵抗
が増え、特にp型シリコン層との間の接触抵抗が大きい
。且つ、長時間の熱処理を行なうと、次第にアルミニウ
ム配線からのアルミニウムが薄いMoSi2膜6を浸透
してシリコンと接触し、浅い接合を破壊してしまうため
コンタクト障害を生しるようになる。加えて、第2図に
示す電極構造も、第1図と同じように電極窓の肩部分S
でのくびれのため、断線し易いことは云うまでもない。
However, when a silicide film such as the MoSi bifurcated film 6 is deposited in direct contact with the silicon layer, contact resistance increases, especially contact resistance with the p-type silicon layer. Moreover, if heat treatment is performed for a long time, aluminum from the aluminum wiring gradually penetrates the thin MoSi2 film 6 and comes into contact with silicon, destroying the shallow junction and causing a contact failure. In addition, the electrode structure shown in FIG. 2 also has a shoulder portion S of the electrode window, as in FIG.
Needless to say, the wire is easily broken due to the constriction.

(C1発明の目的 本発明はこれらの問題点を無(して、極めて信頼性の高
い電極構造をもった半導体装置を提案するものである。
(C1 Object of the Invention) The present invention eliminates these problems and proposes a semiconductor device having an extremely reliable electrode structure.

fdl 発明の構成 その目的は、半導体基体上に形成された窓部ををする絶
縁膜と、該窓部内に形成された金属シリサイド膜と、該
金属シリサイド膜上に形成され、且つ該窓部に埋込まれ
た第1の導電層と、該第1の導電層」二に形成された第
2の導電層を有する半導体装置によって達成される。
fdl Structure of the Invention The purpose of the invention is to provide an insulating film forming a window formed on a semiconductor substrate, a metal silicide film formed in the window, and an insulating film formed on the metal silicide film and forming a window in the window. This is achieved by a semiconductor device having an embedded first conductive layer and a second conductive layer formed in the first conductive layer.

<e+ 発明の実施例 以下9図面を参照して実施例によって詳細に説明する。<e+ Embodiments of the invention Examples will be described in detail below with reference to nine drawings.

第3図および第4図は本発明にががる接続電極構造の断
面図を示しており、第3図は電極窓を白金シリサイド膜
11を介してモリブデン(Mo)膜12によってほぼ埋
没し、その上面にアルミニウム配線15を形成して接続
した構造である。また、第4図に示す電極構造は白金シ
リサイド膜11を介して導電性多結晶シリコン膜13で
埋没し、その上に反応阻止膜として窒化チタン(TiN
)膜14を介在さ−1、その上面にアルミニウム配線1
5を接続した構造である。これらの電極構造で、白金シ
リサイド19+1の代わりにパラジウムシリサイド膜を
用いてもよく、又No膜120代わりにタングステン(
W)膜、 MoSi2 H’A+ 夕7り/l/ シリ
サイド(TaSi2 ) Ij%を用いても良い。ごの
よ・うにすれば、接触抵抗の少ない電極が得られζ、長
時間に亘って使用してもコンククト障害が発生し難くな
る。
3 and 4 show cross-sectional views of the connection electrode structure according to the present invention, in which the electrode window is almost buried in a molybdenum (Mo) film 12 via a platinum silicide film 11, It has a structure in which aluminum wiring 15 is formed on the upper surface and connected. In addition, the electrode structure shown in FIG. 4 is buried with a conductive polycrystalline silicon film 13 through a platinum silicide film 11, and a titanium nitride (TiN) film is placed on top of it as a reaction prevention film.
) with a film 14 interposed therebetween, and an aluminum wiring 1 on its upper surface.
It has a structure in which 5 are connected. In these electrode structures, a palladium silicide film may be used instead of the platinum silicide 19+1, and a tungsten film may be used instead of the No film 120.
W) Film, MoSi2 H'A+ 1/l/silicide (TaSi2) Ij% may be used. By doing so, an electrode with low contact resistance can be obtained, and contact failure is less likely to occur even when used for a long time.

目、つ、本発明にかがる構造はシリサイド膜を被着させ
るのではなく、白金を被着して低温度の熱処理によりシ
リサイド化させるから、シリコン層との接触性がよい。
Second, the structure according to the present invention does not deposit a silicide film, but deposits platinum and converts it into silicide through low-temperature heat treatment, so it has good contact with the silicon layer.

この際、低温度の熱処理は素子特性を変動させないため
に重要なことで、それには白金シリサイド膜、バラジウ
J・シリサイド膜が適している。
At this time, low-temperature heat treatment is important in order not to change the device characteristics, and platinum silicide films and Balajiu J. silicide films are suitable for this purpose.

また、白金シリサイド膜11に直接アルミニウJ1膜を
被着した電極構造では、アルミニウム配線層は腐食され
易い。それは、白金の存在によってアルミニウム膜のエ
ンチング時に使用した塩素ガスの残留物が水洗処理中に
塩酸となり、アルミニウムをエツチングするためと考え
られている。しかし、本構造ではその問題が解消され、
信頼性が一層高められる。
Furthermore, in the electrode structure in which the aluminum J1 film is directly deposited on the platinum silicide film 11, the aluminum wiring layer is easily corroded. It is thought that this is because, due to the presence of platinum, the residue of the chlorine gas used when etching the aluminum film turns into hydrochloric acid during the water washing process, etching the aluminum. However, this structure solves that problem,
Reliability is further improved.

次に、第5図ないし第7図は第3図に示す実施例の電極
形成の工程順断面図を示している。第5図に示すように
PSG膜3に電極窓4を窓ありした後、蒸着法又はスパ
ック法によって膜厚200〜400人の白金(Pt)を
被着し、温度350〜450℃で熱処理して白金シワサ
イド(ptsi又はpt2 Si)膜11を形成する。
Next, FIGS. 5 to 7 show cross-sectional views in the order of steps for forming electrodes in the embodiment shown in FIG. 3. As shown in FIG. 5, after forming an electrode window 4 on the PSG film 3, platinum (Pt) is deposited to a thickness of 200 to 400 layers by vapor deposition or spacing, and heat-treated at a temperature of 350 to 450°C. A platinum wrinkled side (PTSI or PT2 Si) film 11 is formed using the following steps.

psclffJ3上に被着したptは熱処理して未反応
で残るから、熱処理後に王水でエツチングして除去する
。ここに用いられる金属+4料は、500℃以下の低温
熱処理によってシリサイド化される材料が必要であり、
白金あるいはパラジウム(Pct)が好適な材料である
Since the PT deposited on psclffJ3 remains unreacted after the heat treatment, it is removed by etching with aqua regia after the heat treatment. The metal +4 material used here needs to be a material that can be turned into silicide by low-temperature heat treatment at 500°C or less.
Platinum or palladium (Pct) are preferred materials.

次いで、第6図に示ずようにMol*x2をバイアスス
パッタ法によって電極窓がほぼ埋没するように被着する
。余分に被着したpscH臭3上のMo膜は公知のフォ
トプ1コセスによりエツチング除去する。
Next, as shown in FIG. 6, Mol*x2 is deposited by bias sputtering so that the electrode window is almost buried. The excess Mo film deposited on the pscH layer 3 is removed by etching using a known photoprocess.

この場合、バイアススパッタ法によって被着するとデポ
ジットとエツチングが同時に進行し、電極窓側面でのエ
ツチングの進行が速いため、側面にもMo膜12がなだ
らがな1項斜状に積層される。
In this case, when depositing by bias sputtering, the deposition and etching proceed simultaneously, and the etching progresses quickly on the side surfaces of the electrode window, so that the Mo film 12 is laminated on the side surfaces in a gentle one-term diagonal shape.

尚、バイアススパッタ法の代わりに低圧(0,2Tor
r程度)のCVD法でM0膜12を被着してもよい。
Note that low pressure (0.2 Torr) is used instead of the bias sputtering method.
The M0 film 12 may be deposited by a CVD method (approximately R).

その場合、シリコン基板1を350〜450’cに加熱
し、アルゴン又は水素中で五塩化モリブデンを熱分1a
a L、て被着する。CVD法であるから被覆性がよい
。また、シリザイド膜をCVD法でM!着することも可
能で、その場合には例えば五塩化モリブデンとモノシラ
ンとを熱分解して被着させる。
In that case, silicon substrate 1 is heated to 350 to 450'c, and molybdenum pentachloride is heated to 1a in argon or hydrogen.
a L, to be deposited. Since it is a CVD method, the coating properties are good. In addition, the silicide film is made using the CVD method. In that case, for example, molybdenum pentachloride and monosilane are thermally decomposed and deposited.

且つ、この埋没層は高温熱処理しなくても抵抗率の低い
材料が望ましい。上記に例示したW膜。
In addition, this buried layer is preferably made of a material that has low resistivity even without high-temperature heat treatment. W film exemplified above.

)josi2膜、 TaSi2膜は、このような抵抗率
の低い材料である。
) josi2 film and TaSi2 film are such materials with low resistivity.

次いで、第7図に示ずように膜厚5000〜7000人
のアルミニウム配線15をスパッタ法で被着し、パター
ンニングして、電極配線層を完成させる。
Next, as shown in FIG. 7, aluminum wiring 15 having a thickness of 5,000 to 7,000 layers is deposited by sputtering and patterned to complete the electrode wiring layer.

次に、第8図ないし第11図は第4図に示す実施例の電
極形成の工程順断面図を示している。まず、上記例の第
5図と同じく、第8図に示ずようにPSG膜3に電極窓
4を窓あげした後、蒸着法又はスパッタ法によって膜厚
200〜400人の白金(Pt)を被着し、温度350
〜450°Cで熱処理して白金シリサイド(PLSi又
はPh Si)膜11を形成する。また、パラジウムシ
リザイド(P[]2 Si)を形成してもよい。
Next, FIGS. 8 to 11 show cross-sectional views in the order of steps for forming electrodes in the embodiment shown in FIG. 4. First, as shown in FIG. 5 of the above example, after forming an electrode window 4 on the PSG film 3 as shown in FIG. Adhered, temperature 350
A platinum silicide (PLSi or Ph Si) film 11 is formed by heat treatment at ~450°C. Alternatively, palladium silicide (P[]2Si) may be formed.

次いで、第9図に示すように減圧CVD法によってn型
不純物をドープした多結晶シリコン膜13を被着する。
Next, as shown in FIG. 9, a polycrystalline silicon film 13 doped with n-type impurities is deposited by low pressure CVD.

PSG膜3の膜厚を1 tt mとすると、1〜1.5
μm程度の膜厚に被着して、電極窓をほぼ埋没させ、余
分のPSG換3上に被着しノコ多結晶シリコン膜はcF
4ガスを主体としたフレオン系ガスによる卜゛ライエツ
チング(リアクティブイオンエッチ)によって除去する
。この時、0.2Torr程度の減圧によるCVD法で
被着するため、被FH,性が良くて電極窓の側面にも十
分に積層される。
If the thickness of the PSG film 3 is 1 tt m, then 1 to 1.5
The polycrystalline silicon film is deposited to a thickness of approximately μm, almost burying the electrode window, and deposited on the excess PSG layer 3.
It is removed by reactive ion etching using a Freon-based gas mainly composed of 4 gases. At this time, since the film is deposited by the CVD method using a reduced pressure of about 0.2 Torr, it has good FH resistance and is sufficiently laminated on the side surfaces of the electrode windows.

次いで、第10図に示ずように膜厚1000〜2000
人のTiNIRI4をスパッタ法で被着する。TiNI
]ffはナタンを窒素ガスとアルゴンガスとの混合ガス
中でスパッタすると形成される。しかる後、第11図に
示すように、上面にアルミニウム配線15をスパッタし
て被着し、パターンニングする。そうすると、TiN1
’Jがアルミニウムとシリコンとの拡散を阻止する拡散
防止膜となる。
Next, as shown in FIG. 10, the film thickness is 1000-2000.
Deposit TiNIRI4 by sputtering. TiNI
]ff is formed by sputtering natanium in a mixed gas of nitrogen gas and argon gas. Thereafter, as shown in FIG. 11, aluminum wiring 15 is deposited on the upper surface by sputtering and patterned. Then, TiN1
'J becomes a diffusion prevention film that prevents the diffusion of aluminum and silicon.

コノヨウニすレバ、接続電極でのアルミ−ラムおよびシ
リコンの拡散による接触抵抗の増大が防止され、且つ平
坦化されたアルミニウム配線層が形成される。
An increase in contact resistance due to diffusion of aluminum and silicon in the lever and connection electrode is prevented, and a flattened aluminum wiring layer is formed.

(「)発明の効果 以上の説明から明らかなように、本発明にょれば接触抵
抗値は長時間の熱処理に対して変動が少な(て安定して
おり、且つ断線のない平坦なアルミニウム配線層が得ら
れ、ICの信頼性向上に大きく貢献するものである。
(``) Effects of the Invention As is clear from the above explanation, according to the present invention, the contact resistance value is stable with little fluctuation even after long-term heat treatment, and a flat aluminum wiring layer with no disconnection is achieved. This greatly contributes to improving the reliability of ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の接続電極の断面図、第3図
および第4図は本発明にかかる接続電極の断面図、第5
図〜第7図は第3図に示す接続電極の形成工程順断面図
、第8図〜第11図は第41凹に示す接続電極の形成工
程l1IllliWr面図である。 図中、1はP型シリコン基板、2はn型シリ:1ン領域
、3はPSG膜(絶縁B’J)、4は電極窓。 5.15ばアルミニウム配置泉層、11は白金ンリザー
イド、12はモリブデン膜、13は導電性多結晶シリコ
ン膜、14は窒化チタン膜を示している。 第1−図 乙 第 2 図 第3図 第51列 第7図
1 and 2 are cross-sectional views of a conventional connection electrode, FIGS. 3 and 4 are cross-sectional views of a connection electrode according to the present invention, and FIG.
7 to 7 are sequential cross-sectional views of the process of forming the connection electrode shown in FIG. 3, and FIGS. 8 to 11 are sectional views of the process of forming the connection electrode shown in the 41st recess. In the figure, 1 is a P-type silicon substrate, 2 is an n-type silicon region, 3 is a PSG film (insulating B'J), and 4 is an electrode window. 5.15 is an aluminum arrangement spring layer, 11 is platinum lizard, 12 is a molybdenum film, 13 is a conductive polycrystalline silicon film, and 14 is a titanium nitride film. Figure 1 - Figure B Figure 2 Figure 3 Column 51 Figure 7

Claims (1)

【特許請求の範囲】[Claims] 半導体基体上に形成された窓部を有する絶縁膜と、該窓
部内に形成された金属シリサイド膜と、該金属シリサイ
ド膜上に形成され、且つ該窓部に埋込まれた第1の導電
層と、該第1の導電層上に形成された第2の導電層を有
することを特徴とする半導体装置。
An insulating film having a window formed on a semiconductor substrate, a metal silicide film formed in the window, and a first conductive layer formed on the metal silicide film and embedded in the window. and a second conductive layer formed on the first conductive layer.
JP23862683A 1983-12-16 1983-12-16 Semiconductor device Pending JPS60130165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23862683A JPS60130165A (en) 1983-12-16 1983-12-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23862683A JPS60130165A (en) 1983-12-16 1983-12-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60130165A true JPS60130165A (en) 1985-07-11

Family

ID=17032936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23862683A Pending JPS60130165A (en) 1983-12-16 1983-12-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60130165A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0597587A1 (en) * 1992-10-13 1994-05-18 AT&T Corp. Multilayer contacts for semiconductor devices, comprising impurities
US6107687A (en) * 1997-03-18 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having interconnection and adhesion layers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0597587A1 (en) * 1992-10-13 1994-05-18 AT&T Corp. Multilayer contacts for semiconductor devices, comprising impurities
US6107687A (en) * 1997-03-18 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having interconnection and adhesion layers

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