JPS60129677U - Test board for integrated circuits - Google Patents

Test board for integrated circuits

Info

Publication number
JPS60129677U
JPS60129677U JP1762584U JP1762584U JPS60129677U JP S60129677 U JPS60129677 U JP S60129677U JP 1762584 U JP1762584 U JP 1762584U JP 1762584 U JP1762584 U JP 1762584U JP S60129677 U JPS60129677 U JP S60129677U
Authority
JP
Japan
Prior art keywords
test board
integrated circuits
integrated circuit
contact
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1762584U
Other languages
Japanese (ja)
Inventor
黒木 優一郎
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1762584U priority Critical patent/JPS60129677U/en
Publication of JPS60129677U publication Critical patent/JPS60129677U/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは従来のテストボードの斜視図、第1図すは従
来の試験用ICとテストボードの実装を示す模式図、第
2図は一実施例のテストボードの斜視図、第3図は漏斗
状コンタクトプローブの断面図、第4図aおよ゛びbは
試験用ICとICテスト 。 ボードの実装過程を示す模式図をそれぞれ示している。 図において、1は従来のテストボード、11〜1nはコ
ンタクトプローブ、2は試験用IC,2−1、、、′:
 ”=’二gコ〒5H7−;、7−;はコンタクトプロ
ーブ受台、5はスプリング、6は漏斗状導電体をそれぞ
れ示している。
Fig. 1a is a perspective view of a conventional test board, Fig. 1 is a schematic diagram showing the mounting of a conventional test IC and a test board, Fig. 2 is a perspective view of a test board of one embodiment, Fig. 3 Figure 4 is a cross-sectional view of the funnel-shaped contact probe, and Figures 4a and 4b are the test IC and IC test. Each shows a schematic diagram showing the board mounting process. In the figure, 1 is a conventional test board, 11 to 1n are contact probes, 2 is a test IC, 2-1,...':
"='2g 5H7-;, 7-; indicates a contact probe holder, 5 indicates a spring, and 6 indicates a funnel-shaped conductor, respectively.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のコンタクトプローブを植設し、該コンタクトプロ
ーブにて集積回路の端子を当接せしめ当該集積回路の測
定を行う集積回路用テストボードにおいて、前記コンタ
クトプローブの少なくとも3ケ所の先端部に、前記集積
回路の端子を案内し、全ピンの当接を行い得る漏斗状導
電体を付設したことを特徴とする集積回路用テストボー
ド。
In an integrated circuit test board in which a plurality of contact probes are installed and the terminals of the integrated circuit are brought into contact with the contact probes to measure the integrated circuit, the integrated circuit A test board for integrated circuits, characterized in that it is equipped with a funnel-shaped conductor that can guide circuit terminals and bring all pins into contact.
JP1762584U 1984-02-10 1984-02-10 Test board for integrated circuits Pending JPS60129677U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1762584U JPS60129677U (en) 1984-02-10 1984-02-10 Test board for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1762584U JPS60129677U (en) 1984-02-10 1984-02-10 Test board for integrated circuits

Publications (1)

Publication Number Publication Date
JPS60129677U true JPS60129677U (en) 1985-08-30

Family

ID=30505500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1762584U Pending JPS60129677U (en) 1984-02-10 1984-02-10 Test board for integrated circuits

Country Status (1)

Country Link
JP (1) JPS60129677U (en)

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