JPS60127898A - Composite time division switch - Google Patents

Abstract

PURPOSE:To improve the economy of equipment by accommodating the line to preserve the time slot order to the incoming said and adding a time division switch to preserve the time slot order to the incoming side of the normal time division switch. CONSTITUTION:The time slot number (n) is one frame of a connecting line group 63 and the time slot number (k) of an outgoing line group 66 have the relation of n>=k and the line group 66 is connected selectively to the line group 63. The time slot number (m) of the incoming line group 65 and the time slot number (l) of the output line group 67 have the relation of n+m=k+l. In case of 64nkbps switch operation, a time division switch SWA62 executes substantial switch operation from the incoming line group 61 to the line group 63 set by, e.g., a path and the line group 63 selects a predetermined line of the line group 66 via the time division switch SWM64.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a composite time-division switch that includes multiple information in information digitized at a switching point of a communication network and performs time-division exchange.

[Background of the invention]

In general, a composite time-division switch handles the bit rate of 54 kbps for the purpose of transmitting telephone voice in the existing communication network as call information for one channel, and also follows this data transmission speed for high-speed data of 64 kbps or more.゛(
54xm) kbps (where m is the positive OV number), %m1 line communication paths are handled simultaneously for the same data transmission.

FIG. 1 is a functional block diagram showing the main configuration of a time division switch. Entrance lineman,・I,...In is 54k on the phone.
For bps lines, the multiplexer (hereinafter referred to as MUX) 11 is 5
Time division switch (TD8W) with transmission speed of 4n kbps
) 12, and this time division switch 12 performs a switch operation by exchanging the positions of the time slots having the 8-bit PCM code, and transmits the code to the demultiplexing device (hereinafter referred to as DMUX) 13 at a transmission rate of 64 nkbps. Then, this DMUX 13 connects the outgoing line O in the order of the time slot position.
8.02...Distribute 8-pits) PCM code to each On. The central control unit 14 controls the above exchange function operation by making full use of a clock circuit, a counter circuit, and a memory.

Next, the principle of the time division switch will be explained with reference to FIG.

FIG. 2 is an fC functional block diagram showing part of the time division switch and central control unit of FIG. 1 as well as the arrangement of data information on the outgoing transmission line to the time division switch. In FIG. 2, input path 21 is connected to output path 23 via speech path memory (SPM) 22. In FIG. The change of the time slot position by the communication path memory 22, that is, the switch, is performed by the switching means 25 of the control unit 24, and the synchronization counter 26 with the incoming line Ii
Accordingly, the readout follows the switch control information obtained by the called number from the calling party and stored in the switch memory (SWM) 27. The control unit 24 is connected to an input transmission interface unit and an output transmission interface unit (both not shown) by control lines, and transmits and receives control signals via the transmission lines, and also transmits and receives control signals for timing circuit gllr28Fi exchange. It is used for time slot synchronization and also sends timing information to the transmission interface section.

The input path 21 in FIG.
-C, , and call data A2・B,・C in the second frame
Transmit 2. Call route memo +7, (SPM) 22 is the incoming lineman, and the call data A, B1 and C1 are synchronized to the respective positions of ・I2 and ■, and the counter value l of the counter 26 is
Write and memorize according to 2 and 3. On the other hand, when the synchronization counter 26 is switched to the switch memory (5WfVl) 27 that specifies the connection of the destination outgoing line 0i obtained from the control signal to the incoming line Ii, the output line 23 is written to the communication path memory 22. The stored call data is read out according to the comparison table in the switch memory 27. Assuming that writing and reading are performed alternately in this order for each piece of data, according to the comparison table in the switch memory 27, the call data A, A2 of the incoming line worker will be It is read out in the time slot of the exit line O2 in the first frame and the second frame. Similarly, data B, .

[Prior art and its problems]

A conventional composite time division switch will be explained with reference to the drawings. Fig. 3 is an explanatory diagram showing an example of the positional relationship between the time slots for each route and the time slots of the expressway to be time-division switched in the time-division switching system, and Fig. FIG. 3 is a time slot configuration diagram showing an example of the position of data on a highway of a time division switch when the section is multi-dimensional information.

In FIG. 3, I'viUX31 is the input line 11 of n-way
~In are accommodated, n multiplexed, arranged on one highway in the order of input lines, and connected to a switch. The SPM 32, which is a constituent element of the switch, converts the data 'f: 8 bits in the time slot corresponding to each of the input time slots and ~In for each frame of 125 μs, which arrives sequentially from the input high-speed path, to the PCM code. Drink and write synchronous counters. Next, a switch memory (SWM) 34 of an ingress/egress time slot selected from an egress time slot according to the called information obtained from the calling side and an empty egress time slot according to the box status information of this egress route.
Accordingly, data is read from the SPM 32 in the order of the outgoing time slot O1 and transferred to the outgoing fast path. DMUX
38 distributes the information input from the expressway to the outgoing line Of for each time slot. According to Figure 3 (if
) I,, I,, I,, d7 on each n.
The first frame contains data A, B, C, and the second frame contains data A2. B2. C2 is transferred. The time slots of the ingress line Ii and the outgoing line 0i are 8 bits/
125μs and 54kbps telephone line and bird contact is 1
One frame of 25μs contains 8n bits and is 64nkb.
Given the transmission rate of ps, this time slot is 8 bits and 1257n μs.

First, at 8PM32 for the input time slot Ii, the first frame of data A, B, C, is input to the input time slot 'In I! Write to II III゛ -1, iL. δ
■゛M34 has an ingress line I for each of the outgoing lines 0゜0.0□, 11. Instructs to connect I, , 1-
Ru. These operations are realized by repeating writing and reading for each time slot. Outgoing time slot 0. Since the human time slot ep data B1 has not yet been written to the SPM32, data B is transferred to the next frame.Therefore, data A1 is transferred to the outgoing time slot O0゜Oo of the first frame. .C, and the output time slots o,,o,,01!+ of the second frame include data B,,A2.C2.

In Figure 4, the human circuit Lx transmits data containing 16 bits in 125 μs (therefore, the transmission speed is 128 kbps).
When , two 8-bit time slots ■, and ■,
Assume that you use Since data D and D2 become different data if this order is disrupted, this time slot order must be preserved.

The normal 1[talk line operator and I4] transfer data A and B in units of 8 bits at a transmission rate of 54 kbps.

MUX 41 provides 8-bit data D, D2 to telephone lines I, ~, fully multiplexed time slot E, and ~14, respectively.
．． A.

1 frame is 125 μs including B, 256 kbps
transfer data to the switch at a transmission rate of

In FIG. 5, three output examples for the input of FIG. 4 are shown. In normal telephone exchanges, time slots (8-bit
54 kbps) and p1. Therefore, as shown in Figure 5 (1), ((The order of data D and D2 may be reversed. Figure 5 (2) shows the time order of the time slots. This is an example of saving only the frame position relationship and not saving the frame position relationship, and although this can be achieved with notware processing, it is necessary to obtain information from the calling side or the user about the contents of the signal to be exchanged. In addition, if the time slot I-order is not saved at each switch stage, a function is required to add order information to each time slot and adjust the order at the terminal.

Figure 5 (3) further preserves the frame position relationship in the time order of time slots, and in the fc example, the memory of the time division switch (for example, SPM in Figure 3) has two sides, and the time is 125 μs.
Each page is written on one side, the other side is written, and the I7 is used for output, which can be handled using only hardware.

When adding a 54 nk, bps data line to a normal telephone line network and simultaneously exchanging it using a time division switch,
If each time division switch has two sides of the speech path memory (SPM) for the function of saving the time slot order, transmission delays will occur, but compared to the method of saving the time slot order by software, , the negative phase of the software can be reduced, and the conventional 54kbp
It has the advantage of being able to be used for programs in units of s.

However, the conventional back-to-back time division switching system has a problem in that it is not economical because all time division switches are equipped with two-sided memories in order to preserve the order of time slots.

[Purpose of the invention]

An object of the present invention is to accommodate the line whose time slot order is to be preserved on the input side and to add a time division switch to the input side of a normal time division switch that can preserve the entire time slot order. The solution is to solve the problem of 1 + 4, and to provide a time-sharing switch that can be obtained by changing the structure of the association.

[Thanks for the invention]

In the composite time division switch according to the present invention, among the input lines of multiple digital circuits, the time slot Jli2 is connected to the first one whose order is to be preserved; ] When connecting these 111 wires in an exchange, it is necessary to calculate the time slot order of the lines with a speed of n-i (n is a positive jV number) of unit speed. a first h° minute 11 switch to be stored in the first h° minute 11 switch, a second inlet line group whose time slot order is inconvenient among the inlet lines, and the connection port one 11. Among the 712 outgoing lines, the first outgoing line group whose time slot order is to be saved and the second outgoing line rod whose time slot order cannot be saved are accommodated on the outgoing side, and these lines are exchanged. a second time division switch that cannot store in hardware the time slot order of a line having a speed n times the connection unit speed when connected, and the first time division switch selects a time slot order from the first incoming line group. The second time-division switch switches and connects the incoming calls of 7 to the time slots corresponding to the first outgoing line group and corresponds to a predetermined route of the connected line group, and the second time division switch fnJ
The apparatus is characterized in that an incoming call from the first connecting line group is switched and connected to the first outgoing line group.

〔Example〕

FIG. 6 is a block diagram showing an embodiment of the composite time division switch of the present invention, FIG. 7 is a block diagram showing a detailed example of the switch (8WM) in FIG. 6, and FIG. 8 is a block diagram showing a detailed example of the switch (8WM) in FIG. FIG. 9 is a time slot configuration diagram showing an example of the positional relationship of the time slots of the time division switch.

In FIG. 6, the first incoming line group 61 is 64 nkbps.
It is housed on the input side of a first time division switch (SWA) 62, which has two sides of time division switch memory so that the time slot order can be stored in the hardware. be done. The output 1IlI of this time division switch 62 is connected to the L time slot via the connection line group 63e having the same number of time slots as the input G11j) (
SWM) 64. The second incoming line group 65 is housed on the incoming side of the time division switch 64, consisting of 64 kbps lines that do not need to be saved in the 11th time slot. 1st
The outgoing line group 66 consists of lines that can preserve the time slot order, and the second outgoing line group 67 includes lines that cannot preserve the time slot order. be accommodated in. When the number of time slots in one frame of the connection line group 63 is n1 and the number of time slots of the output line group 66 is 5, the relationship n≧ holds and the exit line tax is -
66 can always be selectively connected to the connection line group 63. When the number of time slots in the incoming line group 65 is m and the number of time slots in the outgoing line group 67 is t, the relationship n -1-m = k + t holds. 6.4 For nkbps switch operation,
A time division switch (8WA) 62 performs a substantial switching operation from an incoming line group 61 to a connection line group 63 installed on the route side, and the connection line group 63 is a time division switch (SW
M) 64 to select a predetermined line (time slot) of the outgoing line group 66; Therefore, 64
In the case of nkbps switching operation, the connection line group 63 is not connected to the output line group 67.

FIG. 7 shows the flow of data inside the time division switch (SWM) 64 of FIG. Connection line group 63 and incoming line group 6
5 is accommodated in a MUX 641, multiplexed, and sent out to a highway 642 having a series of time slots. TDSW6
43 is the time slot of the incoming expressway wT642 and the outgoing expressway 6
44 time slots. DMUX64
5 distributes the time slot sequence of the expressway 644 to the routes and sends it to outgoing lines h66 and h67.

FIG. 8 shows an example of the time slot position of MUX 641 in FIG. 7. Lines 11 and ■3 of the connection line group 63 are the 6th
As explained in the figure, in each time slot, data A, .A2.A, and B, .B2.B are switched and arranged in the direction. Lines ■5 and ■ of incoming line group 65. is a 54 kbps line, and the data C7, C2, Cs and B2, D are in the time slots j, respectively.
, each time slot is 8 bits/125μ
It is s. M, UX 641 multiplexed data is sent to expressway 642: f1. ．． 1 frame/125μs
The data of the time slots of line work, ... work, ... old time slots are arranged in . 1; l in Figure 8: Line numbers 1, 3, 5
・Data A in the first frame of 2 for 9th L,
・B, ・C,,D, also have data A2・in the second frame.
B2, C7, and B2 are distributed.

Next, in FIG. 9, expressways 642 and 644 are
7 shows the high-speed paths in and out of the TDSW 643 in Fig. 7. 1 frame includes 12 time slots with 8 bits in 125 μs (64 k x 12 =
) Transmission speed is 768kbps. Referring to the explanation of FIG. 8, it is necessary to preserve the time slot order of time slots 11 and 5 of the inbound expressway 642, but there is no need to preserve the time slot order of time slots I and 4. Time slots 03, 07, 0. .

are allocated periodically. The control circuit of the switch is connected to the input lines ■1 and I3 included in the connection line group 63 in FIG.
are connected to the outgoing lines O8 and 07 included in the outgoing line group 66 (see No. 61-1 and FIG. 7), respectively. Outgoing line 0. , 0? and 01. Since the time slots assigned periodically as shown in FIG. Then, the time slots on the connection line group 63 can be obtained from this correspondence. Therefore, switch operations on the SWM 64 are performed according to this correspondence, and the actual switch fabrication is performed in the swA 6i. On the other hand, the data CD of the incoming line group 65 including normal incoming line operators, . (see Figure 7) is assigned to the outgoing lines 0, 2, and 01°.

In the above embodiment, it was explained that the time division switch has a two-sided communication path memory 7 and is capable of storing the time slot order. The slot order storage means is not limited to two-sided channel memory. In addition, although it was invented that the respective time slots having a one-to-one correspondence on the outgoing line and the connection line group are periodically allocated, it is not possible to determine the location where the time slots have a one-to-one correspondence. The same function can also be achieved by assigning it to In addition, compared to the number of lines that do not require time slot order preservation, there are a small number of lines that require time slot order preservation.
J order childcare is made possible by two sides of the communication path memory.
A time division switch that is connected to a regular time division switch that cannot preserve the order of time slots via a division switch, and therefore enables preservation of the order of time slots using hardware on a smaller scale than a normal time division switch. Visit 1
It is large-scale and A: (
N++: The economical effect of eliminating the need for memory addition is [
7.

〔Effect of the invention〕

As explained above, according to the present invention, the second time-division switch that cannot preserve the order of time slots connects the incoming line that preserves the order of time slots to the hardware that preserves the order of the time slots of this incoming line. the first with
In addition to connecting via a time division switch, the input time slots exchanged by this time division switch are assigned to outgoing lines by valving a connection path that preserves a predetermined time slot order. The effect of economical mourning can be obtained.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the 9 main components of a time division switch, Bag 2
The figure is a block diagram that clearly explains the principle of a time division switch.
Figure 3 shows the positional relationship of time slots in the time division system and time division 1! A block diagram showing an example of the memory of the switch, Figures 4 and 5 are examples of the time slot situation of S when multiple information 11'cr is included? 6 is a block diagram showing an embodiment of the composite time division switch of the present invention. FIG. 7 is a block diagram showing a detailed example of the switch (SWM) in FIG. 6. 9 and 9 are time slot configuration diagrams showing an example of the time slot status of the main part of FIG. 7. 61.65...Incoming line group (1st and 2nd incoming line group) , 62.64... Time division switch (first...
2nd time division switch), 63... connection line group, 66, 67...... outgoing line group (first. each 12 outgoing line groups). Figure 4 5th leap

Claims (1)

[Claims] Among the incoming lines of a plurality of digital lines, the first incoming line group that should have a time slot order is accommodated on the incoming side, and the other connecting line group is accommodated on the outgoing side, and when these lines are exchanged and connected, the connection unit speed n a first time-division switch that is capable of storing the time slot order of a line with a speed twice as high (n is a positive number) in hardware; A first outgoing line group whose time slot order is to be preserved among the outgoing lines and a second outgoing line group whose time slot order cannot be saved are accommodated on the outgoing side, with the connection line group being accommodated on the ingress side; and a second time division switch that cannot store in hardware the time slot order of a line having a speed n times the connection unit speed when the first time division switch connects the first time division switch.
The second time-division switch switches and connects incoming calls from the incoming line group and assigns them to time slots corresponding to a predetermined strategy of the connecting line group and corresponding to the first outgoing line group, and the second time division switch A composite time division switch characterized by switching and connecting incoming calls from the first outgoing line group to the first outgoing line group through a connection path that preserves a predetermined time slot order for the lines of one outgoing line group.