JPS6012788A - Electronic circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit device such as a memory, which is constructed by attaching a large number of electronic components such as ■0 to a printed wiring board.
The purpose is to provide an electronic circuit device that enables higher density packaging and smaller size than conventional systems.

As is well known, in electronic equipment, a large number of electronic circuit devices are used in which a large number of components are attached to printed wiring boards.

As a typical example, an electronic circuit device such as a memory generally has a configuration as shown in FIG.

What is shown in FIG. 1 is a memory of m bits) x [number of words per IOi xn] words, and although not shown, the power supply and ground are all connected in parallel to the IO terminals.

In this configuration, if you look at the IJ rack rows, everything except the chip select signal is connected in parallel.

Here, n-8, the number of chip select signals for each IO is 3.
If the selection is made as shown in Table 1, the configuration will be as shown in Figure 2 (2χ).

Furthermore, the relationship between n and N is n = 2111. 11゜Table 1 If you pay attention to the rows of the IC matrix in Figure 2, all the signals are connected in parallel.

In IIL child circuit devices such as memory, ty
Conventionally, in order to mount each IO on a wiring board and connect addresses, input/output data, town, etc., the front and back sides of the printed wiring board were patterned as shown in Figures 3 and 4. , as shown in Figure 5, were installed side by side. Note that the number t is the bin number. -However, with this pattern I
If an attempt is made to narrow the mounting pitch of C, there is a portion A, so there is a limit to narrowing the interval between mounting electronic components such as IO, and it is not possible to sufficiently increase practical fa. In other words, if the distance is less than the distance that would occur if you try to narrow the part A, then ri
The '4-conductor-' creates a contact force, and it is not possible to narrow the distance any further.

Therefore, the present invention makes it possible to improve mounting efficiency by arranging the bin numbers of at least some of the adjacent electronic parts in the same manner, thereby reducing the electron = lSl collection surface nt of the electronic circuit.

An example of the implementation of the present invention will be described below based on the drawings.

FIG. 6 shows the IO arrangement and its arrangement in the present invention, in which every other IO is arranged in a 10t arrangement in which the arrangement of terminals is reversed from that of the associated IC.

The major difference from the conventional chisel turn is that the common connection line B of the welding process 0 is made a straight line in order to connect the IC groups in the array.

With this arrangement, even if the IO mounting pitch is limited, since the part B is a direct part, it is possible to closely mount ICs, and the mounting density can be increased compared to the conventional method.

Furthermore, with the memory shown in Figure 2, it is also possible to insert two 6. Q: It is possible to perform high-density actual battles compared to the conventional method.

In the above explanation, we have described the example of a station building that is applied to a memory device as the most effective example, but in addition to this, PLA (
programmable logic array), transistors,
It goes without saying that by applying the method to the parallel connection of li'BT modules, the packaging density can be increased and the device can be miniaturized.

[Brief explanation of the drawing]

Figures 1 and 2 are four-dimensional diagrams of conventional electronic circuit devices;
Figure 3 shows the pattern on the front surface of the printed wiring board of the slave circuit device, Figure 4 shows the pattern on the back side, and Figure 5 shows the arrangement of ICs in the conventional device. figure,
p1λGNI is a diagram showing the arrangement of ICs in the embodiment of the present invention, FIG. 7 is a diagram showing the pattern on the surface of the printing arrangement board in the embodiment of the invention. FIG. 9 is a diagram showing the pattern on the surface of a printed image or one board in different embodiments. I 001 e I Oo* -Electronic component 1, u, 9,
16...Pin number Patent applicant Juki 1;1. Keibakuji System Co., Ltd.
Agent Hattori Shumonbei-'; 5 ``iwa; ILel JC#A JLsu?'''τ71'1 81st Crystal 1 Houkie, ,, ICz+°ICzrz LQ) <b)

Claims (1)

[Claims] A large number of electronic components having dual in-line type connection terminals are connected in parallel to conductive wires on a printed wiring board, with most of the connection terminals having the same or similar or mutually related functions and performances having the same rank. An electronic circuit device, characterized in that at least a portion of the terminals of the electronic components to be connected in parallel are arranged in the same order as terminals of adjacent electronic components.