JPS60126848U - Pass line level setter - Google Patents
Pass line level setterInfo
- Publication number
- JPS60126848U JPS60126848U JP1564384U JP1564384U JPS60126848U JP S60126848 U JPS60126848 U JP S60126848U JP 1564384 U JP1564384 U JP 1564384U JP 1564384 U JP1564384 U JP 1564384U JP S60126848 U JPS60126848 U JP S60126848U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- resistance
- pass line
- line level
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のバスマージンテ、（トを説明するための
バスターミネータ回路図、第２図は本考案の一実施例を
示す回路図である。
１．２，３．４・・・デバイス、５・・・パスライン、
６・・・ターミネート抵抗、ＲＨｕ５ ＲＮＬＩ、Ｒら
Ｕ・・・ブルーアップ抵抗、Ｒ）、Ｉｏｇ ＲＮＤ！
ＲＬＤ・・・プルダウン抵抗、Ｓｌ、、Ｊ、ＳｏＵ、Ｓ
ｎＤ・・・スイッチ設定。FIG. 1 is a circuit diagram of a conventional bus terminator for explaining a conventional bus terminal, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1.2, 3.4... Device , 5...pass line,
6... Termination resistor, RHu5 RNLI, R et U... Blue up resistor, R), Iog RND!
RLD...Pull-down resistor, Sl,, J, SoU, S
nD...Switch setting.
Claims (1)
ムにおいて、パスラインのターミネータとしてプルアッ
プ抵抗とプルダウン抵抗の夫々の抵抗値を連動で又は個
別に切換えできる抵抗ネットワーク内蔵のＤＩＰタイプ
スイッチを設け、上記スイッチは通常時は設計される終
端抵抗になる切換位置にスイッチ設定し、バスマージン
テスト時は該マージンに応じた抵抗になる切換位置にス
イッチ設定するターミネータ抵抗の切換回路に構成した
ことを特徴とするパスラインのレベル設定器。In a computer system that connects devices using a bus method, a DIP type switch with a built-in resistor network that can switch the resistance values of a pull-up resistor and a pull-down resistor individually or individually is provided as a terminator for a pass line. A path characterized in that the switch is configured in a terminator resistance switching circuit in which a switch is set to a switching position that provides a designed terminating resistance during normal times, and a switch is set to a switching position that provides a resistance corresponding to the margin during a bus margin test. Line level setting device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1564384U JPS60126848U (en) | 1984-02-06 | 1984-02-06 | Pass line level setter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1564384U JPS60126848U (en) | 1984-02-06 | 1984-02-06 | Pass line level setter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60126848U true JPS60126848U (en) | 1985-08-26 |
Family
ID=30501671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1564384U Pending JPS60126848U (en) | 1984-02-06 | 1984-02-06 | Pass line level setter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60126848U (en) |
-
1984
- 1984-02-06 JP JP1564384U patent/JPS60126848U/en active Pending
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