JPS6012670B2 - Buffer invalidation method in multi-CPU system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for invalidating buffer storage, so-called cache memory, in a multi-CPU (Central Processing Unit) system.

The basic configuration of a multi-CPU system is multiple CPUs, channels, and an MSU (main storage unit).
It consists of.

This MSU has a relatively slow access time but can store a large amount of storage, and is shared by the plurality of CPUs. In such a multi-CPU system, the MS
Even if a faster access time is requested for U, the operation of the MSU is inherently relatively slow, and there is a limit to how fast it can be made. Therefore, each of the multiple CPUs is equipped with a built-in buffer storage capable of high-speed operation, and the MSU
sequentially transfer the contents stored at the desired address and the surrounding addresses to the buffer storage,
A method is used in which each CPU reads and writes data to and from internal buffer storage to achieve high-speed operation. This is based on the fact that a program generally progresses sequentially, and if a certain address of the MSU is specified at a certain point, then the vicinity of that address will be specified at the next point. In this case, the problem is that after one CPU takes in the contents of a certain address of the MSU and its neighboring addresses into its own buffer storage, the other CPUs import the contents of the MSU at that address and its neighboring addresses. If new data is written to the CPU', the content already taken in by the CPU' becomes meaningless and cannot be used as data from now on. Therefore, if such new data writing occurs in the MSU, the contents of the address that has been taken into the buffer storage in the first CPU must be prohibited from being used. This prohibition of use is generally called invalidation. Conventionally, in order to perform invalidation, an invalidate line is installed between one CPU and another CPU, and when one CPU writes new data to the MSU, the invalidate line is installed to the other CPU's. It notifies the MSU that new data has been written via the address line, and also notifies to which address the data has been written via the address line.

Then, if other CPUs have a corresponding address within themselves, they immediately invalidate the contents. In such a conventional buffer invalidation method, each CPU must have a function to notify other CPUs of invalidation information, and invalidation lines and address lines must be installed between each CPU. It is uneconomical in terms of function and circuit structure. This means that multi-CP
As the number of CPUs configuring the U system increases, this problem becomes more and more noticeable. Therefore, the present invention proposes a buffer invalidation method in a multi-CPU system that can avoid the above-mentioned diseconomies.

In accordance with the above object, the present invention focuses on the fact that CPUs, MSUs, etc. in a multi-CPU system are generally connected to each other in a common bus format, and is characterized in that buffer invalidation is executed via this common bus. That is.

In other words, when one CPU stores data in the MSU via the common bus, other CPUs can also see the data store command through the common bus, and at this time, they can check the store address. You can also take a peek. Therefore, other CPUs can independently invalidate themselves based on the peeked results. The present invention will be described below with reference to the drawings.

The attached figure is a block diagram illustrating a multi-CPU system to which the present invention is applied. In this figure, 11-0...
...11-, 2, 11-3 are CPUs, and this shows the case where there are four CPUs (11-1 are not shown)
. Each CPU II-0 to 11-3 can exchange data with each other via the common bus 12, and on the other hand,
The MSU 13 is shared via the common bus 12. now,
Suppose that the contents related to the address area of MSU 13 are stored in the buffer storage 14-0 in CPU II-0, and the contents related to the address area A3 of MSU 13 are stored in the buffer storage 14-3 in CPU II-3. It is assumed that such content is stored. Here, CPU I
-2 stores data in the address mirror of MSU13. In this case, as shown in the figure, the address area A2 partially overlaps with the address area O, so the overlapping area (indicated by double hatching) is
Buffer storage 14 in PUII-0 must invalidate the contents already stored. At this time, conventionally, CPUII-2 was
−. '11-I'll-3 was to be notified of invalidation and its address, but
In the present invention, the intended invalidation is executed as follows. When the aforementioned CPU II-2 stores data to the MSU 13, a flag byte indicating a store command, an address bit string indicating the address to perform the store, and a data byte indicating the data that is the contents of the store. forms a series of data formats,
The data format is sent from the CPU 1-2 to the common bus 12 and transferred to the MSU 13. In this case, it should be noted that since the data format is sent to the common bus 12, other CPU II-0.11-3 (not shown CPU
I-1) can also peek into its data format. In order to perform this peek,
Each CPU II-0 to 11-3 includes flag detection gates 15-0 to 15-3. These flag detection gates 15-0 to 15-3 detect whether or not a flag byte indicating the store command is present on the common bus 12.
If a flag byte exists, the address to be stored in the MSU 13 is temporarily stored in internal address registers 16-0 to 16-3 using the flag detection gate.
In the above example, the contents of address register 16-0 to 16 other than address register 16-2 are
-3 will be stored. Furthermore, within each CPU, internal buffer storage 14-0 to 14-3 (1
4 and 2) exists. This verification is performed by comparing the address register and the address tables 17-10 to 17-3 (excluding 17-2) in verification circuits 18-0 to 18-3, and if a match is found by this verification, an automatic Invalidate the buffer storage within. The address tables 17-1 to 17-3 are portions that hold a correspondence table between the addresses of each buffer storage and the address of Mtaka U. In the above example, the contents of the address area public 2 stored in the address register 16-0 in the CPU II-0 and the contents of the address area held in the address table 17-0 partially overlap, so the verification circuit 18-0
will match the duplicate address and invalidate a portion of the associated buffer storage 1410. In this way, a buffer invalidation method using the common bus is implemented. As explained above, according to the present invention, each CPU is provided with a function for notifying other CPUs of invalidation, and is provided with an invalidation line for notifying each CPU of this notification. A highly economical buffer invalidation method can be realized, especially in a multi-CPU system having a large number of CPUs, without requiring measures such as installing address lines to be invalidated between each CPU.

[Brief explanation of the drawing]

The attached figure is a block diagram illustrating a multi-CPU system to which the present invention is applied. In the figure, 11-0 to 11-3 are CPU, 1
2 is common bus, 1 3 is MSU, 1 4-0 to 14
-3 are buffer storages.

Claims (1)

[Claims] 1 Common bus and multiple Cs that engage with the common bus
PU, and a main storage unit shared by the plurality of CPUs via the common bus, each CPU sequentially stores data in a specified address area in the main storage. It has a buffer storage for transferring and storing data, and each CPU reads and writes data to its own buffer storage, and also writes new data to the main storage unit. When a multi-C
In the buffer invalidation method in PU,
When writing data to a predetermined address area within the main storage unit, each CPU sends a command to store the write data to the main storage unit using flag information and a command to store the write data in the main storage unit. Address information in the main storage unit and the write data are sent to the common bus, and each CPU includes a flag detection gate for detecting that the flag information has appeared on the common bus, and a flag detection gate for detecting that the flag information has appeared on the common bus; an address register that temporarily stores the address information through the flag detection gate opened by the buffer storage; and an address register for temporarily storing the address information through the flag detection gate, which is opened by the buffer storage; an address table holding a correspondence table between the main storage unit and the main storage unit; and a check for detecting that address information stored in the address register at least partially overlaps with an address in the main storage unit held in the address table. circuit, and in each of the CPUs other than the one CPU that sends the write data, when the verification circuit within the CPU performs the detection, the buffer store within the CPU A buffer invalidation method in a multi-CPU system, characterized in that data corresponding to the address information stored in the address information is invalidated.