JPS60124786A - Vector generating system - Google Patents

Vector generating system

Info

Publication number
JPS60124786A
JPS60124786A JP23401783A JP23401783A JPS60124786A JP S60124786 A JPS60124786 A JP S60124786A JP 23401783 A JP23401783 A JP 23401783A JP 23401783 A JP23401783 A JP 23401783A JP S60124786 A JPS60124786 A JP S60124786A
Authority
JP
Japan
Prior art keywords
vector
circuit
displacement
coordinates
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23401783A
Other languages
Japanese (ja)
Inventor
Hiroshi Takemoto
洋 竹本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23401783A priority Critical patent/JPS60124786A/en
Publication of JPS60124786A publication Critical patent/JPS60124786A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

Abstract

PURPOSE:To generate a rectangular vector in high speed by providing the 1st and 2nd vector generating circuits and a picture memory to generate coordinates of a point sequence constituting a side in the broadwise direction of a rectangular. CONSTITUTION:A start point (STX, STY) and a displacement (U, V) in the broad-wise direction are inputted to a vector generation circuit A to input a coordinate sequence shown in X marks of each picture element constituting the side in the broadwise direction to the next vector generating circuit B. The coordinate sequence and a displacement of the side of the vector in the lengthwise direction (DELTAx, DELTAy) are inputted to the circuit to output a coordinate sequence shown in marks ''O'' for the picture element constituting each part of the length and direction. Then the vector is expanded to a picture element memory C according to the output coordinate sequence of the circuit B.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、太さを有しないベクトルの発生回路を用いて
太さを有するベクトルを発生ずる方式に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for generating a vector having a thickness using a generating circuit for a vector having no thickness.

従来技術と問題点 図形などを画か一ロるのに用いられるハク1−ル発生回
路は始点座標と終点座標を与えられてそれらを結ぶ直線
を発生ずる、あるいは始点座標と該始点より終点までの
変位ΔX、Δyを与えられて該始点から該終点まで延び
る直線を発生する、等が主である。そして従来のベクト
ル発生回路は線幅が1画素の、つまり太さを有しないベ
クトルを発生ずるものか一般的であるから、それを用い
て矩形(太さを有するベクトル)を発生させるためには
、(11プログラムによって矩形の四辺を構成する点列
の座標を算出し、その矩形枠内で延びる水平あるいは垂
直ベクトルを多数発生させる方式や、(2)一旦、矩形
の四辺を書き込んでから、その矩形枠の内側を塗りつぶ
しプログラムを使って塗りつぶす方式をとるなどする必
要がある。しかしながらこれらの方法は、ベクトル発生
回路で発生ずるベクトルの本数が非常に多く、またアル
ゴリズムが複雑なためハードウェア化が困難である欠点
を有する。
Conventional technology and problem pointsA square generation circuit used to trace a figure is given the coordinates of a starting point and an end point and generates a straight line connecting them, or the coordinates of the starting point and the line from the starting point to the ending point. The main method is to generate a straight line extending from the starting point to the ending point given the displacements ΔX and Δy. Conventional vector generation circuits generally generate vectors with a line width of 1 pixel, that is, without thickness, so in order to generate a rectangle (vector with thickness) using it, (11) A method in which the coordinates of a sequence of points constituting the four sides of a rectangle are calculated by a program and a number of horizontal or vertical vectors extending within the rectangle are generated, (2) Once the four sides of the rectangle are written, It is necessary to use a method to fill in the inside of the rectangular frame using a fill program. However, these methods require a large number of vectors to be generated in the vector generation circuit, and the algorithms are complex, so it is difficult to implement them in hardware. It has the disadvantage of being difficult.

発明の目的 本発明は、通常のヘタトル発生回路へ入力するベクトル
・データとして、矩形(太さを有するベクトル)の太さ
方向の辺を構成する点列の座標を発生し、これを用いる
ことにより、矩形ベクトルの発生を高速に行なおうとす
るものである。
Purpose of the Invention The present invention generates the coordinates of a sequence of points forming the sides in the thickness direction of a rectangle (vector with thickness) as vector data input to a normal hetator generation circuit, and uses this to generate , which attempts to generate rectangular vectors at high speed.

発明の構成 本発明は、太さを有するベクトルの発生方式において、
該ベクトルの開始点と太さ方向の辺の変位を入力として
該太さ方向の辺を構成する画素の座標列を出力する第1
のベクトル発生回路と、該座標列および該ベクトルの長
さ方向の辺の変位を入力として該長さ方向の各部を構成
する画素の座標列を出力する第2のベクトル発生回路と
を備え、該第2のベクトル発生回路の出力座標列に従っ
て画像メモリに該ベクトルを展開することを特徴とする
が、以下図示の実施例を参照しながらこれを詳細に説明
する。
Structure of the Invention The present invention provides a method for generating a vector having a thickness.
A first input device that inputs the starting point of the vector and the displacement of the side in the thickness direction and outputs a coordinate string of pixels forming the side in the thickness direction.
a second vector generating circuit that inputs the coordinate string and the displacement of the sides in the longitudinal direction of the vector and outputs the coordinate string of pixels constituting each part in the longitudinal direction, The present invention is characterized in that the vector is developed in the image memory according to the output coordinate string of the second vector generation circuit, and this will be explained in detail below with reference to the illustrated embodiment.

発明の実施例 第1図は通常のベクトル発生回路へ入力するベクトルデ
ータの説明図である。ベクトルデータは開始点座標(S
TX、5TY)と変位(ΔX、Δy)を示すもので、こ
れに基いてヘクI−ル発生回路はベクトルを構成する各
々の画素の座標を次々と算出し、該当する画素値を特定
の値にする。ここで画素とは、2次元のアドレス(座標
と呼ぶ)を持った画像メモリを構成する単位であり、画
素値の種類には1ヒソ1−(0または1)、2ビツト(
0〜3)など種々のものがある。第1し1でX印は始点
、O印はヘタトルを構成する各画素であり、図では3つ
ずつ並んで有段構造になっているが、これは量子化によ
るものである。即ぢ周知のようにベクトルつまり直線は
y = a X 十すの1次式で表わされ、a−Δy/
ΔXであるが、ベクトル発生はXを単位量ずつ大にし、
その各Xに対するyを旧算し、これらのx、yの組が各
画素の座標となるが、メモリに格納する等の関係でyも
単位量の整数倍である必要があり、そのような値になら
なければ切捨、切上げ等する。図の有段形状はこの量子
化の結果性したものである。
Embodiment of the Invention FIG. 1 is an explanatory diagram of vector data input to a normal vector generation circuit. The vector data is the starting point coordinates (S
TX, 5TY) and displacement (ΔX, Δy).Based on this, the hexagonal generation circuit successively calculates the coordinates of each pixel that makes up the vector, and converts the corresponding pixel value to a specific value. Make it. Here, a pixel is a unit that constitutes an image memory having a two-dimensional address (referred to as coordinates), and the types of pixel values include 1 bit (0 or 1), 2 bits (
There are various types such as 0 to 3). In the first column, the X mark is the starting point, and the O marks are each pixel forming the hetator. In the figure, three pixels are lined up in rows to form a stepped structure, but this is due to quantization. As is well known, a vector, or a straight line, is expressed by the linear equation y = a
ΔX, but vector generation increases X by a unit amount,
The y for each X is calculated backwards, and the pair of x and y becomes the coordinates of each pixel, but y also needs to be an integral multiple of the unit amount due to storage in memory, etc. If the value does not reach the desired value, round down or round up. The stepped shape in the figure is the result of this quantization.

第1図で説明したベクトルは太さを有しないものである
から、太ざをつけるために本発明では開始点座標(ST
X、5TY)から太さ方向に広がる点列をめて上記のベ
クトル発生回路へ入力する。第2図はこの説明図である
。同図のベクトルを発生するためのデータは開始点座標
(STX。
Since the vector explained in FIG. 1 does not have a thickness, the present invention uses the starting point coordinates (ST
A series of points extending in the thickness direction from X, 5TY) is collected and input to the vector generation circuit described above. FIG. 2 is an explanatory diagram of this. The data for generating the vector in the figure is the starting point coordinate (STX).

5TY)と長さ方向の変位(ΔX、Δy)、それとして
められる。また太さ方向の辺(×印の集合として示す)
も本発明ではベクトルと考え、ベクトル発生回路で発生
させる。この太さベクトルは始点を同じSTX、STY
、変位はu、vとすることができ、この変位(u、v)
は U−一Δy°w/β ・・・・・・(2)■=Δx−w
/β ・・・・・・(3)としてめられる。これらを予
備段階で算出して初段のベクトル発生回路から(STX
、5TY)を基準として太さ方向の辺を構成する座標列
を発生させ、この座標列を各ベクトルの始点群として次
段のベクトル発生回路に与え、長さ方向に延びる多数の
ムク1−ルの座標列を発生させる。第2図の○印が長さ
方向に延びる画素である。
5TY) and the longitudinal displacement (ΔX, Δy). Also, the side in the thickness direction (shown as a collection of x marks)
In the present invention, the vector is also considered to be a vector, and is generated by a vector generation circuit. This thickness vector has a starting point of the same STX, STY
, the displacement can be u, v, and this displacement (u, v)
is U-1 Δy°w/β ・・・・・・(2)■=Δx-w
/β ・・・・・・(3) These are calculated in the preliminary stage and the first stage vector generation circuit (STX
. generates a coordinate sequence of The circles in FIG. 2 are pixels extending in the length direction.

第3図は本発明の一実施例を示すブロック図で、Aは初
段のヘクI−ル発生回路、Bは次段のベクトル発生回路
、Cは画像メモリである。動作は次の通りである。まず
、開始点(STX、5TY)と太さ方向の変位(u、v
)をベタ1−ル発生回路Aに入力して、太さ方向の辺を
構成する各画素(第2図の×印)の座標を次々に出力す
る。得られた座標列は次段のベクトル発生回路Bへの人
力データ(開始点データ)となる。但し座標は1つずつ
与え、当該座標を始点とするベクI−ルが発生し終った
ら次の座標を与えて次のベクトルを発生さゼ、以下同様
にする。このベクトル発生回173 Bの変位データと
して(ΔX、Δy)を入力すると、出力座標列は第2図
の○印の画素に相当するので、これに従って画像メモリ
Cへ書き込みを行うと該メモリ内には第2図の矩形が展
開される(書き込みを実行する回路は省いている)。
FIG. 3 is a block diagram showing an embodiment of the present invention, where A is a first-stage hexagonal generating circuit, B is a next-stage vector generating circuit, and C is an image memory. The operation is as follows. First, the starting point (STX, 5TY) and the displacement in the thickness direction (u, v
) is input to the solid circle generation circuit A, and the coordinates of each pixel (marked with an x in FIG. 2) constituting the side in the thickness direction are output one after another. The obtained coordinate string becomes the manual data (starting point data) for the vector generation circuit B at the next stage. However, the coordinates are given one by one, and when the vectors starting from the coordinates have been generated, the next coordinates are given to generate the next vector, and so on. When (ΔX, Δy) is input as the displacement data of this vector generation time 173B, the output coordinate string corresponds to the pixel marked with ○ in Figure 2, so if you write to the image memory C according to this, the data will be stored in the memory. The rectangle shown in FIG. 2 is expanded (the circuit that executes writing is omitted).

なお、ベクトル発生回路Aが出力する座標列の要素であ
る各座標どうしは4方向連結になっている。第4図(b
lはその説明図で、この図の○印の画素の座標とΔ印の
座標の関係を互いに4方向連結であるという。一方、ベ
クトル発生回路Bが出力する座標列の要素である座標ど
うしは8方向連結になっている。第4図(alはその説
明図で、この図の○印の画素の座標とΔ印の座標の関係
を互いに8方向連結であるという。図示のように4方向
連結では○部画素に対する△部画素が上、下、左、右の
いずれかにあれば両画素は連結しているとするが、△部
画素が斜めに上、下又は左、右にあるなら両画素は連結
していないとする。これに対して8方向連結では斜めに
ある場合も連結しているとする。具体例でいうと第1図
では斜めの関係の○印2画素があり、これで直線をなす
(連結している)とするから8方向連結法を採用してい
る。
Note that the coordinates that are elements of the coordinate string output by the vector generation circuit A are connected in four directions. Figure 4 (b
1 is an explanatory diagram thereof, and the relationship between the coordinates of pixels marked with ○ and the coordinates of pixels marked with Δ in this diagram is said to be four-way connected. On the other hand, the coordinates that are the elements of the coordinate string output by the vector generation circuit B are connected in eight directions. Figure 4 (Al is an explanatory diagram thereof; the relationship between the coordinates of pixels marked with ○ and the coordinates of pixels marked with Δ in this figure is said to be 8-way connection. As shown in the figure, in 4-way connection, △ part with respect to ○ part pixel If the pixel is at the top, bottom, left, or right, the two pixels are considered connected, but if the △ pixel is diagonally above, bottom, left, or right, the pixels are not connected. On the other hand, in 8-way connection, it is assumed that they are connected even if they are diagonal.To give a specific example, in Figure 1, there are two pixels marked with ○ in a diagonal relationship, and these form a straight line (not connected). ), the 8-way concatenation method is adopted.

これに対して第2図の×部画素は斜めに連結しているも
のはなく、1画素付加されて上下左右関係の連結となっ
ているから4方向連結法をとっている。この第2図の○
部画素は8方向連結である。
On the other hand, the pixels of the x section in FIG. 2 are not connected diagonally, but one pixel is added and are connected vertically and horizontally, so a four-way connection method is used. ○ in this figure 2
The partial pixels are connected in 8 directions.

このように連結形態の異なるベクトル発生回路を用いる
理由は、A、B共に斜め連結可能な8方向連結型のベク
トル発生回路を用いると、第5図に示すように不連続点
(隙間)Gが発生ずるからである。これを防ぐにはA、
Bいずれかが4方向連結であればよい。例えば第5図の
例ではO部画素が4方向連結をとるなら隙間Gは発生せ
ず、また×部画素が4方向連結をとって点線×印が付加
されると、これより延びるムク1−ル(点線0群で示す
)が隙間を埋め、いずれの場合も隙間発生を回避できる
。塗りつぶし処理では、隙間発生は不都合であるが、市
ね塗りは黙認できるから、ベクトル発生回路A、Bはい
ずれも4方向連結型であってもよい。
The reason why vector generation circuits with different connection configurations are used is that if an 8-way connection type vector generation circuit in which both A and B can be diagonally connected is used, the discontinuity point (gap) G is created as shown in Fig. 5. This is because it occurs inadvertently. To prevent this, A.
It is sufficient if either B is connected in four directions. For example, in the example shown in FIG. 5, if the pixels in the O area are connected in four directions, no gap G will occur, and if the pixels in the (indicated by the dotted line 0 group) fills the gap, and in either case, the generation of the gap can be avoided. In the filling process, the generation of gaps is inconvenient, but since the filling process can be tolerated, vector generation circuits A and B may both be of the four-way connection type.

発明の効果 以上述べたように本発明によれば、ムク1−ル発生 ゛
回路へ入力するヘクl−ルデータが少ないので、矩形発
生が高速化できる。また、従来のベクトル発生回路の機
能をそのまま利用できるので、装置としても安価に構成
できる利点がある。
Effects of the Invention As described above, according to the present invention, since less square data is input to the square generation circuit, rectangle generation can be made faster. Furthermore, since the functions of the conventional vector generation circuit can be used as is, there is an advantage that the device can be constructed at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は通常のヘタトル発生回路によるベクトル発生の
説明図、−第2図は本発明の原理説明図、第3図は本発
明の一実施例を示すプロ・ツク図、第4図はベクトル発
生回路の種類の説明図、第5図は8方向連結型のベクト
ル発生回路だけを用いた場合に生ずる不連続点の説明図
である。 図中、A、Bはベクトル発生回路、Cは画像メモリであ
る。 出願人 富士通株式会社 代理人弁理士 青 柳 稔
Fig. 1 is an explanatory diagram of vector generation by a normal hetator generation circuit, - Fig. 2 is an explanatory diagram of the principle of the present invention, Fig. 3 is a process diagram showing an embodiment of the present invention, and Fig. 4 is a vector diagram. FIG. 5 is an explanatory diagram of types of generation circuits, and is an explanatory diagram of discontinuities that occur when only eight-way connected vector generation circuits are used. In the figure, A and B are vector generation circuits, and C is an image memory. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (2)

【特許請求の範囲】[Claims] (1)太さを有するベクトルの発生方式において、該ベ
クトルの開始点と太さ方向の辺の変位を入力として該太
さ方向の辺を構成する画素の座標列を出力する第1のハ
ク1−ル発生回路と、該座標列および該ヘクl−ルの長
さ方向の辺の変位を入力として該長さ方向の各部を構成
する画素の座標列を出力する第2のベクトル発生回路と
を備え、該第2のベクトル発生回路の出力座標列に従っ
て画像メモリに該ベクトルを展開することを特徴とする
ベクトル発生方式。
(1) In a method of generating a vector having a thickness, the first vector 1 receives the starting point of the vector and the displacement of the side in the thickness direction as input, and outputs a coordinate string of pixels constituting the side in the thickness direction. - a second vector generating circuit that inputs the coordinate string and the displacement of the side in the longitudinal direction of the heckle and outputs a coordinate string of pixels constituting each part in the longitudinal direction. A vector generation method comprising: expanding the vector in an image memory according to an output coordinate string of the second vector generation circuit.
(2)第1および第2のハク1−ル発生回路の少くとも
一方は4方向連結型であることを特徴とする特許請求の
範囲第1項記載のベクトル発生方式。
(2) The vector generation system according to claim 1, wherein at least one of the first and second wave generator circuits is of a four-way connection type.
JP23401783A 1983-12-12 1983-12-12 Vector generating system Pending JPS60124786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23401783A JPS60124786A (en) 1983-12-12 1983-12-12 Vector generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23401783A JPS60124786A (en) 1983-12-12 1983-12-12 Vector generating system

Publications (1)

Publication Number Publication Date
JPS60124786A true JPS60124786A (en) 1985-07-03

Family

ID=16964248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23401783A Pending JPS60124786A (en) 1983-12-12 1983-12-12 Vector generating system

Country Status (1)

Country Link
JP (1) JPS60124786A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106084A (en) * 1986-10-23 1988-05-11 Nec Corp Graphic drawing system
JPH0266684A (en) * 1988-08-31 1990-03-06 Nec Corp Information processor
JPH0293877A (en) * 1988-09-30 1990-04-04 Nec Corp Information processor
JPH02165389A (en) * 1988-12-20 1990-06-26 Ricoh Co Ltd Information processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106084A (en) * 1986-10-23 1988-05-11 Nec Corp Graphic drawing system
JPH0266684A (en) * 1988-08-31 1990-03-06 Nec Corp Information processor
JPH0293877A (en) * 1988-09-30 1990-04-04 Nec Corp Information processor
JPH02165389A (en) * 1988-12-20 1990-06-26 Ricoh Co Ltd Information processor

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