JPS60123918A - Reference voltage generating device - Google Patents

Abstract

PURPOSE:To obtain an optical output voltage, by optionally setting the drain current and gate length of an MOS transistor by utilizing the voltage difference between the gate and source of the transistor. CONSTITUTION:An optional output voltage is obtained by optionally setting the value of a constant-current source I0 by utilizing the voltage difference between the gate and source of a P-channel N<+> gate MOS transistor and P-channel N<-> gate MOS transistor. This output voltage is obtained by setting the gate length or drain current to an optional value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a reference voltage generating device.

[Background of the invention]

Conventionally, as a reference power source, a reverse voltage (Zener voltage) Vz of a PN junction diode and an insulated gate field effect transistor 2 are used as a reference power source.
For example, the threshold voltage V r it of a transistor is used. Furthermore, there is a need for an insulated gate field effect transistor structure in which a high voltage is equal to the bandgap. However, the output voltages of these systems are each fixed values, and it is not possible to obtain an arbitrary output voltage.

[Purpose of the invention]

An object of the present invention is to provide a reference voltage generator that can set an arbitrary output voltage.

An object of the present invention is to provide a high-performance reference voltage generator using a general-purpose process, using positive metal as the threshold of a MOS transistor, without degrading the performance of the circuit part.

[Summary of the invention]

The key point of the present invention is to utilize the difference in voltage between the gate and source of an N+ gate or P+ gate MOS transistor and a low impurity concentration gate MOS transistor in a MOS transistor, and set the drain current and gate length to a pressure point. Especially, any output tJ! The object of the present invention is to construct a four-screw pressure generating device that obtains pressure.

[Embodiments of the invention] Examples of the present invention will be described below.

FIG. 1(a) shows a planar groove-m of a P-channel MO8) transistor. The MOS transistor 401 has an N- region doped with phosphorus as an N-type impurity at a low temperature in the gate layer 101, and a P-type impurity boron of the same type as the drain 104 and source 105 in the gate layer 102 so as to recess the N- region. is a MOS transistor (hereinafter abbreviated as N-MOS transistor) consisting of a gate layer doped to a high dK.

402 MOS) transistor has N in the gate layer 103.
This is an N (Ga) MOS) transistor heavily doped with phosphorous type impurity. Note that 106 is a source and drain/contact hole, 202 is a source and drain extraction kt electrode, and 201 is a gaiter extraction At'g electrode. be.

Here, the impurity tolerance of the gate layer 101 of the N-gate MO8) transistor 401 and the N1-gate MOS transistor 4
The difference in impurity vIJm degree of gate layer 103 of 02 is 10'
cm-” or more.

FIG. 1(b) is a schematic representation of the cross-sectional structure of FIG. 1(a). An N-gate MOS transistor 401 and an N+-gate MOS transistor 40 are disposed on an Nm substrate 301.
2 is formed. 107 is a gate oxide film.

N-Gate MO8) When a voltage is applied to the gate of the transistor, a voltage is applied to the N- region via the P+ region, and a depletion layer spreads from the P+ region to the N- region. The extent of the depletion layer, X, in the case of a step junction, is expressed as:

Cocoa, ε. :True 2(')u'fJL rate (8,85X1
0-”F/z) 68th section, silicon relative capacity 114 (12
)q, 1 child's load blocking (1,6X10"C) ■: Gate applied voltage (V) ND: Donor unpolished concentration (cm -") NA,
Accessor impurity concentration Ccm-'')φ Two spreading magnetic potentials: Boltzmann's constant 111: Carry P yield of A-type semi-integrated body.

In Figure 2, No = 10"cm-" r NA = 1
This shows the gate applied voltage and the spread of the depletion layer in the gate layer when the gate voltage is 020ty;r''.As the gate applied voltage increases, the depletion layer spread also increases. As the depletion layer expands, the channel length L1 increases by an amount ΔL, (ΔL5 is a function of the gate applied voltage v1, ΔL
The effective channel length is reduced by t = f (Vas). The relationship between the channel length and the threshold voltage Vry+ is expressed as shown in FIG. 3, and as the channel length L1 becomes smaller, the threshold voltage VTH also tends to become smaller.

FIG. 4 shows the Vas-In characteristics of a MOS transistor. TN+ is an N+ Doug-MOS transistor (Fig.
02) TN- is a MOS without a junction in the gate layer)
transistor, TNt- is a MOS with a junction in the gate layer)
Each of the transistors (FIG. 1 401) is equal. M.O.S.
) Both the transistor TN+ and the MOS transistor TNI- are MOS transistors because there is no spread of depletion layer in the gate layer.) The relational expressions between the voltage and current of the transistor are as follows, and β is the Rayaner conductance constant.408)
Ransistor l1lN4 and MO8? Both Ranjista provinces are equal. Therefore, with the same drain current, MO8 transistor T
Threshold voltage difference between N'' and TNI- (VTRNl-VTHI
4") is constant. However, 4 in the case of l1lN, -
The pressure-da equation is as shown in equation (3)', and the effective channel length becomes smaller by ΔL9 due to the expansion of the depletion layer. As shown in Figure 2, as Vas increases, ΔL also becomes sharper (L, -Δ
bt) becomes more elaborate, the threshold screw pressure becomes smaller as shown in Figure 3. Therefore, the MOS characteristics of TN2- vary as shown by the broken line with respect to transistor TNI-. Therefore, by using the voltage difference between the gate and source of the MOS):7 transistors 1'N+ and 1'Ni, any desired output voltage can be obtained by arbitrarily setting the drain α current as shown in FIG.

FIG. 5 shows a circuit that utilizes the voltage difference between the gate and source of two 1VIO8) transistors in the P-channel MO8) transistor configuration of FIG. 1 and extracts the differential voltage.

■, is a constant current source, TN◆, TN2- are MOSFETs with different threshold voltages IN+, VτHN2- and channel conductances βN and β-, and each gate-source voltage is VN” , V)J2-, then VN2-=VTIIN2-+m (7) The gate-to-north voltage of both MOS) transistors can be extracted.

A sufficiently large resistance may be applied to the constant current source, and as long as the characteristics are the same, diffused resistance, polycrystalline Si resistance,
Resistors made by ion implantation, MOS) transistors can be used.

FIG. 6 shows a P-channel N+gate MOS transistor and a P-channel N-gate MOS transistor in the circuit configuration of FIG.
Measurements and measurements of transistor gate-source distance 4Hi, gate length a, and drain current In are not shown. The gate-source voltage difference becomes smaller as the drain current becomes smaller. This is due to the spread 9 of the depletion layer of the N-gate MO transistor 8) and reflects the MOS characteristics shown in FIG. The dependence of the gate-source voltage difference on the gate length when viewed from the same drain-current is L, (40
The effect is large at μm, and becomes almost constant at L, )40 μm. This is because the ratio of the spread of the depletion layer to the gate length of the N-gate MOS transistor is large in a portion where the gate length is small, and therefore there is a large dependence on the gate length.

However, as the gate length increases, the effect of the spread of nitrogen depletion j- on the gate length becomes smaller, and this is thought to be because the effect is no greater than the spread of the depletion layer to a certain extent.

Based on the above, using the voltage difference between the gate and source of the N+ gate MO8) transistor and the N-gate MOS transistor of the P channel MOS transistor, the gate length and drain DC can be set arbitrarily by using the voltage difference between the gate and source. The desired output voltage can be obtained by adjusting the output voltage.

In the first embodiment of the present invention, the circuit configuration shown in FIG.
P-channel N1-gate MO8) Constant current source I using the gate-source voltage difference between the transistor and the P-channel N-gate MOS transistor.

An arbitrary output voltage can be obtained by setting the current to an arbitrary value.

In the second embodiment of the present invention, the circuit configuration shown in FIG.
Using the voltage difference between the gate and source of the P-channel N-gate MO8) transistor and the P-channel N-gate MO8) transistor, set the gate length to an arbitrary value to create a constant current source. An arbitrary output voltage can be obtained by setting the current to an arbitrary value.

Above, P channel N-gate MO8, 97 resistor and N
1 goo) N08) Gate of transistor, Nose l & 01
A reference voltage generator using a pressure difference can obtain any output voltage by arbitrarily setting the gate length and drain/-flow. However, since the output voltage is small, the N″ gate Mo
ST9 transistor N + gate 1-N08) When using one-stage closed gate and source crimping or more, the output voltage is multiplied by 0.

FIG. 7 is a third embodiment of the present invention, and shows the basic concept of n-fold multiplication using a two-layer case as an example.

1 is the power supply anode end of the reference voltage generation circuit, 10 is the source end.
1ttt source connected to anode end 1/) 40S transistor to P channel, 11 connected to source iP channel MO8) drain end of transistor lO, gate and drain yt
P channel N+ connected to Mτ and connecting the substrate to the source end
12 is a P-channel MO8) transistor whose source is connected to the drain end of the transistor 11, the gate and the drain end are connected to the electric gap extreme, and the P-channel MO8) transistor is connected to the substrate gold source end. N+Goo) MO8) transistor, 20 has its source end connected to the power supply anode end 1, and its gate end connected to the P channel Most? P-channel MO8) transistor whose source is connected to the gate of the transistor 10; 21 is a P-channel N-gate whose source is connected to the drain end of the uMO8) transistor 10, whose gate drain end is connected and whose substrate is connected to the source end. The MO8 transistor 22 is a P-channel N-gate MO whose source is connected to the drain end of the P-channel MOS transistor 21, whose gate and drain 4 are connected to the power source anode and to the substrate gold source end.
8) U/I'm a jista.

In the configuration of io, ii, tz, P channel/1/MO8) drain end of synristor 10 and P channel A/N+gate MO
If the voltage between the intersection of the drain/end of the transistor 11 and the power source anode is vl, then the current flowing through the P-channel N"gate MO8) synristor 12 is β. P: Channel of the P-channel MOS transistor Conductance constant β1: P channel, N + gate MOS transistor 9/resistor size ratio (channel width/channel length) VrnN”: P channel k N + gate MO8) 2
The threshold 1 voltage of the transistor is V, which is the P channel N1 gate voltage. On the other hand, the P-channel N-gate MO8 transistor 22e flows as follows: 1z=-βaP' β22 ((Vl -Vd■N
− J −VtnN− ]”−λβ.P−At (Vl
2VtI%m-)" Here, β, 2; P channel MO8) Dimensional ratio of transistor [Channel width/Channel length (Lg-ΔL,)] Vrmw-: P f'r NekN- MO S )
7 7 transistor threshold voltage Vl: P channel "N-MOS) 7 Y series 22 gate-source direct voltage. P channel/I/MO8) transistors 10, 20
Since the gate voltages of 20 and 2 are the same, the currents of 2 and 2 are the same.

(s), (9) to v,,V. N0
Geito MO8 Tora/Jista 11.

12 and N-gate MO8) U7 The voltage difference Vt Vs between the gate and the gate of resistor 21.22 can produce an output voltage twice that of the single configuration obtained in (6) and (7). .

FIG. 8 shows a fourth embodiment of the present invention in which a diode is connected between P-channel N4 gate MOS transistors 11 and 12 in the same manner as in FIG.
When n + gate MOS transistors are connected and a P channel N-gate MO8) is diode-connected between P channel N-gate MOS transistors 21 and 22, and n i' transistors are read, a P channel N'' gate is formed. M.O.S.
Transistor 12 and P channel N-gate MO8) U/
Raster 22 gate-source voltage V1-*■! The difference in voltage between the gate and source of the N+ gate MOS transistor and the N- gate MO8) is expressed as V7-V,' = n (-doubling configuration gate-source voltage difference).
−n times.

Therefore, the reference voltage t-N+gate MO8) transistor and N-gate MO8) gate or source of transistor +dj
The method shown in FIG. 8 can be used when the pressure difference is multiplied by the indigo number.

These real examples are P-channel MO8)? This method is related to the N+ gate MOS controller/distor and N-goo MOB) Lanozista, but this method is applicable to P1 game)
The same applies to MOB) transistors and N-Ge-1M08) transistors.

In addition, the above method can be applied to a P-gate MOS transistor of an n-channel MO8) transistor, an N+ gate MO8) transistor, and a P-gate MOS transistor, instead of a P-channel transistor.
Of course, it can also be applied to S transistors and P+GEGA MO8) transistors.

The above method is for the PN junction of the gate layer, but
In the case of (ifh -LOW Junction of the gate layer), the depletion layer spreads toward the lower concentration side, and the effect is smaller than that of the method using a PN junction, but the method can be similarly applied.

According to the embodiment of the present invention, by arbitrarily setting the gate length and drain current of the transistor (MOB), it is possible to obtain an arbitrary output direct voltage and an output that is an integral multiple of the gate-source pressure difference, providing a high degree of design freedom. , it is possible to expand the reference appointment application within the IC.

〔Effect of the invention〕

According to the present invention, any reference pressure can be set in a normal process.

[Brief explanation of the drawing]

Figure 1 shows a plan view (a) and a top view (b) of an N+ gate MOS transistor and a low voltage N-gate MOS transistor, and Figure 2 shows the gate applied voltage and gate layer of the N-gate MOS transistor. Figure 3 showing the relationship between the depletion layers of
The figure shows the relationship between the channel length of a MOS transistor and the threshold 4 voltage.
,, □-〇Mis In custom-made diagram, Figure 5 shows the first implementation of the present invention in the 7th stage to extract the voltage difference between the gate and source of the N+ gate MOS transistor and the N- gate MOS transistor. Example circuit diagram, Figure 6 shows P channel N
+ Goo) MOB) Transistor and N-gate MOB) A diagram of the second embodiment of the present invention showing the relationship between the gate-source voltage difference, gate length, and drain current of a transistor. Figure 7 is the third embodiment of the present invention. FIG. 8 is a circuit diagram showing the basic concept of n-fold multiplication in the embodiment of the present invention, and is a circuit diagram for n-fold multiplication in the same manner as in FIG. 7 of the fourth embodiment of the present invention. . 10...P channel MO8) transistor, 11...
P81 diagram (a) (b) Certain 2 6 0.5 t, 0 14 20 Ke°-to Tl 710 1λFF-<V no θ + Manel length 14 C1”') No. 42 Moray 5 Prisoner 6 Eye Part length (PQv() $q Figure o30 Temachi 3' Temai 3 07-

Claims (1)

[Scope of Claims] 1. A reference voltage generating device that utilizes a voltage difference between the gate and source of two MOS transistors, and is characterized in that an arbitrary output pressure can be obtained. 2. In claim 1, by controlling the spread of a depletion layer in the gate layer with the drain current of the MOS transistor, the effective channel length of the MO8) transistor can be arbitrarily changed, and the output voltage can be arbitrarily set. A reference voltage generator characterized by adding. The reference voltage generator according to claim 1, characterized in that an arbitrary output voltage can be obtained by arbitrarily setting a gate length. 4. In claim 2 or 3, the former M
A reference voltage generator t characterized by comprising means for fully amplifying Q-voltage positive pressure. 5. The reference voltage generating device according to claim 4, wherein the means for amplifying the voltage is means for multiplying the voltage by an integral number. 6. In claim ig1, the two MOs
S) The gate layer impurity concentration of the transistor is 10'crr&
- A reference voltage generator characterized in that it has a voltage equal to or greater than 1.