JPS60123125A - Phase corrected filter circuit - Google Patents

Abstract

PURPOSE:To correct excess filter characteristics due to a floating capacity or the like by connecting a phase correcting resistance in series to a filter capacitor in a circuit where the filter capacitor is connected to a pair of differentially coupled active elements. CONSTITUTION:Transistors (TRs) Q1 and Q2 are differentially coupled, and a filter capacitor C is connected between the collector of the TRQ2 and the earth. An input signal Vi is given to the base of the TRQ1, and a filter output signal V0 is led out from the collector of the TRQ2 through a buffer TRQ4 of a high input impedance. In the filter circuit constituted in this manner, a phase correcting resistance RS is connected in series to the capacitor C. This resistance RS corrects excess filter characteristics which are caused by influences of the junction capacity of TRs and the floating capacity of electrode leads and are added in case of phase delay.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in a filter circuit in which a filter capacitor is coupled to one output electrode of a pair of differentially coupled active elements.

Background technology and its problems FIG. 1 shows a conventional filter (integrator) circuit.

This circuit basically consists of a differential connection between transistors Ql and Q2 and a connection between the collector ground of Q2.
-) A Self-written d> Kichi Su1 - Utaoka 1 mutual integral (low-pass) characteristic has been obtained. The input signal Vi is the transistor Q
1, and the integral (low-pass) output signal V
o is derived from the collector of transistor Q2 via a high input impedance buffer transistor Q4. Transistor Q4 constitutes an emitter follower together with current source Q6, and also constitutes a negative feedback path to transistor Q2, thereby adjusting the integrator Kane to pA.

A current source Q5 (current value generator) is coupled to the common emitter of the differential pair Q1 and Q2, and a current I/2 is connected to the collector of Q2.
A current source load is connected to supply the current.

Since the impedance of this current source load in the input signal band seen from the collector of transistor Q2 is considered to be infinite, the emitter resistance re('-, 2
6/Io (mA); Ic is between the collector and ground) and the capacitor C constitute a first-order low-pass filter.

However, at low frequencies such as the audio band, the low-pass characteristics of PJ + Desir (transfer function 11) as shown in Figure 2.
However, at high frequencies such as the video band, Ql is affected by the base-emitter capacitance of transistors Q1 and Q2.

A lζ phase lag occurs between the base voltage of Q2 and the collector current of Q2, making it impossible to obtain perfect integral characteristics.

That is, as shown in FIG. 3, an unnecessary low-pass characteristic occurs.If this phase rotation becomes large, there is a possibility of oscillation when a filter with a high Q is constructed.

OBJECT OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and its object is to provide a filter circuit that can compensate for phase lag with a simple configuration and obtain desired transfer characteristics even in a high frequency range. It is to provide.

Summary of the Invention The filter circuit of the present invention couples a filter capacitor to one output electrode of a pair of differentially coupled active elements,
This device is designed to obtain an output obtained by high-frequency processing of an input signal, and is characterized in that a phase correction resistor is coupled in series with the capacitor. With this configuration, it is possible to cancel the phase delay due to the capacitance within the active capacitor and obtain correct integration characteristics.

Example The present invention will be explained below based on examples.

FIG. 4 is a principle diagram of an integrator showing an embodiment of the filter circuit of the present invention, and the same parts as in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 4, a phase correction resistor R5 is connected in series with the integrating capacitor C shown in FIG. 1 so that the phase shift is canceled.

FIG. 5 is a price model of the transistors Q1 and Q2 shown in FIG. In FIG. 5, the input Vi is given to the base B of ]・Larrangestaff, and the base B of the transistor Q1
Consider the case where is grounded. In this case, the signal current i of transistor Q2. is・−α0 1cm yB・□ “e Here, α. is the current amplification rate, and re is the emitter resistance hvB
'E is the voltage between B'E in Figure 5, Ce6 (current source Q5
The collector capacitance of Q2 and the collector capacitance of transistor Q2 are ignored. From the above equation, the frequency characteristic of 1° on the collector signal side matches that of VB'H.

Figure 6 shows that I is several tens of μA compared to the base-emitter of transistor Q2! : Since the amount is negligible,
The voltage at B' can be approximated as shown in the equivalent circuit of FIG. Therefore, . Therefore, the collector voltage Vo of transistor Q2 is as follows. In other words, low pass (phase delay) due to Ce in the denominator
Since the element appears, if the value for the phase correction resistor in series with the integrating capacitor is selected so that , the above equation becomes , and an ideal integrator is obtained.

The actual value of the correction resistor R5 is Cc, which was ignored in the above explanation.
%Ccs is also taken into consideration, and transistors Q1, Q
Although it differs slightly depending on the characteristics of No. 2, it is approximately several tens of ohms. Creating this resistance value within an IC requires a relatively large area, and also requires devising a manufacturing process. Therefore, Figure 8,
As shown in FIG. 9, the shape of the integral capacitor C connected in series with FLs is devised, and R5 is inserted in series with the capacitor under equal constraints.

FIG. 8 is a cross-sectional view of the main part of the integrating capacitor portion of the IC, and FIGS. 9A to 9C show various forms of the planar shape of FIG. 8. As shown in FIG. 8, the integrating capacitor C has a three-layer structure consisting of an aluminum electrode (1) on the surface of the IC, a dielectric layer (2) such as a materide film, and an N+7i1 (3). The resistive layer (3) is diffused with a relatively high concentration and has a relatively low resistivity ρ. This N'' layer (3) can be used as a diffused resistance layer to insert a correction resistor Rs in series to the integrating capacitor C.
Figure A shows the planar shape of the capacitor when 1 (5) is relatively large.
The width is increased and the length is shortened. In Figure 9C,
A relatively large ratio is obtained by partially narrowing a part of the longitudinal direction of the N'' layer (3) in the width direction.

FIG. 10 is a circuit diagram of a trap filter to which the present invention is applied, and has a configuration known as a Pyford circuit. This filter circuit has two stages of integrators connected together, and the first integrator is composed of a differential pair of transistors Q1 and Q2 and a capacitor C1 at the collector of Q2, and a transistor Q4 receives the output of this integrator. ,Q7
A second integrator is constituted by the capacitor C2 at the collector of the differential pair Q7. The output of the second stage integrator is derived as an output vo via an emitter follower consisting of a transistor Q8 and a current source Q9.

Also, this transistor Q8 serves as a transistor,
The phase delay is compensated.

As shown in Figure 10, input Vi is applied to terminal TI (Q1 base) and T6 (one end of capacitor C2), and terminal 'I'
2 (one end of capacitor C1) is grounded, it becomes a trap filter. Further, when input is applied to the terminals 1 and T2 and the terminal T6 is grounded, a low-pass+band-pass characteristic is exhibited. By inputting to terminal T1 and grounding the others, it becomes a second-order low-pass filter, and by inputting to terminals 1 and 2 and grounding the others, a bandpass characteristic is obtained, and by inputting to terminal T6 and grounding the others, it is bypassed. characteristics are obtained.

Effects of the Invention As described above, the present invention provides a filter circuit in which a filter capacitor is coupled to one output electrode of a pair of differentially coupled active elements to obtain desired filter characteristics. When used in a high frequency range, the extra filter (low-pass) characteristics that are added when there is a phase lag caused by the junction capacitance of the active element or the stray capacitance of the electrode lead can be corrected. I can do this. Therefore, a filter circuit having a desired ideal transfer characteristic can be obtained with a simple configuration.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional filter circuit, Figure 2 is a transfer function block diagram when ideal integral characteristics are obtained, and Figure 6 is a block diagram of a transfer function when ideal integral characteristics are obtained.
The figure is a transfer function block diagram that includes unnecessary low-pass components that are added when there is a phase delay caused by the junction capacitance of the active element and the stray capacitance of the electrode leads. Figure 4 is an integrator circuit showing one embodiment of the present invention. Figure 5 is a circuit diagram of an equivalent model of the transistor in Figure 4, Figure 6 is a circuit diagram of an equivalent model of the base-emitter of transistor Q2 in Figure 4, and Figure 7 is an approximate equivalent of Figure 6. 8 is a cross-sectional view of the IC in the capacitor portion of FIG. 4, FIGS. 9A and C are plan views showing various forms of the capacitor electrode in FIG. 8, and FIG. 10 is a diagram of the filter circuit of the present invention. It is. In addition, in the symbols used in the drawings, (1)......■1 pole (2)...
・・・・・・・・・Visitor layer (3)・・・・・・・・・
...N+ layer Q1, Q2...Differential transistor pair Q3...Current source transistor Q5
・・・・・・・・・・・・Current source C・・・・・・・・・・・・Filter capacitor
・・・・・・・・・・・・Phase correction resistor Vi・・・・・・
. . . Input signal vo . . . Output signal. Agent Masaru Ueya Yoshio Tsuneko Toshiki Sugiura

Claims (1)

[Claims] a differentially coupled active element pair, a current source coupled to the differential coupling point, a current source load coupled to one output electrode of the active element pair, and a filter capacitor coupled to the output electrode. and a phase correction resistor coupled in series with the filter capacitor.