JPS60121822A - Counter circuit - Google Patents

Abstract

PURPOSE:To obtain a counter circuit which does not require complicate control by connecting plural basic units each consisting of a transfer gate MOS switch controlled with two phase clocks which never overlap each other in the same period, inverter, and a capacitor. CONSTITUTION:The transfer gate switch SW formed by connecting an n channel CHMOS transistor Tr1 and a pCHMOSTr2 in parallel and the SW consisting of an nMOSTr3 and a pMOSTr4 are connected in series, and the inverter consisting of an nMOSTr5 and a pMOSTr6 is connected thereto; and capacitors C1 and C2 are connected to the connection point of each SW and the inverter, and clock signals phi1 and -phi1, and phi2 and -phi2 are applied to gates of respective SWs to constitute a basic unit 10. When frequencies of the clocks phi2 and phi2 are both denoted as (f), the basic unit 10 has delay time with a time constant C2/fC1. Plural basic units 10 are connected in series and the final stage output is inputted to the 1st stage to obtain a stable counter circuit which counts pulses with a signal period of generate a pulse with a long period and is not influenced by the manufacture process.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a counter circuit that counts short-period pulses and generates longer-period pulses, and is particularly applicable to electrically erasable EEPROMs. It is used in write/erase control circuits, etc.

[Technical background of the invention and its problems]

Electrically erasable program: CEE PROM (Electrical
icallyErasable Programmab
EFROM) has been widely used in recent years because it does not require erasure by ultraviolet rays unlike conventional EFROM. In this EE PROM, it is necessary to perform various timing controls including the booster circuit, and for this reason, 10 MI-1z, that is, the period 1
It has a clock oscillator of about 00 S. Incidentally, the write/erase cycle is approximately 1 ms, and the data verify cycle is approximately 10 μs, so long-period pulses must be generated using short-period clock pulses.

As a method for generating long-period pulses from such short-period pulses, there is an RC delay method in which a delay is generated using a time constant determined by a resistor and a capacitor. However, when forming a MOS capacitor on an LSI,
In relation to the occupied area, a maximum capacity of only 10 PF can be obtained. In order to obtain a time constant of 10 μS, a resistance value R of 】MΩ is required, but achieving this does not mean increasing the number of LSI manufacturing steps, but also reducing variations due to process variations. Therefore, it is difficult to obtain an accurate high resistance value, and the RC delay method is practically impossible.

The second method is to divide the basic clock frequency, but in order to digitally divide the frequency by a factor of 100 to obtain a 10 μS clock pulse, a 7-stage T-type flip-flop is required. To occupy a large area on I and to obtain an additional 1 mS pulse, an additional 7
~8 stages of flip-flops are required, which is not realistic due to the exclusive area.

The third method is to perform analog noise counting using the principle of a so-called charge pump.A charge pump is a method in which signal charges captured in an interface state are injected into a substrate.・, The circuit shown in Figure 1 is typical. This is used for refresh control of dynamic RAM (・), and input terminal 1 is connected between capacitor C M
It is connected to the doin of the Ivi OS ) transistor 'r2 via the OS transistor T, and a capacitor C and a precharge transistor T3 are connected to its source side.
σ] drain, connected to inverter 40 input terminal
The output side of the inverter 4 is the output terminal.A high potential is applied to the source electrode 6 of the precharge transistor 'r3, and the capacitors C,
The drain of transistor T1 and the gate of transistor T are both grounded to the substrate.

In such a configuration, when the gate of the transistor T3 is opened for a certain period of time, the common connection point Node 3 is precharged to a high potential, and a predetermined clock pulse is applied to the input terminal 1, the voltage accumulated in the capacitor C is Since the gate of transistor Te opens due to the electric charge, the electric charge accumulated in capacitor C6K is gradually transferred to transistor R2.
As a result, the potential at node 3 rises, and when it exceeds the threshold of inverter 4, the potential at output terminal 2 is inverted.

With such a counter, the disadvantages of the previous two methods can be overcome because the count number is not easily affected by the two lump-filling manufacturing processes, and it can be achieved without using a large area. However, this method using a charge pump has a problem in that it cannot be used in a circuit using a CMO8+- transistor or the like to which no gate bias is applied. 1-In other words, in order to turn on the transistor T, the potential of the gate electrode 5 of the transistors 1 and 3 needs to be lower than the low potential Vss, but generally the substrate potential is Vss, so I
], the drain of transistor T2 becomes forward biased with respect to its gate, preventing normal operation. Moreover, there is the disadvantage that one of the complementary transistors operates due to the current in the original 11 direction, causing the I7 to latch. In addition, after the potential at the output terminal 2 is inverted, a pulse is applied to the gate 5 of the charging transistor T3 at a predetermined timing to precharge T3, and the pulse is inverted again to reduce the duty of the pulse to 50%. However, this timing control is very complicated and requires waveform shaping to make the duty 50%, which increases the cost of equipment and equipment.

[Object of the Invention] The present invention was made in view of the above-mentioned problems in VC, and it is possible to achieve stable counting force without being affected by fluctuations in the manufacturing process by using a back gate bias, and to achieve complicated control. The purpose is to provide a counter circuit that does not require

[Summary of the invention]

In order to achieve this objective, in the present invention, the transfer gates are connected in series to each other, each controlled by at least two phase clocks having equal and non-overlapping periods. An ink wire connected to the last stage of the switches connected in series, and an ink wire connected to each interconnection point of the switches as well as between the last stage switch and the inverter connection point and the reference potential point. This is a basic structural unit, and any number of stages of this basic structural unit are connected in series, and because it is determined only by the number of counts or the capacity-l ratio, it is susceptible to fluctuations in the manufacturing process and requires complicated control. It is not required to be cooked.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 2, I) is a circuit diagram showing the basic constituent unit 10 of the counter according to the present invention, which includes an n-channel MOS transistor T, and a P-channel Iν1ts) transistor T.
The first transfer gate switch with r2 connected in parallel and the n-channel 10S transistor 'r13 and p
Channel, Ruhe IOS transistor''r4.

A second transfer gate switch connected in parallel is connected in series, and the output of this second transfer gate switch (+411 has 11 channels [\I OS +
- transistor l]'r5 do p channel 1S10 S t
・The jlU gate of the inverter with the transistor connected outside the target is 7t long, and the European transistors Tr1 and Tr2 are connected to the ground 1L at the connection point of the first transfer gate and the second transfer gate. ,i',3,'
Clock signals φ1 and φ are applied to each gate of I'r4, respectively.
1, φ2, φ2 are applied. Note that φ and φ are expressed by signals having a quotient-low relationship fJ\opposite to the level. Mabuko-N! ,
The input terminal of the transfer gate 1 is the input terminal 11, and the input terminal of the inverter T1. And the source and drain of Tr60 are connected to each other, and output signal 12 is obtained. This flexible structure is represented by the symbols shown in Figure 2 (bl).

The operation in such a basic configuration JO will be explained next.

Now let V2 be the potential V of the input terminal ``1'', and the potential of the common connection point j3 between the second transfer gate and the inverter is v2, then the relationship between these V□, 2 and the transferred charge Q is C1 (V −V2) =CJ. Both clock signals φ1 and φ2 have a frequency r
If the input end 11 and the 7'-end 12
The current 1 flowing between θ; -1, and can be regarded as a resistance expressed by 1, which is 1 due to the fact that there is a delay td in applying the potential.

By cyclically following such a basic structural unit 1o in an odd number of stages so as not to cause oscillation, a counter can be formed. Fig. 3 shows an example in which three stages are connected.
;The second t? The output of the G component unit is input to the fourth stage.

In the case of N-stage connection, the overall oscillation frequency F is 2 td N
2RCN l+i 2 C22NIn2, C
When O, IPF, C2=lOPF, and N=3, the output obtained has a period about 420 times longer. For example, if the clock frequency f=HJMH2; then a pulse of 42 μs can be easily obtained. FIG. 4 shows the output potential V at the node 15 in FIG. 3 in this case.

This is a time chart showing the relationship between the clock signals φ1 and φ2, and it can be seen that a long-period pulse having a period equal to 420 clock signals is generated.

FIG. 5 is a circuit diagram showing an embodiment in which the counter circuit 21 of the present invention is used together with a boost circuit 20 in an EEPROM, and the boost circuit 2o is also driven by the two clock signals φ1 and φ2 that drive the counter circuit 21. I have to. This booster circuit 20 has M stages of self-biasing.
OS transistor T. 1,T,...Tro
02 are connected in series, and two clock signals φ1 and φ2 are applied alternately to each gate via a connection C6. Like this y'1. In the B voltage circuit, as the clock signal advances, the subsequent stage MOS transistor boosts the voltage, and the boosted voltage Vp is generated via the capacitor CL.
It is taken out as p. This booster circuit is used as a power supply'voltage Vl)
The time tH required to boost the voltage from D to VPPf is expressed by .

Here ■L is the amplitude of the clock signal - VPP is the boosted voltage,
(2) 1h is the threshold value of the transistor, M is the number of boosting stages, and f is the fundamental frequency of the clock, which can be treated as a constant except for -[, so tll is a function of f.

Therefore, the waveform of Vpp obtained by the booster circuit and (2) obtained by the counter circuit. By appropriately selecting the waveform and the circuit constant, the periods can be made to match, as shown in FIGS. 6(a) and 6(b). In an EEPROM, insert/erase characteristics are affected by whether or not a required boosted potential is applied at a predetermined timing. Therefore, the clock pulses of the counter circuit and booster circuit, which generate pulses for various controls, are connected to a common VC.
=j allows for good timing.

In the above embodiments, two types of clock signals were used, or clock signals of three or more phases with equal periods and non-overlapping based on the same source were used, and transfer gate MOS switches controlled by these clock signals were connected in series. It's okay.

In addition, although the transfer gate MOS switch in the basic configuration is a CMO8 configuration in which a p-channel type and an n-channel type are combined in the embodiment, it is not necessary and may be of either conductivity type. As for the circuit configuration, either an EEs configuration or an ED configuration can be used.

〔Effect of the invention〕

The counter circuit according to the present invention as described above includes a transfer gate SiOS switch and an inverter that are controlled by at least two-phase clocks having equal periods and that do not overlap with each other and are directly connected to each other. A counter is formed by connecting several stages of straw bales in series, using the connection point connected between each connection point and the reference potential as one unit of the configuration, and using the isometric resistance determined by the switch and the resistance. Moreover, since it is determined only by the count number or the capacity ratio, accurate counts can be achieved without being affected by variations in the manufacturing process, and moreover, no complicated control is required during counting.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of a conventional RC delay type counter, Fig. 2 is a circuit diagram showing an embodiment of the basic structural unit of the counter circuit of the present invention, and Fig. 3 and 1 are circuit diagrams showing the basic structural unit of the counter circuit of the present invention. A circuit diagram showing an example in which three stages are connected in series, Fig. 4 is a time chart showing the relationship between the clock signal used and the counter output, and Fig. 5 shows the clock signal of the counter circuit E E P
Connection diagram showing an example that is common to the ROM booster circuit,
Figure 6 is a 1-time chart showing the coincidence of the valley output timings of the booster circuit and the counter circuit in Figure 5. 10...Basic structural unit, 11...Input terminal, 12...
・Output terminal, 13, 15... Node, 20... Boost circuit, 2 ■... Counter circuit, Tr, ゛3 +
Tr 5''' n-channel MO'S transistor, 7
I+r2. Ill, 4.11,6. ... p-channel MO8) transistor. Applicant's agent Kiyoshi Inomata 1 Figure 6 Figure 2 Figure 4 420 inquiry■ Figure 5 2'1 Figure 6

Claims (1)

[Claims] 1. Transfer gate MOS switches controlled by at least two-phase clock signals having equal periods and non-overlapping periods and connected in series to each other; and a final stage of the series-connected switches. The basic structural unit is an inverter connected to the inverter, each interconnection point of the switches connected in series, and a capacitor connected between the connection point of the final stage switch and the inverter and the reference potential point, A counter circuit characterized in that an arbitrary number of stages of constituent units are connected in series, and the output of the final stage is inputted to the first stage. 2. The counter circuit according to claim 1, wherein the reference potential is a power supply voltage or a ground potential. 3. The run-up circuit according to claim 1 or 2, wherein the clock signal coincides with the control clock of the booster circuit of the EEPROM.