JPS6011944A - Program analyzer - Google Patents

Abstract

PURPOSE:To check the working of a computer in terms of data by tracing an execution locus of each module, and collecting the check information. CONSTITUTION:At first, the register procesing is executed to a bit map memory 5. Then a multiplexer 12 is switched to a real device 1, and the operation of the device 1 is started to decode successively the instructions of programs to be checked and stored in a memory 3. The address of a module with which the instruction is executed is stored to a history memory 6 in the form of data. Then the similar address data are successively collected in accordance with the progress of the program. When the collection is through with data, the data are analized to obtain a hierarchical diagram.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a technique for tracking the execution trajectory of a computer program and analyzing machine operation.
When a program to be inspected is made up of a plurality of modules combined, a program analyzer is provided that collects information on the execution trajectory of each module.

<Background of the Invention> In recent years, operating programs for computer systems are divided into modules of appropriate size according to the content of the work, etc., and when executed, each module is connected via a call instruction to form a series of 4A a. It has become In the case of this type of structured program, when shipping the system, it is necessary to conduct 461 tests to determine whether all modules are executed in accordance with the designed combinations. However, there is still no way to check the execution trajectory of each module using data.
This makes the system check incomplete.

<Objective of the Invention> The present invention is a program configured by combining a plurality of modules, and the computer operation can be checked data-wise by tracking the execution locus of each module and collecting inspection information. The purpose is to provide a new program analyzer that can perform 114 functions.

<Structure and Effects of the Invention> In order to achieve the above object, the present invention registers the start address of each module and the set address of the return command in advance in the registration means, and then executes the program to start the machine. The controller operates the module, reads the addresses of commands executed for each module as data, compares them with the registered data, and when there is a match between the two data, sequentially stores the addresses of the commands executed in the data storage means to collect information. It was decided to.

According to the present invention, by retrieving address data from the data storage means, the execution locus of each module can be easily grasped. By creating a hierarchical diagram showing the combined structure of each module based on the data read out in the history, and comparing it with the hierarchical diagram at the time of design, it is possible to check whether each module has been executed as designed and to improve computer operation. The present invention has excellent effects that achieve the purpose of the invention, such as making it possible and easy to check data.

<Explanation of Examples> Figure 1 shows a machine 1 (hereinafter referred to as the actual machine), which is a computer system, and a program analyzer 2 by Akira Kiyoshi.
The connection status is not shown.

The actual device 1 includes a memory 3 in which a block diagram to be inspected is stored;
The actual CPU 4 (Cen.
tral Processing Llnit).

The program to be tested is constructed by combining t modules, and a hierarchical diagram of each module is shown in Figure 2, with dots on the sides. In the c132 diagram, each block represents a module, three modules "I 9 P2 + I'3 are connected to the module P, and the module I11 is either the module Pl+ or the module P2 is the module "211 "22 +P23 are connected to each other, and furthermore, two modules are connected to module '22.''
22-1, I", 2-2 are combined. The start address of the module P is A in FIG.
A return instruction is provided at the final address a.

Similarly, in FIG. 3, the module "l + "2 +
”3, the optical surface address is AI + A2 + A3, and the return command setting address is aII A2, A3,
Moji: L-L P 11, P21 +'22 +"
23 has the first address AII + A21 HA22
+A23, return instruction setting address is aII +
"21+a22+a23, Mod/L/I' 22
-1, P22-2 is the first address or A22-1
, A22-2, return instruction setting address is 122
-1. They are respectively indicated by a2□-2. Also, address 1) 1°1+2 in module 1'. b3 has module 11. , I), , A call instruction to call the beginning of P3 is set, and similarly, the address b11 in module pl is either the call instruction of module P11 or the address 1) 2+ + '2 of module P2.
2) 1) 23 has module 1) 21 r P22
+1'23 117 output instruction is at address h22-] of module '22, t)22-2 has module P22-1. ．． 1''22-2 calling instructions are set respectively.

The program analyzer 2 of the present invention includes a bitmap memory 5 and a history memory 6 in the example shown in the first section 1. The bitmap memory 5 stores the start address and return instruction setting address for all modules, and the hist memory 6 stores actual punishment 1 or actual instruction execution address.
Only the addresses that match the recorded data are selected (11) and stored.

Registration or storage of such addresses is C11118.
Its operation is controlled by This CI' tl 8i
A. Based on the detection program stored in the memory 11, turn on the control circuit 7 and turn it on! - In addition to controlling operations such as data writing to the map memory 5 and the history memory 6, the display device 9 multiplexer 12
Att1/stator manually generated from CI' II 4 and CP [13] is stored in bitmap memory 5 by time division.
Output to. Further, the timing control circuit 13 is
The operation timing for loading the address data from the actual machine (21'Ll4) into the history memory 6-\r'Fj: is determined.

FIG. 4 shows program check f-111+4, and the operation of the tree invention will be described below based on flowchart 1 in the same figure.

First, in step 21, the registration process to the hit map memory 5 is executed, and as a result, the data ``1'' is stored in the hit map memory corresponding to the setting address of the head map and return command in all the modules, or other areas are stored. is set to data “0”. At step 22, multiplexer 2 is switched to actual machine 1, and in step 23, operation of the actual machine is started, and each instruction of the program to be tested stored in memory 3 is sequentially decoded and executed.
-ru. During this process, when an instruction at an address where data "1" is set in the bitmap memory 5 is executed, the bitmap memory 5 sends an output of logic "1" to the history memory 6. As a result, the address of the module where the command was executed is stored as data 2 in the hist memory 6, and as the program progresses, similar address data is collected from time to time (step 24).

FIG. 5 shows an example of collection of address data, and the hist memory 6 in the same figure stores in chronological order the 7'F and stake of each module that matches the registered data after an instruction is executed. After the data collection is completed, in step 25 the process moves to the analysis of the stored data, and through this analysis, the E+
A hierarchical diagram shown in Chart 6 can be obtained.

Thus, if we compare the hierarchy diagram at the time of design shown in Figure 2 with the 1-layer diagram shown in Figure 6, we can see that the hierarchy diagram in Figure 6 (J module P22-2 is missing, and from this it can be understood that during the test program 1''t, module P2□-2 was not actually executed.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram showing the program analyzer →] of this defense, Fig. 2 is a hierarchical diagram of the design n1 program, and Fig. 3
Figure 5 is a diagram explaining the address of the design program, Figure 4 is a flowchart of the program 167-W (without showing steps), Figure 5 is a diagram explaining the state of data storage in the hist memory, Figure 5 is a diagram explaining the data storage state of the hist memory, (This is a hierarchical diagram of 4 execution programs. ■... Actual machine 5... Hit map memory 6... Hist memory 8... CP
U special π) Applicant Tateishi ij; Ki Co., Ltd. -〇〇

Claims (1)

[Claims] In a program configured by combining a plurality of modules, a registration means for registering a start address and a set address of a return instruction in each module, and an address of each module in which an instruction has been executed is compared with registered data and selected. A program analyzer comprising: data storage means for storing data; and control means for controlling data processing operations of the registration means and data storage means.