JPS60117854A - Transmission logical circuit of time division multiplex communication equipment - Google Patents

Abstract

PURPOSE:To transmit a signal of each transmitter uniinterruptibly even at manual switching of two transmitters by inputting a signal after additive sum operation of a selected transmitter to an additive sum operation circuit of the transmitter not selected. CONSTITUTION:When a transmitter switching signal (b) is at logical H, that is, the 1st transmitter is selected, an AND circuit 4 of the 1st (transmitter) transmission logical circuit 1 is set by the signal (b) and an output signal (c) of an additive sum operation circuit 2 of the 1st transmitter is returned to the said circuit 2. Moreover, the signal (b) is inputted to an AND circuit 5 of the 2nd transmission logical circuit 8 via inverter circuits 7, 6, the circuit 5 is also set and the said output signal (c) is applied also to the input of the additive operation circut 2 of the 2nd transmitter through the AND circuit 5 and an OR circuit 3. When the switching signal (b) is logical L, that is, the 2nd transmitter is selected, an output signal (a) of the additive sum operating circuit 2 of the 2nd transmitter is returned similarly to the additive sum operating circuit 2 of both the transmitters. Thus, the signal of both the transmitters is uninterruptible even at the switching of the transmitters.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transmission logic circuit for a time division multiplex communication device.

[Prior art]

A conventional circuit of this type is shown in FIG. In the figure, l is a transmission logic circuit of a time division multiplex communication device, 2
is a sum calculation circuit in this transmission logic circuit l.

It is a well-known fact that in the above-mentioned time division multiplex communication device, logic processing is performed in the sum calculation circuit 2 of the transmission logic circuit 1 in order to perform differential phase modulation. Here, during the logic processing of the summation calculation circuit 2, if the initial values are different, the sign after the summation calculation processing will also be different.

Therefore, in such a conventional transmission logic circuit, 2
When manually switching two transmitters, each transmitter has a different sign after the summation calculation, which has the disadvantage that it is not possible to switch signals without momentary interruption.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and in the transmission logic circuit provided in each of two transmitters, one of which is selected by an external switching signal. By inputting the signal after the summation calculation of the selected transmitter to the summation calculation circuit of the transmitter that has not been selected, the signal of each transmitter can be interrupted without momentary interruption even when manually switching between two transmitters. It is an object of the present invention to provide a transmission logic circuit for a time division multiplex communication device that is capable of transmitting data.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the figure, ■ is the transmission logic circuit of the first transmitter (hereinafter referred to as the first transmission logic circuit), 8 is the transmission logic circuit of the second transmitter (hereinafter referred to as the second transmission logic circuit), 4 5 is the first AND circuit (first logic circuit) that inputs the Japanese signal of the selected transmitter after calculation into the Japanese calculation circuit of the transmitter itself, and 5 indicates that the other transmitter is selected. 3 is a second AND circuit (second logic circuit) which inputs the signal after the Japanese operation of the other transmitter to the Japanese operation circuit of the unselected transmitter when the transmitter is selected. second AND circuit 4,
OR circuit that inputs the output of 5 to the Japanese arithmetic circuit 2, 6, 7
is an inverter circuit.

Further, a is the signal after the summation operation from the second transmission logic circuit 8, C is the signal after the summation operation from the first transmission logic circuit 1, and b is the signal after the summation operation from the first transmission logic circuit 1. This is a switching signal for switching the second transmitter, and is "H" when the first transmitter is selected, and "L" when the second transmitter is selected.

Next, the operation will be explained.

First, when the transmitter switching signal is "H", that is, the first transmitter is selected, the switching signal turns the antenna circuit 4 of the first transmitting logic circuit 1 into the ON state, and the first transmitter is switched on. 1
The output signal C of the summation calculation circuit 2 of the transmitter passes through the first to AND circuits 4 and the OR circuit 3 to the summation calculation circuit 2.
It will be returned.

The above switching signal is passed through the inverter circuit 7.6 to the second
is also input to the second AND circuit 5 of the transmission logic circuit 8,
This second ant circuit 5 also enters the N state, and the output signal C of the sum calculation circuit 2 of the first transmitter passes through the second AND circuit 5 and the OR circuit 3 to the second transmitter. It is also applied to the input of the sum calculation circuit 2.

On the other hand, when the switching signal is "L", that is, the second transmitter is selected, this switching signal causes the second AND circuit 5. and the first AND circuit 4 of the second transmission logic circuit 8 is in the ON state, and in this case, the second
The output signal a of the sum calculation circuit 2 of the transmitter is returned to the sum calculation circuit 2 of both transmitters.

According to the device of this embodiment, the output code of the transmission logic circuit is the same for both transmitters, and even when switching between the first and second transmitters, the signals of both transmitters can be uninterrupted. Can be sent.

Note that the basic principle of the present invention is widely applicable to devices in which the output signs of two devices differ due to differences in initial values, and similarly to the above embodiment, signals of two devices can be switched without momentary interruption.

〔Effect of the invention〕

As described above, according to the present invention, in the transmission logic circuit of the time division multiplex communication device provided in each of the two transmitters, the selected transmission Since the signal after the summation calculation of the transmitter is inputted, the signal from each transmitter can be transmitted without momentary interruption even when the two transmitters are manually switched.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a transmission logic circuit of a conventional time division multiplex communication device, and FIG. 2 is a schematic configuration diagram of a transmission logic circuit of a time division multiplex communication device according to an embodiment of the present invention. 1.8... Transmission logic circuit, 2... Sum calculation circuit, 3
... OR circuit, 4 ... First AND circuit (first logic circuit), 5 ... Second AND circuit (second logic circuit), 6 ... Inverter circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa

Claims (1)

[Claims] fl) A transmission logic circuit of a time division multiplex communication device having a summation calculation circuit for performing differential phase modulation, which is provided in each of two transmitters, one of which is selected by an external selection or non-selection signal. a first logic circuit that receives the selection signal and inputs the signal after the summation calculation of the selected transmitter to the summation calculation circuit of the transmitter itself; and a second logic circuit that inputs the signal after the summation calculation of the other transmitter to the summation calculation circuit of the unselected transmitter itself. logic circuit.