JPS60116172A - Semiconductor device - Google Patents

Abstract

PURPOSE:To perform a bipolar operation by forming the first and second regions in semi-insulating regions, and selectively providing the other third conductive type region on the semiconductor between the both the first and the second regions, thereby applying a forward bias between the third and the first regions, and forming an imaginary base region under the third region. CONSTITUTION:P type impurity is doped in high density on the main surface 10a of a semi-insulating semiconductor 10 to form a semiconductor layer 11, and a base electrode 12 is selectively coated on the layer 11. With the electrode 12 as a mask an N type impurity ions different from the layer 11 are implanted from the main surface side of the semiconductor 10, thereby forming the first and second regions 13, 14 as emitter and collector regions. Then, the layer 11 is selectively etched to set the remaining layer 11 as the third region. Emitter and collector electrodes 15, 16 are coated on the regions 13, 14, respectively. A forward bias potential is applied between the region 13 and the layer 11, an imaginary base region due to the implantation of the majority carrier from the layer 11 is formed in the semiconductor 10 under the layer 11, thereby performing a bipolar transistor operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a semiconductor device, particularly a modern semiconductor device with a special configuration that allows bipolar transistor operation.

BACKGROUND TECHNOLOGY AND PROBLEMS Bipolar I transistors as circuit elements of semiconductor integrated circuits have been developed due to the simplification of manufacturing and wiring patterns.
It is desirable to adopt a so-called lateral structure in which the emitter, base, and collector regions are arranged in a plane. However, this lateral structure bipolar transistor generally has a drawback that the current amplification factor β is small.

On the other hand, a semiconductor device using a GaAs compound semiconductor has 1
0. Semiconductor integrated circuits made of GaAs have been attracting attention because of their excellent high-speed operation and the fact that GaAs has semi-insulating properties, which simplifies the isolation structure between circuit elements. (There is.

OBJECTS OF THE INVENTION The present invention provides a semiconductor device which does not operate as a bipolar transistor with a particularly large current amplification factor and which is used as a semiconductor integrated circuit or a single semiconductor device, for example, and has excellent commercial continuity. be.

4 Summary of the Invention In the present invention, ′ζ is characterized in that a first region serving as an emitter region of one conductivity type and a second region serving as a collector region are arranged in a semi-insulating semiconductor with a required spacing between them. 1st
A third region 4J is selectively provided on the semi-insulating semiconductor between the second region # and a copita ζ1-shall layer of another conductivity type. Then, a forward high speed voltage of 5.5 mm is applied between the third region and the first region. Then, from these third regions, 61 people were transferred to the '12 insulating semiconductor region of the third region 1.
A virtual base region is formed in each third region 1 to perform bipolar transistor operation.

With reference to the drawings, an example of the semiconductor device according to the present invention will be explained along with an example of its manufacturing method in order to facilitate its understanding. As shown in FIG. For example, an Ill-V group compound semiconductor substrate of l+ RA S or a semiconductor layer 00), which does not contain impurities in terms of η and exhibits high resistance, is prepared, and one main surface (10
a) An example in which P-type impurities are doped to +i:I+ concentration is ^j! For example, 1m (11,) of GaAs semiconductor is
ζThis semiconductor I
n(II), optionally with the required width W
+l f: 'Hasei Konkaku 1r I, J, Illusionary base electrode (
12) is applied ohmically. .

Next, using this electrode (12) as an etching resist, for example, as shown in FIG. 2, the semiconductor IFti (11) exposed to the outside on both sides of tJij% (12) is removed by etching.

Next, as shown in FIG. 3, using at least the electrode (I2) as a mask, the semi-insulating base plate is connected from the main direction side of the semiconductor layer αψ to other conductivity types different from the semiconductor layer (l). For example, N-type impurities are introduced by ion implantation, diffusion, etc., so that at least the positions of the opposing edges are in a predetermined positional relationship with the edges of the electrode (12) and the semiconductor layer (11) below. , i.e. these edges coincide with rt,
In other words, if this semiconductor layer (11) has the required width,
First and second areas regulated to enter (13)
and (14) are formed. In this case, these areas (13
) and (14), the position of the edge facing 11-i is automatically adjusted to maintain a predetermined positional relationship with the 'd1 pole (12) and its semiconductor layer (11), as described above. Consistent with
Semiconductor 1fJ is so-called cell soar aligned.
In the selective J-etching of (11) (as a mask)
C) This electrode (12) is used as a mask,
Although the positions of the edges of these regions (13) and (14) are not shown in the figure, the positions of the edges of the
-I-Ion implantation of impurity or expansion mask IH
It is also possible to form each region (I3) and (14) by forming a .

Next, the emitter and collector electrodes (15) and (16) are ohmically deposited on the first and second regions (13) and (14). , for example, an N-type emitter and a semiconductor with impurity concentration of +11+ impurity concentration of type 1:Ii impurity concentration 9 in the first and second regions (13) and (14), for example, a semiconductor of type 1:4rll
) are arranged side by side in a plane. E, C and B represent the names of kominota, -l rector and base, respectively -3-.

Soj, 7, ffil /y-7d'? (S 3 territory Ji
A forward bias can be applied between f133 and the second region (11) and (14), and a reverse bias can be applied between f133 and the second region (11) and (14). As a result, the ball of the majority carrier from the third region (jl) is transferred to the semi-insulating semiconductor 00 between the first and second regions j13i (13) and (14) of this third region (II). ) is implanted into the high resistance region (17), where a virtual
A base region 1 is generated, and this creates the first region ′C (1
3) Promote that majority carry “+1 person of 1 electron,”
This virtual base area is defined as J1]1 (first flJJ area (
13) majority carrier reaches the second region (+4)4j, N
-Performs P-N type bipolar transistor operation.

In addition, in the example of 1, J-: 3Ai, the first and second regions (I3) to (14) are formed by the ion implantation method or the diffusion method, but these are formed by the alloy method. You can also.

Effects of the Invention I - According to the semiconductor device according to the present invention described above, each region (
11) , (13) and (14) have a lateral structure arranged in a plane, so take out the electrodes.

Wiring becomes easy, which is advantageous when configuring an integrated circuit.

Further, as mentioned above, the device of the present invention has a lateral structure, but nevertheless, the device of the present invention has a lateral structure.
There is an advantage that humans can obtain Ii style amplification factor β. Zunawa I) In the present invention, the current path by the base region, that is, the injection center rear, is actually
Half group 15fl+ outside the 53rd region (11) with a 1+ impurity concentration of 1, and a region (17) with a low impurity concentration of 61
C1 injection of C7 to form inside ↑ - Yaria's 1 wide 11k length is the 3rd ladle ζ] Scolding, Manoko Hangai to the edge 1 cattle bandit (
17), the bottom seat harry J′ is low and the average JI
It is less susceptible to the influence of the collector voltage (!II), and the current increases by 1.1 × 4β, and the bibolar transistor operates at a faster operating speed.

Furthermore, this zIY property is caused by variations in the thickness, characteristics, etc. of the thirteenth region (11), since each substantial base region is formed in a semi-insulating 'Kj# body. (The influence of stiffness is small, and therefore, a stable and uniform conductor device can be easily manufactured.

Maso ζ, for the third region (11), the first and second regions (
13) and (14) have symmetry, so 1. :lL
It is possible to form a transistor in which the emitter and collector are a pair (!1).

In addition, since it is configured as a semi-insulating semiconductor, the integrated circuit b'B
When applying &, isolation between elements becomes simple f1
There is a profit to be made into one.

[Brief explanation of drawings]

j' (S Go to Figure 1/Figure 4 is a one-dimensional enlarged view of each step of a manufacturing method of an example of a semiconductor device according to the present invention. 00) is a semi-insulating II semiconductor, (11) (13) and (14) are people number 3. These are first and second regions.

Claims (1)

[Claims] A first layer that becomes an emitter region of one conductivity type in a semi-insulating semiconductor.
A third epitaxial layer of a different conductivity type is selectively formed on the semi-insulating semiconductor between the first and second regions. A region is provided, and a forward high-intensity pressure is applied between the third region and the first region to transform the virtual base region into the semi-insulating region of the third region by injecting the majority carriers from the third region. 1. A semiconductor device which is formed of a polar semiconductor to perform bipolar 1-transistor operation.