JPS6011515B2 - Signal detection control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection control circuit in a recording/reproducing apparatus.

In a digital recording and reproducing device that converts continuous signals such as audio or images into digital quantities and records and reproduces them,
During reproduction, it is common to implement means for absorbing jitter in the reproduced digital signal.

A buffer memory is used to absorb this jitter. Writing to the buffer memory is performed using a clock extracted from the reproduced digital signal, and reading is performed using a clock having a reference oscillation frequency. If the frequency of the clock extracted here differs greatly from the frequency of the reference clock, unnecessary information will be read from the buffer memory, and noise will be mixed into the reproduced signal.

Furthermore, if reading from the buffer memory is performed when no clock has been extracted during reproduction, noise will also be mixed into the reproduced signal. As described above, in a digital recording/reproducing apparatus, it is essential to perform the writing and reading timings of the buffer memory correctly.

The present invention is a digital recording and reproducing system having a closed servo system that runs the tape at the same constant speed as during recording by synchronizing a signal obtained by dividing a constant frequency signal recorded on a control track with a reference frequency signal. The device detects the frequency of the signal reproduced from the control track during playback, generates a signal to configure the closed servo when the frequency becomes almost the same as that during recording, and then generates a signal to configure the closed servo when synchronization is achieved. Noise is mixed into the reproduced signal by generating a signal to start writing to and reading from the buffer memory, and by stopping writing to and reading from the buffer memory when the clock signal extracted from the reproduced digital signal ends. The present invention provides a signal detection control circuit that can prevent such occurrences.

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows a block configuration including a buffer memory 1.

The reproduced digital signal 6 is sent to the buffer memory 1 and the clock extraction circuit 2, and the clock extracted by the clock extraction circuit 2 is used for writing into the buffer memory 1 and is also sent to the data detection circuit 3. As long as the clock is being regenerated, there is an output from the data detection circuit 3, and this output is used to control the buffer memory-1. The reproduction control signal 7 is sent to the servo control detection circuit 4,
Its output is used to control the servo switching 9 and the buffer memory 1. The outputs of the data detection circuit 3 and the servo control detection circuit 4 are ANDed by an AND gate 5, and this is used as a control signal for the buffer memory 1. The portion surrounded by the broken line including the data detection circuit 3 and the servo control detection circuit 4 is the portion of the present invention. The data detection circuit 3 is the second
This can be realized as shown in the figure.

The operation will be explained below using FIG. The data signal from the clock extraction circuit 2 is input to a 1/n division circuit 11 and a signal detection circuit 12. The signal detection circuit 12 further receives a signal of an arbitrary bit of data. This signal uses a signal before demodulation, and as long as data is being read, "1" is written into the signal detection circuit 12 according to the clock signal. The signal detection circuit 12 continuously
Outputs “1” only when n “1”s are written, and outputs “0” if n “1”s are not written consecutively.
Output. The output of this signal detection circuit 12 is read into a flip-flop 13 using the output of the divider/retractor circuit 11 as a clock.

As a result, the output Q of the flip-flop 13 becomes "1" as long as n pieces of data of the reproduced digital signal 6 are successively reproduced, and otherwise becomes "0". The output of this flip-flop 13 is used as a control signal by NOR.
Gates 14 and 15 input the output of frequency dividing circuit 11 to counting circuits 16 and 17.

The count value is m. Now, as long as the data of the reproduced digital signal 6 is being reproduced without any disturbance, the output Q of the flip-flop 13 is "1" as described above, so the output of the frequency dividing circuit 11 passes through the NOR gate 15, and the counting frequency is 17.

When m clocks are input to the counting circuit 17, a carry output CA is output, and this carry output CA and the counting circuit 17
The counting circuit 16 is reset to the initial state in synchronization with the clock by performing a NAND 18 with the clock input to the clock. This reset causes the carry output 2 of the counting circuit 16 to
Kawama becomes “0”.

When n pieces of data are successively output without disturbance and this state is maintained m more times, the counting circuit 16 becomes a reset state, and the carry output 2 remains at "0". This carry output 20 is used as an inverted output 21 from the data detection circuit 3. If data is lost due to dropout, the output of the signal detection circuit 12 becomes "0", and as a result, the clock from the frequency dividing circuit 11 is input to the counting circuit 16, but this state does not continue m times. As long as counting circuit 1
Since there is no carry output from 6, the output of the data detection circuit 3 remains at "1".

When the data of the reproduced digital signal is disrupted, that is, when the data ends, the input to the signal detection circuit 12 is disrupted, and its output continues to be "0". At this time, the clock from the frequency dividing circuit 11 is input to the counting circuit 16, so
After m counts, a carry is constantly output, and the data detection circuit 3 outputs "0". This clock counting circuit 17 is reset to the initial state. This data detection circuit 3 can be used to control the buffer memory, but since this circuit rises quickly, it operates before the servo is synchronized, which results in noise being mixed into the reproduced output.

Therefore, a circuit to detect servo synchronization is required. That is the servo control detection circuit 14. The operation of the circuit will be explained below with reference to FIG. When the playback button is pressed, "1" appears at the terminal 22, resetting the servo control detection circuit 4 to its initial state.

That is, at the rising edge of 22, the rising edge detection circuit 24 generates a reset pulse (shown in FIG. 3) to perform a reset. Since the flip-flop 38 is reset, "0" is output to the output QL. As a result, the output to the servo converter 9 becomes "0", and the tape is running in an open servo state. Next, playback control signal 7 from the tape
is sent, the playback control signal detection circuit 25
outputs "1" as long as the reproduction control signal continues.

The reproduction control signal detection circuit 25 generates a set pulse (shown in FIG. 3) when the reproduction control signal 7 ends. The duty of the reproduction control signal 7 is set to be sufficiently large. The rise detection circuit 26 detects the rise of the reproduction control signal 7 and generates a reset pulse (shown in FIG. 3), and applies a reset input to the reset terminal 33 of the counting circuit 34 to set it to an initial state for starting counting. The reproduction control signal 7 is inputted to the gate terminal 35 as a gate signal for determining the counting period of the counting circuit 34. Using this gate, the clock 23 having a frequency sufficiently higher than that of the reproduction control signal 7 is inputted to the clock terminal 36 for counting.

This count value is decoded by a decoding circuit 37. If the reproduction control signal has a normal frequency, a fixed count value is output, so the decoding circuit 37 outputs "1" at that time. If it is not normal, the output will be "0". The output of the fall detection circuit 27 of the reproduction control signal 7 is used as a clock, and the above data is input to the flip-flop 38. When normal, the output QL of flip-flop 38
becomes ``1'' and Q2 becomes 0. As a result, the gate terminal 35 of the counting circuit 34 receives the signal ``0'' through the AND gate 32.
” will be input, so no counting will be performed from now on.

Additionally, a "1" is output by the AND gate 28 and sent to the servo switch 9 to switch the servo into a closed loop state. If it is not normal, a gate signal is input to the gate terminal of the counting circuit 34, so that counting is performed again. After the reproduction control signal becomes normal, until the servo system stabilizes in a closed loop state, the reproduction digital signal data will be disturbed, so do not input it to the buffer memory. For this purpose, a delay circuit 39 is provided, and this delay circuit 39
After the servo system is switched and stabilized in a closed loop state, a signal that becomes "1" is sent as a buffer memory control signal.

The outputs of the servo control detection circuit 4 and the data detection circuit 3 are A
The ND gate 5 performs an AND operation, and the result is used to control the buffer memory. As described above, according to the present invention, writing to or reading from the buffer memory 1 is not performed before the servo system is stabilized, and furthermore, the reproduced digital signal is stopped immediately after completion.

When controlling the buffer memory 1 using only the data detection circuit 3, writing and reading are executed before the servo system is stabilized, so the reproduced digital signal is distorted and reproduced, resulting in noise being mixed into the reproduced signal. .

On the other hand, when the buffer memory is controlled by only the servo control detection circuit 4, the falling edge of this circuit is slow, so even though the reproduction digital signal has finished, writing to and reading from the buffer memory 1 is executed, and the reproduction is started. Noise will be mixed into the signal.

However, in the present invention, the deficiencies of each detection circuit are compensated for, so that the buffer memory can be controlled correctly.

It is also possible to control the buffer memory 1 only by the data detection circuit 3 and make the capacity of the buffer memory sufficiently large so that it can absorb disturbances caused by servo switching of the reproduced digital signal. The memory capacity becomes extremely large, leading to high costs. Furthermore, since the state of data disturbance at the time of servo switching is not necessarily constant, it is difficult to determine the capacity of the buffer memory.

According to the circuit system of the present invention, the capacity of the buffer memory is 4
・The capacity can be easily determined without causing any problems with data disturbance during servo switching.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of buffer memory control including the circuit of the present invention, FIG. 2 is a data detection circuit diagram of the present invention,
FIG. 3 is a servo control detection circuit diagram of the present invention. 1...Buffer memory, 2...Clock extraction circuit, 3...Data detection circuit, 4...
...Servo control detection circuit, 6...Reproduction digital signal, 7...Reproduction control signal, 9...
...Servo switching. Shige〆Z zu Shizu 7

Claims (1)

[Claims] 1 In a recording/playback device that digitizes a signal, records it on a tape, and plays it back, it plays back a signal of a constant frequency recorded on a control track during playback, divides the signal, and synchronizes it with a signal of a reference frequency. By running the tape at the same constant speed as when recording, the reproduced digital signal is written to the buffer memory for jitter absorption at a constant cycle, and when read from the buffer memory at a constant reference frequency, The time to start writing and reading is when the playback control signal and the reference frequency signal are synchronized, and the time to stop writing and reading from the buffer memory is when the clock extracted from the playback digital signal ends. A signal detection control circuit characterized in that it is configured as follows.