JPS60113525A - Ecl gate circuit - Google Patents
Ecl gate circuitInfo
- Publication number
- JPS60113525A JPS60113525A JP22238583A JP22238583A JPS60113525A JP S60113525 A JPS60113525 A JP S60113525A JP 22238583 A JP22238583 A JP 22238583A JP 22238583 A JP22238583 A JP 22238583A JP S60113525 A JPS60113525 A JP S60113525A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ecl
- gate circuit
- cascode
- ecl gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1738—Controllable logic circuits using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明はＥＣＬ （Ｅｍｉｔｔｅｒ ＣｏｕｐｌｅｄＬ
ｏｇｉｃ） ゲート回路に関するものである。[Detailed Description of the Invention] Technical Field> The present invention is directed to ECL (Emitter Coupled L).
ologic) This relates to gate circuits.
〈従来技術〉
ＥＣＬゲート回路において、高抵抗を用め電流レベルを
下げて低消費電力化することが提案される。しかし、従
来のＥＣＬゲート回路では出力インピーダンス、入力容
量共に大きくなり、スピードか落ち、波形もくずれてぐ
る。<Prior Art> In an ECL gate circuit, it has been proposed to reduce power consumption by using a high resistance and lowering the current level. However, in the conventional ECL gate circuit, both the output impedance and the input capacitance become large, the speed decreases, and the waveform becomes distorted.
〈発明の目的〉
本発明は、ＥＣＬゲート回路にトランジスタのカスコー
ド接続を導入することにより、低消費電力で入力容量の
小さい回路を実現する。またこの接続により、前段回路
の出力インピーダンスか大きい場合でも、回路の入力容
量の影響を最小限に抑え、低消費電力化できる。<Object of the Invention> The present invention realizes a circuit with low power consumption and small input capacitance by introducing a cascode connection of transistors into an ECL gate circuit. Furthermore, with this connection, even if the output impedance of the preceding stage circuit is large, the influence of the input capacitance of the circuit can be minimized and power consumption can be reduced.
〈実施例〉 以下図面に従って本発明の詳細な説明する。<Example> The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す２人力ＮＯＲゲート回
路である。トランジスタロ工〜Ｑ４ ｓ抵抗Ｒ１〜Ｒ３
は通常のＥＣＬゲート回路を構成するもので、Ｑ２ ｈ
Ｑ３とＱ４は差動増幅として動作する。Ｑ□は定電流
源でＲ１−Ｒ３は低消費電力化のために高凱抗値のもの
を用いている。ここにおいて、本発明は図示のように、
トランジスタＱ５ 、Ｑ６を追加し、上記差動増幅器に
このトランジスタＱ５ 、Ｑ６をカスコード接続して構
成される。このカスコード接続により、Ｑ２ ｒ Ｑ３
の入力容量の増加を抑える。FIG. 1 shows a two-man power NOR gate circuit showing one embodiment of the present invention. Transistor work~Q4 s resistor R1~R3
constitutes a normal ECL gate circuit, and Q2 h
Q3 and Q4 operate as a differential amplifier. Q□ is a constant current source, and R1-R3 are of high resistance value in order to reduce power consumption. Here, the present invention, as illustrated,
Transistors Q5 and Q6 are added, and these transistors Q5 and Q6 are connected in cascode to the differential amplifier. With this cascode connection, Q2 r Q3
suppress the increase in input capacitance.
第２図は第１図の回路を含むゲート接続例を示すもので
ある。第１図と同一機能を有する１小分Ｃｔこは同じ符
号を付して示している。FIG. 2 shows an example of gate connections including the circuit of FIG. 1-subsection Ct having the same function as in FIG. 1 is indicated with the same reference numeral.
例えば、第２図のような接続の場合、Ｑ５＋Ｑ６のない
場合に比べて、Ｑ２ 、Ｑ３の入力容量の増加は抑えら
れるので、前段回路の抵抗ＲＬが大きい場合（電流レベ
ルを下げて低消費電力化を可能にする）でも、応答速度
、波形への悪影響を最小限にとどめられる。For example, in the case of the connection shown in Figure 2, the increase in the input capacitance of Q2 and Q3 can be suppressed compared to the case without Q5 + Q6. even if the current speed is reduced, the negative effects on the response speed and waveform can be minimized.
〈発明の効果〉
以上のように本発明は、カスコード接続をＥＣＬ回路（
（導入して実用価値の高い低消費電力化回路が提供でき
る。<Effects of the Invention> As described above, the present invention connects cascode connections to ECL circuits (
(By introducing this, a low power consumption circuit with high practical value can be provided.
第１図は本発明の一実施例を示す回路図、第２図は第゛
１図の回路を用いたゲート接続例を示す回路図である。
Ｑ、−Ｑ４ ・トランジスタ、Ｑ５ 、Ｑ、 ・・・カ
スコード接続のトランジスタ。
代理人 弁理士 福 士 愛 彦（他２名）Ｊｈ２図FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of gate connection using the circuit of FIG. Q, -Q4 ・Transistor, Q5 , Q, ... Cascode connected transistor. Agent Patent attorney Aihiko Fuku (2 others) Jh2 diagram
Claims (1)
ることを特徴とするＥＣＬゲート回路。1. An ECL gate circuit characterized by having a transistor connected in cascode to a differential amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22238583A JPS60113525A (en) | 1983-11-24 | 1983-11-24 | Ecl gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22238583A JPS60113525A (en) | 1983-11-24 | 1983-11-24 | Ecl gate circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60113525A true JPS60113525A (en) | 1985-06-20 |
Family
ID=16781526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22238583A Pending JPS60113525A (en) | 1983-11-24 | 1983-11-24 | Ecl gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113525A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0390593A2 (en) * | 1989-03-30 | 1990-10-03 | Kabushiki Kaisha Toshiba | Heterojunction bipolar transistor integrated circuit |
| EP0511711A2 (en) * | 1991-05-01 | 1992-11-04 | Koninklijke Philips Electronics N.V. | Programmable combinational logic circuit |
-
1983
- 1983-11-24 JP JP22238583A patent/JPS60113525A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0390593A2 (en) * | 1989-03-30 | 1990-10-03 | Kabushiki Kaisha Toshiba | Heterojunction bipolar transistor integrated circuit |
| EP0511711A2 (en) * | 1991-05-01 | 1992-11-04 | Koninklijke Philips Electronics N.V. | Programmable combinational logic circuit |
| EP0511711A3 (en) * | 1991-05-01 | 1995-03-15 | Philips Nv | Programmable combinational logic circuit |
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