JPS60110160A - Static induction type thyristor - Google Patents

Static induction type thyristor

Info

Publication number
JPS60110160A
JPS60110160A JP21902683A JP21902683A JPS60110160A JP S60110160 A JPS60110160 A JP S60110160A JP 21902683 A JP21902683 A JP 21902683A JP 21902683 A JP21902683 A JP 21902683A JP S60110160 A JPS60110160 A JP S60110160A
Authority
JP
Japan
Prior art keywords
type
impurity concentration
concentration region
electrode
impurity density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21902683A
Other languages
Japanese (ja)
Inventor
Isao Yoshino
功 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21902683A priority Critical patent/JPS60110160A/en
Publication of JPS60110160A publication Critical patent/JPS60110160A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066Gate region of field-effect devices with PN junction gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To increase the voltage gain and to readily control a current by partly forming a high impurity concentration region in a low impurity concentration region from the first electrode. CONSTITUTION:An anode electrode 1, a P type high impurity concentration region 2, an N type impurity or N type low impurity concentration region 3, an N type high impurity concentration region 4, a cathode electrode 5 and a gate electrode 9 are provided. A P type high impurity concentration region 6 is buried dispersively in the N type impurity or N type low impurity concentration region 3, and a P type high impurity concentration region 8 of a current control electrode is formed in the region 3 from the electrode 5. Thus, the pinch-off of a depletion layer is facilitated between gates, the abrupt implantation or stop of carrier can be performed by the high or low potential barrier, the voltage stopping gain is improved, and the current can bae turned ON or OFF in a short time.

Description

【発明の詳細な説明】 本発明は静電誘導型サイリスタに係シ、特にそのゲート
(キャリアを制御する電極及び不純物密度領域)構造に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic induction thyristor, and particularly to its gate (electrode for controlling carriers and impurity density region) structure.

従来の静′に誘導型サイリスタ、即ち埋込みグー)8I
サイリスタは、第1図に示すように、n型不純物もしく
はn型低不純物密度領域3にP型高不純物密度領域6が
分散状に埋込まれた構造であった0同量図において、前
記領域3の一生面に番まP型高不純物密度領域2が形成
され、さらに陽極電極1が設けられている。イし主面に
はn型高不縄物密度領域4が形成され、さらに陰極電極
5が設けられている。またP型高不純物密匿領域6は埋
込みゲート端子7に接続されている。
Conventional statically induced thyristor, i.e. embedded (G) 8I
As shown in FIG. 1, the thyristor has a structure in which a p-type high impurity density region 6 is embedded in an n-type impurity or n-type low impurity density region 3 in a dispersed manner. A P-type high impurity density region 2 is formed on the entire surface of the electrode 3, and an anode electrode 1 is further provided. An n-type high impurity density region 4 is formed on the main surface of the plate, and a cathode electrode 5 is further provided. Further, the P-type highly impurity-concentrated region 6 is connected to a buried gate terminal 7.

この様な構造では、電圧阻止利得を大きくするためにチ
ャンネル幅を狭くすると、定格電流が小さくなるという
問題がある。また、チャンネル幅を拡大すると゛a電圧
利得低下し、大電流をターンオフ(導通状態から阻止状
態への移行)できないという欠点があった。
In such a structure, there is a problem that when the channel width is narrowed in order to increase the voltage blocking gain, the rated current becomes small. Furthermore, when the channel width is increased, the voltage gain (a) decreases, and a large current cannot be turned off (transition from a conducting state to a blocking state).

本発明の目的は、これらの欠点を改良して、電圧利得を
増大させ、もって電流の制御が容易にできる静電誘導型
サイリスタを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an electrostatic induction thyristor which can improve these drawbacks, increase voltage gain, and thereby facilitate current control.

本発明は、第1の電極下に一導−Iiim高不純物密度
領域と一導電型低不純物密度領域とが順に接続され、前
記低不純物密度領域中に逆導電型領域が分散状に埋め込
まれた静電誘導型サイリスタにおいて、前記第1の電極
の方から前記低不純物密度領域中に逆導電型の高不純物
密度領域を部分的に形成したことを特徴とする静電誘導
型サイリスタにある。
In the present invention, a high impurity density region of one conductivity type and a low impurity density region of one conductivity type are sequentially connected under a first electrode, and regions of opposite conductivity type are embedded in a dispersed manner in the low impurity density region. The electrostatic induction thyristor is characterized in that a high impurity density region of an opposite conductivity type is partially formed in the low impurity density region from the first electrode.

次に図面を参照しながら本発明の詳細な説明する。Next, the present invention will be described in detail with reference to the drawings.

第2図は本発明の実施例の静電誘導型サイリスタを示す
断面図である。
FIG. 2 is a sectional view showing an electrostatic induction thyristor according to an embodiment of the present invention.

同図において、本静電誘導型サイリスタは、陽極電極1
、P型窩不純物密度領域2.n型不純物もしくはn型低
不純物密度領域3、n型高不純物密度領域4.陰極電極
5、ゲート電極9とを有し、このn型不純物もしくはn
型低不純物密度領域3にP型窩不純物密度領域6が分散
状に埋込まれ。
In the figure, the electrostatic induction thyristor has an anode electrode 1
, P-type cavity impurity density region 2. n-type impurity or n-type low impurity density region 3, n-type high impurity density region 4. It has a cathode electrode 5 and a gate electrode 9, and this n-type impurity or n
P-type cavity impurity density regions 6 are embedded in a dispersed manner in the type low impurity density region 3.

陰極電極5の方からn型不純物もしくはnff1低不純
物密度領域3に%;流制#電極であるP壓高不純物密度
領域8を形成したものである。例えば、P型窩不純物密
度領域2,6.8及びn型高不純物密度領域4の不純物
密度が1×2020crrL−1そしてn型低不純物密
度領域3の不純物密度がlXlO121 儂 、ゲート間隔は10〜20μn1とする。
From the cathode electrode 5, a P-high impurity density region 8, which is a flow control electrode, is formed in the n-type impurity or nff1 low impurity density region 3. For example, the impurity density of the P-type cavity impurity density regions 2 and 6.8 and the n-type high impurity density region 4 is 1×2020 crrL−1, the impurity density of the n-type low impurity density region 3 is lXlO121, and the gate interval is 10~ It is assumed to be 20 μn1.

このような構造にすることによシ、グート間の空乏層の
ピンチオフを容易にし、電位障壁の胃低によって急激な
キャリアの注入、!止をcIT能にする。これによシミ
圧阻止利得が向上し、短時間で電流のオン、オフができ
るし、またゲートIIII槓が広いので空乏層のピンチ
オンしている距離が長く。
Such a structure facilitates the pinch-off of the depletion layer between the grooves and the rapid carrier injection, due to the lower potential barrier! cIT function. This improves the impedance blocking gain, allowing the current to be turned on and off in a short time, and since the gate III is wide, the pinch-on distance of the depletion layer is long.

高耐圧化が可能となる。High voltage resistance is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の靜1妨導型(埋込みグー) 81)サイ
リスタの断面図、第2図は本発明の実施例の靜′FM、
誘導型サイリスタの断面図である。同図において、 1・・・・・・陽極電極、2・・・・・・P型尚不純物
密展領域、3・・・・・・n型不純物もしくはnii不
純物密度領域。 4・・・・・・n型高不純物密度領域、5・・・・・・
陰穐′g憔、6・・・・・・P型高不純物密度領域、7
・・・・・・埋込みゲート端子、8・・・・・・P屋高
不純物密度領域、9・・・・・・ゲート電位。 第 1 凹 第 2 図
Fig. 1 is a cross-sectional view of a conventional thyristor of the 1-disturbance type (embedded type);
FIG. 2 is a cross-sectional view of an inductive thyristor. In the figure, 1... Anode electrode, 2... P-type impurity dense region, 3... N-type impurity or nii impurity density region. 4...N-type high impurity density region, 5...
Yin 穐'g憔, 6...P-type high impurity density region, 7
. . . Buried gate terminal, 8 . . . P high impurity density region, 9 . . . Gate potential. 1st concave 2nd figure

Claims (1)

【特許請求の範囲】[Claims] 第1の電極下に一導電型高不純物密度領域と一導電型低
不純物密度領域とが順に接続され、前記低不純物密度領
域中圧逆導電型領域が分散状に埋め込まれた静電誘導型
サイリスタにおいて、前記第1の電極の方から前記低不
純物密度領域中に逆導電型の高不純物密度領域を部分的
に形成したことを特徴とする静電誘導型サイリスタ。
A static induction thyristor in which a high impurity density region of one conductivity type and a low impurity density region of one conductivity type are sequentially connected under a first electrode, and medium voltage opposite conductivity type regions are embedded in a dispersed manner in the low impurity density region. 2. The electrostatic induction thyristor according to claim 1, wherein a high impurity density region of an opposite conductivity type is partially formed in the low impurity density region from the first electrode.
JP21902683A 1983-11-21 1983-11-21 Static induction type thyristor Pending JPS60110160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21902683A JPS60110160A (en) 1983-11-21 1983-11-21 Static induction type thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21902683A JPS60110160A (en) 1983-11-21 1983-11-21 Static induction type thyristor

Publications (1)

Publication Number Publication Date
JPS60110160A true JPS60110160A (en) 1985-06-15

Family

ID=16729087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21902683A Pending JPS60110160A (en) 1983-11-21 1983-11-21 Static induction type thyristor

Country Status (1)

Country Link
JP (1) JPS60110160A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS637670A (en) * 1986-06-27 1988-01-13 Sanken Electric Co Ltd Field-effect semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS637670A (en) * 1986-06-27 1988-01-13 Sanken Electric Co Ltd Field-effect semiconductor device

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