JPS60109907A - Mixed two-frequency oscillating circuit - Google Patents

Abstract

PURPOSE:To vary a fundamental frequency and also to output a mixed two-frequency signal by reading a data stored in a ROM at an optional step. CONSTITUTION:A sin wave data of 801 sampling between 0-pi/2 is stored in the ROM2 as 0-4096 for example. An address signal advanced sequentially by the preset step number P is generated from an address generating section 1 and the sin wave data stored in the ROM2 is read and converted into an analog signal by a DA converter 3. When the sin wave is read from the ROM2 by the address signal advanced continuously by the set step number P a sinusoidal wave signal is outputted from the DA converter 3 and since the circuit is constituted that data 0 is inputted to the DA converter 3 once per twice, a 2-frequency signal is outputted from the DA converter 3 in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a mixed two-frequency oscillation generator whose oscillation output signal is a signal obtained by mixing signals of three predetermined frequencies.

Prior Art and Problems Three-frequency signals have various uses. For example, when testing modems, by adding three-frequency signals, it is possible to simultaneously test the characteristics corresponding to each frequency component.
It is. A tone signal based on a three-frequency signal is also used. To generate such a three-frequency signal, it is common to combine oscillation signals of each frequency, but this requires an oscillator to oscillate a signal of each frequency, which poses a cost problem.

Also known is a configuration in which sine wave data is stored in a ROM (read only memory), read out using an address signal that advances in predetermined steps, and converted into an analog signal. Rather than storing it, it is also possible to generate a three-frequency signal. However, such a configuration has the disadvantage that the frequency cannot be made variable.

Purpose of the Invention The object of the present invention is to make it possible to vary the fundamental frequency and output a mixed three-frequency signal by not reading data stored in a ROM at any arbitrary step. be.

Structure of the Invention The present invention is configured to include a memory that stores sine wave data, a DA converter that converts the sine wave data successively output from the memory into an analog signal waveform, and a successive address signal of the memory. It is provided with means for generating data by increasing the number of steps and setting data input to the DA converter to 0 every two times.Examples will be described in detail below.

Embodiment of the Invention FIG. 1 is a schematic block diagram of an embodiment of the invention.
2 is an address generator, 2 is a ROM, and 3 is a DA converter. As shown in Figure 2, ROM2 has 8 bits between 0 and π/2.
For example, if the sine wave data of 01 sampling step is 0
~4096. The address generator 1 generates an address signal that is sequentially incremented by a preset number of test steps P, and the sine wave data stored in the ROM 2 is read out and converted into an analog signal by the DA converter 3.

When sine wave data is read from the ROM 2 using an address signal that continuously advances by a set number of steps P, a sine wave signal will be output from the DA converter 3. It is configured such that 0 data is input to the DA converter 3 once every
The A converter 3 outputs a three-frequency signal.

For example, if sine wave data is read out from the ROM 2 by sequentially generating address signals with a set number of steps P, the result will be a sine wave signal as shown in (al) in FIG. By inputting O data to the DA converter 3 once at a time, a three-frequency signal as shown in (bl) in FIG. 3 is output.

As mentioned above, when sampling between 0 and π/2, the step is 801, and the sampling frequency is 8 KHz, the fundamental frequency λ is P x 2.5. Also DA
When data that is 0 every second time is input to the converter 3, a three-frequency signal with the same fundamental frequency λ (KHz) and frequency (4-λ) (KHz) mixed by a bell is output. . For example, if the number of steps P is 500, the fundamental frequency is 1
A three-frequency signal that is a mixture of a 250 Hz signal and a 2750 Hz signal is output.

The sinusoidal function with a sampling frequency f of 8 KHz is
It is given by s in (2yrf/8000)n.

Note that n indicates the T1th sample. Now, 4
00(1. Considering synthesis with a sine wave of frequency 1-f.
Setting 2πf/8000=θ, the following equation is obtained.

sinθn+5in(πn-θn)=sinθn+
sinπn-cosθn-5inθn'cO3πn = (1-cosycn) ・s inθnHere, T
If l is an odd number, (1-(: OS-πn)"2 If n is an even number, (1-cosyrn) = 0. That is, by outputting 0 once every two times, , f
, 4000-f have been synthesized.

FIG. 4 is a block diagram of one embodiment of the present invention, with 10
1 is a step setting section, 11 is an address calculation section, 12 is an address control section, 13 is a control circuit that controls each section, and 14 is a s
A ROM 15 stores in-wave data and is a DA converter. A step number P is set in the step setting section 10,
This step number P and an address signal C for accessing the ROM 14 are applied to the address calculation section 11. The address calculation section 11 adds the step number P and the address signal C, and adds the output signal S to the address control section 12 and the control circuit 13.

If the sine wave data stored in RC>M14 has 800 steps between 0 and π/2 as shown in FIG. It outputs control signals d and e by identifying whether the signal b' is equal to or less than O, and outputs a control signal f by identifying that the signal b' has been output twice.

When the signal value indicates 800 or more, the address control section 12 outputs the address signal C based on the calculation of (1600-signal b) using the control signal e. Further, the address calculation unit 11 calculates the number of steps P from the step setting unit 10 by the control signal d.
The sign of is inverted and added to the previous address signal C, and the resulting signal C is output.

Further, when the signal S indicates 0 or less, the address control section 12 inverts the sign of the signal S using the control signal e and outputs the address signal C.
and the sign bit g applied to the DA converter 15 is inverted. As a result, the DA converter 15 outputs an analog signal whose polarity is inverted. Further, the address calculation section 11 inverts the sign of the step number P from the step setting section 10 according to the control signal d, adds it to the previous address signal C, and outputs the resultant signal S.

Also, when it is determined that the signal has been output twice, the control circuit 13 sends the control signal f to the address calculation section 11 and the address control section 12, and the address control section 12 uses the control signal f to The address signal C in which the O data of the ROM 14 is stored is outputted so that the data of 0 is input to the DA converter 15, and the address calculation unit 11 inputs the step number P to the previous address signal C without reading out the 0 data. Outputs a signal with the calculated value twice.

FIG. 5 is an explanatory diagram of the operation of the embodiment of the present invention. As mentioned above, sine wave data of 800 sampling steps between 0 and π/2 is stored in the ROM 14, and sine wave data of 800 sampling steps between 0 and
This shows a case where the address where the data is stored is "0" and the number of steps P set in the step setting section 10 is 300. In addition, (a) includes the sign bit g,
Positive and negative DA and input data to the converter 15 are shown, and the dotted line shows the case where 0 data is output. Also (b
) to fgl show an example of the signals b-H of each part in FIG.
When the address signal co from the address control unit 12 is "6" indicating the 0 data storage address (as shown in C1), the signal from the address calculation unit 11 is 300 is obtained by adding the number P of 300, and the address signal c1 from the address control unit 12 becomes "300" which is the output of the signal S as is (as shown in C1).

After the signals 0 and 300 are output from the address calculation unit 11, the control circuit 13 indicates that the signals 0 and 300 have been output twice.
Since the control signal f shown in fl is applied to the address calculation unit 11 and the address control unit 12, the address control unit 12 stores 0 data even if the signal is 300 + 300 = 600. Address “0” is the address signal C2
Output as . In addition, in the next calculation, the address calculation unit 11 uses the address signal C2 of "0" and the step number P of 3.
It does not add 00, but the previous calculation result of 60
0, and add 30 to this 600, which is the step number P.
Adds 0 and outputs a signal. That is, address signal C
The signal is 900, which is the value obtained by adding 300, which is the number of steps P, to I twice.

When the signal length becomes C100+300=900, the control circuit 13 recognizes that the signal length is 800 or more and outputs control signals d and e. That is, as shown in (d), b >
When determination 800 is made, control signals d and e are output. The address control unit 12 uses this control signal e to
, (1600-signal b) address signal C3
Output. In the tel, it is shown as (1600-b). Therefore, the address signal C3 of "700"
will be output. In addition, in the address calculation section 11, in the next calculation, the sign of the step number P is inverted and added to the address signal C3 according to the control signal d, so that the signal number becomes 400. For this signal C4, the address control section 12 outputs it as is as an address signal C4.

Next, in the address calculation section 11, the previous address signal C4
The number of steps P with the sign reversed is added to the signal S, and the control circuit 13 outputs the control signal f, since the signal S is output twice, and -1 With this control signal f,
The address control unit 12 outputs an address signal C5 of "0" at the 0 data storage address. Further, in the next calculation, the address calculation section 11 outputs a signal representing the calculation result of 100-300=-200. The control circuit 13 uses this signal θ
It identifies the following and outputs control signals d and e.

In (d), the change in the control signal d is shown by determining that the signal level is 0 or less when b<Q.

In response to this control signal e, the address control section 12 inverts the sign of the signal S, outputs an address signal c6 of "200", and inverts the sign pg as shown in (gl).

In tel, bx(-1) indicates that the sign of the signal is inverted. In addition, in the next calculation in the address calculation section 11, the sign of the step number P is inverted and added to the previous address signal C6, so the step number P has the same sign as the first, that is, a positive sign. The signal number is 200+300=500.

This signal 500 is directly output from the address control section 12 as an address signal C7. A signal of 800, which is the sum of this address signal C7 and the number of steps P, is output from the address calculation unit 11, but since signals of -200 and 500 are output, the control circuit 13 outputs the control signal f.
As a result, the address control unit 12 outputs an address signal C8 of 0''.

Next, in the address calculation section 11, 800+300=110
It will output a signal of 0, and this signal will be 800.
As described above, the control circuit 13 outputs the control signals d and e, and the address control section 12 outputs the control signals d and e.
The calculation result of eoo-1xoo-500 is sent to the address signal c.
Output as 9. The address calculation unit 11 inverts the sign of the step number P using the control signal d and adds it to the address signal c9, so that the next signal is 500-300,
= 200. This signal S is directly output from the address control section 12 as the address signal CIO. The calculation result of this address signal clO and the number of steps P is 2
0 (1-300=-100, and the control circuit 13 has b>
When Q is identified, the control signals d and e are output, and since this is the second time, the control signal f is output.As a result, the address control unit 12 outputs the address signal C1l of "0", and the code bit is ) g is inverted.

As mentioned above, in the address calculation section 11, the signal
The control signal d when the number is 0 or more inverts the sign of the step Hp and adds it to the previous address signal C, and the control signal d when the number is 0 or less inverts the sign of the step number P and adds the previous address signal C. Addition is performed with the address signal C, and after the two calculations, the calculation result is stored using the control signal f and addition is performed with the next step number P.

Further, in the address control section 12, the operation result of (1600-signal b) is set as the address signal C by the control signal e when the signal S is 800 or more, and the sign of the signal S is inverted by the control signal e when the signal S is 0 or less. is used as address signal C and inverts the sign pitch +-g, and the control signal f is used to output address signal C in ROM 14.
It outputs an address signal C of a data storage address. Therefore, the sign bit g is (+) as shown in Tgl.
and (-), indicating positive and negative polarity,
Corresponding to this code pitch Ig, the DA converter 15 converts RO
The read data of M14 is converted into an analog signal and output.

As mentioned above, if the number of steps P is 300, the fundamental frequency λ is 750 Hz, and the mixing frequency is 325.
It becomes 0Hz. That is, a mixed three-frequency signal of 750 Hz and 325'OH2 is output from the DA converter 15. As mentioned above, since the number of steps P can be set arbitrarily, the fundamental frequency λ can be arbitrarily selected, and a three-frequency signal that is a mixture of signals with frequencies that have a certain relationship with this fundamental frequency λ can be generated. can be output. Furthermore, by changing the sampling frequency, the fundamental frequency λ can also be changed.

FIG. 6 is a block diagram of another embodiment of the present invention;
0 is a step setting section, 21 is an address calculation section, 22 is an address control section, 23 is a control circuit, 24 is a ROM, 25 is a switching circuit, 26 is an O data storage section, and the DA converter is not shown. There is. The address calculation unit 21 calculates the number of steps P set in the step setting unit 20 and the address signal C from the address control unit 22, and sends a signal of the calculation result to the control circuit 23 and the address control unit 22. ,
The control circuit 23 determines whether the signal is greater than or equal to 800 or less than or equal to 0, and outputs control signals d and e. After the signal is output twice, it outputs a control signal f, and this control signal f is output. This is added to the switching circuit 25. The switching circuit 25 switches between the read data of the ROM 24 and the 0 data stored in the 0 data storage section 26, and applies the data to a DA converter (not shown).

The address calculation section 21 performs calculations between the previous address signal C and the set number of steps P, and performs calculations by inverting the sign of the number of steps P using the control signal d.

The signal S as a result of this calculation is applied to the address control section 22 and the control circuit 23, and control signals d and e are output depending on the determination result of whether the signal S is 800 or more or 0 or less, and the address The control unit 22 uses the control signal e when the value is 800 or more to make the calculation result of (1600-signal b) an address signal C, and uses the control signal e when the value is 0 or less to invert the sign of the signal and use it as the address signal C. and sign p+-g
This is to reverse the .

In addition, the control circuit 23 applies the control signal f to the switching circuit 25 by sending the signal twice, and instead of the successive data of R and 0M24, the O data from the 0 data storage section 26 is sent to the DA converter (Fig. (not shown).

In this embodiment as well, since the number of steps P can be set arbitrarily, the fundamental frequency can be arbitrarily selected, and a three-frequency signal can be output.

In the embodiment shown in FIG. 4, a means for generating an address signal for a 0 data storage address is provided between the address control section 12 and the ROM 14, and after accessing the ROM twice, the address control is performed. Instead of the address signal from section 12,
From this means, the address signal of the 0 data storage address is transferred to the ROM.
It is also possible to have a configuration in addition to 14.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention includes a memory such as a read-only memory ROM2.14.24 that stores sine wave data, and a DA that converts the sine wave data read from the memory into an analog signal waveform. A converter 3.15 converts the read address signal of the memory into a preset number of steps P.
and means such as an address control section, an address calculation section, or a 0 data storage section 26, which sets the data input to the DA converter to 0 every two times. An arbitrary fundamental frequency can be selected according to the number of steps P, and a three-frequency signal obtained by mixing signals of other frequencies at the same level as the signal of this fundamental frequency can be output.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, and FIG. 2 is a schematic block diagram of an embodiment of the present invention.
An explanatory diagram of in-wave data, Fig. 3 (al, fb) is an explanatory diagram of operation, Fig. 4 is a block diagram of an embodiment of the present invention, Fig. 5
Figures fa) to fg) are explanatory diagrams of the operation of the embodiment in Figure 4;
The figure is a block diagram of main parts of another embodiment of the present invention. l is address generation section, 2, 14.24 is ROM, 3.1
5 is a DA converter, 10.20 is a step setting section, 11.
21 is an address calculation section, 12 and 22 are address control sections,
13.23 is a control circuit, 25 is a switching circuit, and 26 is a 0 data storage section. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 4 (9) Trouble (-) Figure 6 Procedural Amendment September 18, 1980 Commissioner of the Patent Office Shiga Gakuden 1 Indication of the case Patent Application No. 217101 of 1982 Name of the invention Mixed three-frequency oscillation circuit 3 Relationship between the person making the amendment Patent applicant address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name ( 522) Fujitsu Limited Representative Takuma Yamamoto 4 Agent Address 20-7-6 Toranomon-chome, Minato-ku, Tokyo Subject of amendment Detailed explanation of the invention in the specification (1) Specification No. 8
In lines 13 to 16 of the page, [300 was added as shown] is corrected as follows. 0 as shown in , and once every two address calculations, the control circuit 3 sends a control signal f as shown in (fl).
is output and applied to the address calculation section 11 and address control section 12, so the address signal cQ from the address control section 12 is "0" indicating the 0 data storage address (as shown in C1). Since this address signal co is also applied to the address calculation unit 11, the next signal from the address calculation unit is calculated by adding the step number P of 300. Page 12, line 18, "For...is inverted." is corrected as follows. For [, the control signal f is output once every two times, so the address signal c4 is “0” indicating the 0 data storage address.
''. Next, the address calculation section 11 calculates the previous address signal C4.
is "0", but as in the case described above, 1 is output, and 100 is output, which is the sum of 300, which is the number of steps P whose sign is inverted, to the signal 400 when this address signal c4 is output. Since the control signal f is not outputted, the signal S from the address calculation section 11 at this time is outputted as is from the address control section 12 as the address signal C5. Next, the address calculation section 11 calculates the previous address signal C5.
The number of steps P with its sign reversed is added to 10.
A signal of 0-300--200 will be output. The control circuit 13 identifies that the signal S is negative and outputs the control signals d and e. In Figure 5 (dl),
As shown by b<o, the control signal (1) changes due to the determination that the signal level is 0 or less. Also, the address control unit 12 changes the signal level to -1 based on the control signal e. The signal is inverted and output, and the sign bit g is inverted as shown in (g).The control signal e inverts the sign of the signal S as shown by bx (-1) in tel. Then, by outputting the control signal f once every two times, the address signal C6 becomes "0" indicating the 0 data storage address.Next, the address calculation section 11 , previous address signal c6
is 0'', but as described above, this address signal C6
300, which is the number of steps P, is added to the signal when is output. Therefore, the signal from the address calculation section 11 is
200+300=500. At this time, the control signal f
Since the signal is not outputted, it becomes the address signal C7 and is outputted from the address control section 12 as it is. Next, the address calculation section 11 outputs 800, which is the sum of this address signal C7 and the step number P. In this case as well, the address control unit 1
An address signal c8 of "0" is output from 2 to 2. Next, in the address calculation section 11, 800+300=110
Since a signal line of 0 is formed and the signal line is 800 or more, the control circuit 13 outputs control signals d and e. The address control unit 12 receives 16oo by this control signal.
-+too-sO. The calculation result is output as address signal C9. Further, in the address calculation section 11, the sign of the step number P is inverted by the control signal d and added to the address signal C9, so that the next signal becomes 500-300-200. This signal S is output from the address control section 12 as an address signal CLO of "0" by the control signal f once every two times. Next, in the address calculation section 11, since the previous signal is added to the step number P whose sign is inverted, 2
It becomes 00-300--100. In the control circuit 13, control signals d and o are determined based on b<o.
Output. As a result, the sign of the signal -100 is inverted and becomes 100, and since the control signal f is not output, it becomes the address signal C1l as it is. Also, the sign bit g is inverted as shown in gl. (3) Correct the drawing in Figure 5 as shown in the attached sheet.

Claims (1)

[Claims] A memory that stores sine wave data, a DA converter that converts the sine wave data successively output from the memory into an analog signal waveform, and generates the successive address signals of the memory by stepping them by a preset number of steps. A mixed two-frequency oscillation circuit characterized in that the mixed two-frequency oscillation circuit is provided with means for setting data manually inputted to the DA converter to 0 once every two times.