JPS60109794A - Drive circuit of stepping motor - Google Patents

Abstract

PURPOSE:To prevent an unnecessary noise voltage generated when providing a period in drive signals of phases by providing logic product circuits which generate drive signals with pause period. CONSTITUTION:A monostable multivibrator 6 triggered at the OFF time of a drive signal A' for deciding a pause period width of a drive signal for producing an OFF output T1 only during a sufficiently short time as compared with a half period of the drive signal, and a delay circuit 8 for delaying the ON timing of the drive signal A during the delay time of the triggering operation of the multivibrator 6 are provided, and a logic product circuit 7 which receives the output of the multivibrator 6 and the output of the delay circuit 8 and generates a drive signal Aout with a pause period to be applied to a stator coil instead of the drive signal inputted to the delay circuit 8 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a drive circuit for a stator hinge which generates a signal to be supplied to a stator coil of a stator 1, 6e and 6e.

[R scenery technology]

FIG. 1 shows a schematic diagram of a conventional two-phase STETSUHI J motor, and FIG. J2 shows the drive circuit for the Tanabata motor. FIG. 3 is an explanatory diagram of the same operation as above. In FIG. 1, (l) is a permanent magnet rotor, (2) and i
3] is a stator coil. One stator coil (
2) is the input phase and N' phase, the other stator coil (3)
constitutes the B phase and the B' phase, and is designed to be excited in both positive and negative polarities. As shown in Figure 2, the 7-Tano drive circuit has a counter (4) that counts the 0 inputs.
) and the outputs Q1 to Q4 of the counter (4) as address inputs, and the data outputs of 4 hits are input into the phases, A' phase, B phase,
Generated as each output of B' phase)1. OM, t51
It is composed of. The counter (4) is provided with a switching terminal for switching between tanabata (Tanabata) and reverse rotation depending on whether the counter (4) is incremented or incremented. FIG. 3 is an explanatory diagram of the operation during normal rotation of Tanabata. As shown in the figure, by counting the clock input CLK, the outputs Q1 to Q4 of the counter [4] are sequentially powered up. Then, the phases are entered, A' phase, B phase, B
The waveform of the 'phase changes as shown in the figure. The input phase and A' phase and the 13th phase and B' phase are in opposite phase to each other,
The input phase and the B phase and the A' phase and the B' phase are out of phase by a half period. By the way, in such a conventional example, the direction of the current flowing through the stator coils 12) and (3) suddenly changes at the moment when the A phase and the A' phase are switched, or at the moment when the B phase and B' phase are switched. If the phase is reversed, undesirable operation will occur due to back electromotive force, etc., so it has been proposed to provide a rest period in which both the on-phase and A' phase or the B and B' phases are off. FIG. 4 shows a circuit 11 that generates such a pause period, and in the same figure, (6)
is a monostable multivibrator, and (7) is an acid gate. Monostable multipolarizer +61? When the 'iA' phase falls, a tri-force is applied and 'r1 is held low for a minute period.
I will do it as a bell. Therefore, even if the phase rises, the upper J1
During the 2 m short period, the output Aout of the anti-game controller remains at the L level, and after the lapse of the above-mentioned short period, it reaches the output voltage level 7outV'id. If the output N'out is created with a similar circuit configuration for the A' phase, the drive term h1 bar signal A out , A'ou with a rest period +gJ at the time of switching
t is equal to fL. 13444, using the same concept for the B' phase, it is possible to obtain the drive signals 13 out and B'out that have a pause period during reciprocation (
(See Figures 45 (a) to (d)). But 6 Vc iA 4
+MI, y) In the case of the circuit example, I′i theoretically operates as positive A, but in reality there is a delay in the trigger operation of the monostable multiplier (〇), so the instantaneous noise voltage The disadvantage is that this occurs on the output side. Figure 6 (
a) to (d) are diagrams of its operation, and the phase input and A
'When the phase switches as shown in the same figure (al (b)),
The outputs 'r and H of the monostable multivibrator (6) rise with a slight delay. Just because I wanted to, I entered the phase oh 7
(H level) When it is about to reach K, the way it comes out = l
Since a state in which l, is not completely off (L level) occurs instantaneously, an unnecessary noise voltage v0 is generated in the waveform of 8out, which is the loss of the transistor in the first stage of the driver, and There was a value of 1 for a long time when it became the cause of dl14 excitation.

[Purpose of the invention]

The present invention was created in view of the above-mentioned points, and it is possible to prevent unnecessary noise voltage from occurring by providing - (stop output) for the drive signal t1g of each phase. The object of the present invention is to provide a drive shaft circuit for the Stereo-9.

[Disclosure of the invention]

The configuration of the present invention will be explained below with reference to the illustrated real-time signal 1j.-As shown in FIG. Rest period of the generated drive signal [1] A monostable multi-channel generator (4) for deciding, and each! Misaki (Do 100 No. 100 Oshitai 3, 17ri 1 Maru 1000 Pipe 1 Nota (6)
A delay circuit (8) is provided which delays the trigger operation by 11], so that each monostable 71 and 1,000 bytes have a delay circuit (8).
The output of el and the drive signal that triggers the monostable multivibrator (6) are the output and input of the delay circuit 18) which uses the drive I##l signal, which is in opposite phase to the drive signal that triggers the monostable multivibrator (6). , an AND gate (7) is provided which generates a drive signal with a rest period applied to the stator coil I21 t31 in place of the drive signal inputted to the d extension circuit 181Vc. In the rigid series shown in figure a7, the circuit list 8) is composed of resistors It, , R2, condenser C2 diode D, and isciverter +9111LI), resistor I is also 1, and hexadecimal C is an integrating circuit. It consists of The time constant of this integrator circuit is set sufficiently small, and the trigger operation of the monostable multivibrator (6) is
It is set at about the same level as Yruji Moe. 4s +g1;
FIG. 7 is an explanatory diagram of the operation of the 7-diagram circuit. Now, when the N' phase drive signal switches from O7 (H level) to Off (LL/Bell), the fall of the monostable multivibrator (6) is retriggered, and its output = ll becomes a predetermined level. It becomes L level only during the rest period. On the other hand, at this time, the input phase drive signal VC switches from off (L level) to on (H level), so the output of the inverter (9) changes from H level to L level.
Switch to level. However, the inverter (9)
Since an integrating circuit consisting of a resistor R1 and a sensor C is connected to the output side of the sensor C, the light heavy voltage V of the sensor C is
C does not bark in the uras and ridges, and slowly lowers F as shown in Figure 48. However, when the light pressure of the coefficient C falls below the threshold level Vth shown by the dotted line in FIG. 8, the output 4d of the inverter 110 changes from the L level to the I level. While the output id of the inverter (10) is L and is a bell, the output A of the 7nd gate (7)
Naturally, out is L level 11. Therefore, even in tie 3-J, where the input drive signal 1g goes to the H level and the output 'L'1 of the monostable multivibrator lfi+ has not yet completely reached the L level, the inverter 110+ Since the output Ad is still at the L level, unnecessary noise pressure is not generated on the output side of the AND gate (7) as in the past. Then, if the output of this inverter:10) becomes Ad7J)l (level), and the output 'V□ of the multivibrator (6) goes to H level, the output of Pnt□ gate I7) Aou
t becomes 1 (bevel). (K and ζl Therefore, ]:, / diode C is diode D
The output A of the inverter 11ω is passed through the
Since d immediately returns to the L level, the output of the AND gate (7) also immediately returns to the L level jlJ. Therefore, 71 "I'm in trouble" without causing unnecessary noise 11 pressure and 711 thousand vibrators 16)
It is possible to obtain a driving signal that changes lJ to fj -4- during one stop determined by . The drive signal Δ' completes a predetermined rest period depending on the road configuration.
Out%Bout and B'out can be used.

FIGS. 9(a) and 9(b) show an example of a circuit other than the invention for creating a drive signal with a pause period.
Figure <a) is a circuit for creating the stop period No. 1a, in which the clock pulse is manually applied to the rest period of A' phase + ul I phase No. ゛ P, and the rest period of B phase and B' phase. Two signals 'r' are respectively generated. FIG. 10 is an explanatory diagram of the rest period 1tl signal generation circuit shown in FIG. 1(a).

First, the clock pulse is inverted in a buffer stage consisting of an inverter (1) and becomes Ichikawa v1. This direct pressure V
1 is input to an integrating circuit consisting of an ore it and a condenser IjC, and the direct 1fVC output from this integrating circuit is inputted to an inverter 112). , Intimidating VC is Haji 1
When the threshold level Vt11 indicated by point +U in Figure 0 is exceeded, the output of the inverter 112) becomes L level I+7, and M and the ratio IJc reach the above threshold level y:31.
When the output voltage of the inverter C becomes smaller than th, the output of the inverter C becomes 1 (level). The output of the inverter 114j, which causes the inverter 114j to invert, shows the change in pressure.
) is applied to the -10,000 input of the Nant gate 1J6), and is also applied to one of the Nant gates 06) via the inverter t13). In addition, the output voltage of the inverter 11 is V, and the output voltage of the inverter 11 is
G) (I) Applied to the open input and also via the inverter 114)? / #J is connected to the curved blade input of gate t151. Therefore, from the Nant gate 151161, the resting phase il1 times '1'2 and [+1 are shown in FIG. 10, respectively. Each rest period signal 11. , 'v2 is shown in Figure 9 (bj
is input into a cooking circuit as shown in . One pause period 1
It is applied to the human power of one side of the country, and the physical power of the other side is applied. Between A 18
No. 'L', l-, i acid gate +19) and applied to one input of steel. In addition, the other input of each AND gate 咥~此0) is &4[,,,&'phase,B
+4j is added to each of the phase and B' phase drive signals. Therefore, on the output side of each Ashitoge-1-,, +7) to 2f++, there is a resting period 1 river, respectively, Nout,
'71' out, 13 out, f3' out,
It is possible to do fF'i. 411 figure is -49
This is an explanatory diagram of ・1・J1 of the circuit in FIG.
A drive signal A in which each of the A' phase, B phase, and B' phase drive signals does not pass through the acid gate Jη~(2o) and has a pause period as shown by the dotted line in the figure.

ut, 71'ciut, 43 out, B'
Out is something that cannot be obtained. In addition, from Fig. 9, fi
In each of the diagrams in FIG. 11, the inverted signal q1 of the output Q1 of the cursor (4) of the circuit in FIG. 2 is used as the black pulse.

By the way, in the issue creation circuit between the main lines in FIG. 9(a), the threshold of the inverter +I21
1 is assumed to be 1/2 of the maximum if & of the Vc of the core/7' sensor C, as is clear from the I operation diagram in Figure 10. [When it is cold, the pause period signal ′[□, ′[
The width will be 12 different. The pause period signal generation circuit shown in FIG. 12 takes this point into consideration, and even when the threshold level vt11 of the inverter (12) is low, the widths of the pause period signals '11□ and P2 are made to be the same. This is what I did. In the circuit shown in FIG. 1A12, a series circuit of a resistor R4 and a diode D is connected in parallel with the resistor as a circuit for leaving the cosidenser C. Therefore, the voltage VC of the converter C is slightly acidic during charging.
However, during discharge, tumors and tumors appear as shown in Figure 13.
It descends quickly. Therefore, the inverter (I2
) is smaller than 1/2 of the maximum value of VC2 formed by the small diameter C, as shown by the dotted line in Fig. 413, and even when vb>va, the resistance R3
, by setting the resistance value of the tow to an appropriate value, the dormant period 1
...The widths of the signals 'v1 and 'r2 can be made the same.

〔Effect of the invention〕

The present invention is constructed as described above, and! A monostable multi-byte generator is used to create the rest period of the drive signal, which is triggered when the drive signal is off, and produces an off output for a period of light minutes shorter than a half cycle of the drive signal. A delay circuit is provided to delay the trigger operation of the monostable multivibrator by IJI, and the output of each monostable multivibrator is a drive signal that is in opposite phase to the drive signal that triggers the monostable multivibrator. The stator coil is provided with an AND circuit which takes the outputs of the delay circuit and the output of the human-powered delay circuit as inputs, respectively, and generates a drive signal with a rest period that is applied to the stator coil in place of the drive signal input to the delay circuit. Therefore, even if there is a slight time delay in the trigger operation of the monostable multivibrator, the output of the delay circuit is off (1)], the output of the AND circuit will not become OFF, and therefore This has the effect that a drive signal having a rest period determined by a monostable multivibrator can be obtained without generating unnecessary noise voltages.

[Brief explanation of drawings]

Fig. 41 is a schematic configuration diagram of a conventional typical stage hinge Tanabata; Fig. 2 is a circuit diagram showing a conventional example of the same drive circuit;
FIG. 3 is an explanatory diagram of the same operation as above, FIG. 4 is a circuit diagram of a pause period creation circuit used in the conventional example above, and FIGS.
The figure is an explanatory diagram of the same operation as above, FIG. 7 is a main circuit diagram of an embodiment of the present invention, FIG. 8 is an explanatory diagram of the same as above, and FIG. 9 (a)
(b) is a circuit diagram of another drive circuit other than the present invention, FIGS. 10 and 11 are explanatory diagrams of the same operation as above, FIG. 12 is a circuit diagram of still another drive circuit other than the present invention, and FIG. is an explanatory diagram of the same operation as above. Ill is a permanent magnet rotor, I21 ill is a stator coil, (6) is a monostable multivibrator, (7) is an acid gate, and (8) is a delay circuit. Agent Patent Attorney Ishi 1) Chief 7 Figure 1 1 Figure 3 Figure 1 lower - L" - 10 - "" - Choichito Figure 6 Figure 7 Figure 8 th

Claims (1)

[Claims] A stepper roller having permanent magnets mutually magnetized to N and S poles at equal angular intervals in the circumferential direction, and a pair of stator coils that rotationally drive this permanent magnet rotor. A set of drive signals each consisting of a rectangular wave signal that is applied to one end of each of the stator coils 3 and having a phase difference of approximately 90 degrees, and a set of drive signals that are respectively applied to the other end of each stator coil and that are in opposite phase to each of the drive signals. In the drive circuit of the STUDIO PJ Tanabata that generates the drive signal, the rest period of the drive signal is tri-powered when each drive signal is off, and the OFF output is produced for a period sufficiently shorter than the half cycle of the drive signal. A monostable multivibrator for width determination and a delay circuit that delays the output of each drive signal by the delay time of the trigger operation of the monostable multivibrator are provided, and the output of each monostable multivibrator and , and the output of a delay circuit that receives a drive signal having a phase opposite to that of the drive signal that triggers the monostable multivibrator, respectively;
This patented Stehinter Tanabata drive circuit includes an AND circuit that generates a drive signal with a pause period that is applied to the stator coil in place of the drive signal that is input to the delay circuit.