JPS60109768A - Controller for pwm inverter - Google Patents

Abstract

PURPOSE:To bring the modulation factor into coincidence by rising or falling a voltage between lines of both inverter by the same carrier and voltage levels, thereby accurately displacing at 30 deg. the voltage between the lines of 0 deg. inverter and the voltage between the lines of 30 deg. inverter. CONSTITUTION:A comparator 4 compares a rising sawtooth wave (n) with a voltage level Vc, and the output D falls synchronously with the crossing point with Vc when the rising sawtooth wave (n) rises. The output D falls when the rising sawtooth wave (n) falls. The output z-D of a comparator 5 similarly rises or falls synchronously with the fall or rise of the falling sawtooth wave -n. Then, the rise of the line voltage between a 0 deg. inverter and 30 deg. inverter is alternately synchronized with the rise of the -D, and the phase voltages of the both interters are fallen or risen to control the line voltage between the both inverters.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a PWM semiconductor switch for an inverter device that can easily eliminate the fifth and seventh intermittent harmonics of an AC voltage in an inverter that converts DC power into AC power. Concerning the means of cape control.

[Background of the invention]

As a device for converting DC power to AC power, there is generally an inverter circuit that uses semiconductor switches such as transistors and thyristors.
o + Xo l YOI Yo + Zo + Zo
+ Xso + Xso + 'Ys. ,■,. , Z3
゜, n13゜ are wedge-shaped semiconductor switches, respectively.
o perform pairwise operations with each other.

Lln + Vo + VVo + LIso+ Vs
. , W30 is the phase voltage, U3O.

-Vxo, Sya. , are respectively TJo, Vo+~
・Control so that it appears to be ~0 and is delayed by 130 degrees. Father, the thickness of the voltage is IUol"IVol"IWol=
IUaol = 1V3(II”1Vv3o1...+
1) Control (wealth) so that it is equal to ↓. The I//RI and Tatra/S 1 are connected in a staggered manner, and their vector diagram is shown in FIG. Phase voltage 'J80+V! . ,■,. That's it
L.

30" behind the phase voltages IJo, Vo, Wo', 2 (
When 1) holds, the nth harmonic en is the output of I/·kutra/s1, and becomes as follows. As for the content rate of the n-th harmonic wave, it is known from equation (3) that there is no m 6 (211+1)±1st-order reprint wave. In this way, the phase voltage U30 +
V2O+W3n are each phase voltage U. , VO,Vv
6. When controlling so that the equation (11) holds with a delay of 306, as shown in Fig. 4, uo, VO + Llso
, Vso @ triangle (Et”o+ ”so and level V.

)'WfV
'JXrA1jj K Il of I waveform is fc v6
: level ve to o in Figure 4; nth harmonic content rate ε on the primary side of the triangular wave 0 amplitude inverter transformer 1 in Figure 4
ゎHowever, θl−60°−30°mem11θ2”600+
30° x I (1) From equation (3) and equation (5), the n-th intermittent harmonic content on the secondary side of the i7verter transformer 1 is as follows.

At this time, the resonant harmonic wave U of the parent ωt filter 2 in FIG. 1 is basically li! d wave number f. against 4 fo nito force and Al1
The attenuation rate ρ of the order cylinder harmonic is 1− (2π”o)2/12π4′o) and when n24, ρ=Button formula<6) and the formula (7J, l: 1.1 The output width of the AC filter 2 and the pressure distortion factor ε are as follows: ε≦3.8'16 fc′fcL,Kh,;,0.5, and a three-phase sine wave with a small distortion factor is obtained.

Next, the phase voltages Usnr Vso + Wso are delayed by 30° with respect to the phase voltages Uo, Vo, Vvn KT, respectively,
The phase voltage waveform U as shown in FIG. 4 is obtained by controlling the equation il+ so that it holds true. .

Traditional + to generate Vo, IJso, Vso k
The UII N1 circuit is shown in Figure 3.

The carrier wave generation circuit 31 generates a triangular wave 10'ff shown in FIG.
A triangular wave [. is the inverter output sine frequency f. (
Hereinafter, this will be referred to as the fundamental frequency. ), and its peak value is An. The carrier wave generation circuit 32 is the fourth
The triangular wave '30 shown in the figure is completely generated, and the triangular wave eLso is a triangular wave [. The phase is delayed f by 180° relative to
Its frequency is equal to the triangular wave 1o. Moreover, its peak value is A36. The feedback signal of the DC j5 width amplifier 33il-i/i/inverter output and the set value for setting the inverter output are used for all calculations. Yes, the comparator circuit 4 uses a triangular wave [.

and the voltage level vt 2, and its output is the 4th
K h in the figure.

It is. Ring cow 7 and 6 are comparison circuit 4 outputs Kb.

This circuit generates PWM waveforms (Xo, Yo in FIG. 4) k, and operates to determine which semiconductor switches (xo, Yo, etc. in FIG. 4) to commutate depending on the rise and fall of KhO. The comparison circuit 5 and the linog counter/tough are the same circuits as the comparison circuit 4 and the linog counter 6. The pulse amplifier 8 is a circuit for operating the semiconductor switch shown in FIG.
Ysn- operates in a High period as an ON period.

Semiconductor switch XQIYOI XLO+Yjo etc. is the 4th
When performing the operation shown in the figure, Uo+V(++
U301 V2O etc. are shown in C in Figure 4.

However, the control circuit of FIG. +VQ+W
ok occurs, phase voltage Uso, V2O, VS7
30k generation, for each, we have a carrier generation circuit 31°32 and a comparison circuit 4.5 ◇Accurately, the phase voltage Uo, Vo+Wo and the phase voltage [J301 V301
~3o and digit 4] cannot be even 30 degrees. Also, it is not possible to accurately match the scales. Therefore, equation (3)
The secondary side of the innovator transformer shown in FIG. 1 contains the fifth and seventh harmonic components.

Here, if the resonant frequency of the AC filter 2 in FIG. 1 is selected to be the fourth harmonic of the fundamental wave, the fifth harmonic is not attenuated but amplified in the output of the AC filter 2.

Therefore, the distortion rate of the output of the AC filter 2 deteriorates.

In order to prevent this, the resonant frequency of the AC filter 2 must be completely lowered, which has the disadvantage of increasing cost and increasing space.

[Purpose of the invention]

The purpose of the present invention is to provide a PW M '+t of an inverter device that outputs a three-phase sine wave that does not contain components below the tenth island frequency.
Provides a filter circuit.

[Summary of the invention]

The present invention provides a 06 i/verter (phase voltage Uo in Fig. 1).
+ V (the inverter that generates 1+ Wo) and the 30' inverter (the electric current generated at $- in Figure 1 BE Uso, V
so, W3(1) is synchronized alternately with the intersection of the falling sawtooth wave n whose frequency is 12 times the fundamental frequency and the voltage level Vc, and the 06-7 inverter and 30° The falling line voltage of the inverter is converted into a rising sawtooth whose frequency is 12 times the fundamental frequency.
They are alternately synchronized to the intersections of wave n and voltage level Vc.

In other words, the line f! of both inverters depends on the carrier wave and voltage level in the direction. JJ 'rlL voltage is raised and the line voltage of both inverters is lowered using the same carrier wave and voltage level. KJ means that the line voltage of the 0° inverter and the line voltage of the 30° inverter are precisely This allows the modulation depth to match accurately.

[Embodiments of the invention]

FIG. 5 shows an embodiment of the invention. Further, FIG. 6 is a time chart illustrating the entire operation of the circuit of FIG. 5. The excavation circuit 51 with an oscillation frequency of 12X212X fHz (f is the fundamental frequency) generates 1212 C/52f! : Drive. The output of the 212-decimal counter/returner 52 starts from the least significant bit. , DI, I)2. Ds, 1)4. D*, D6゜L)? 1 D81 D91 DIOI Dll,
212;if, the least significant bit of color/re52 is Do
Its frequency is 12×2”XfH2, and the most significant bit is D + + and its frequency is 12XfHz.

1) The /A conversion circuit 53 generates a rising sawtooth wave n by D/A converting the output D o ``''-D + + of the 21ffi base counter 52. The sawtooth wave n is shown in FIG. 6 and its amplitude is A. The D/A conversion circuit 54 is 212
The output of Shinkau/ri52. ~1)5. The complement of 1)/A
The conversion generates five falling sawtooth waves. A sawtooth wave n is shown in FIG. 6, and its amplitude is A. The DC amplifier 33 uses a feedback signal obtained by feeding back the output of the AC filter 2 shown in FIG. 1, and a setting 1 for setting the output of the AC filter 2 shown in FIG.
This is a circuit for direct and all calculations, and its output is Vc shown in FIG. Comparison circuit 4 is a sawtooth wave n and Vc
This is a circuit for comparing f. The output is D shown in Figure 6,
When the rising sawtooth wave n is rising, it rises in synchronization with the intersection with Vc. Further, D falls in synchronization with the fault with Vc when the rising sawtooth wave n falls.

The comparison circuit 5 is a circuit that compares the falling sawtooth waveform with Vck. The output is D shown in Fig. 6, D rises in synchronization with the intersection with Vc when the falling sawtooth wave n is falling, and Vc when the falling sawtooth wave ■ is rising. D falls in synchronization with the intersection with . - The binary counter 55 is a color driven by the most significant bit D11 of the 212 binary counter 2. The output is C8 shown in Figure 6,
It is C5°C21C'3. Its least significant bit is C8-
The frequency is 6XfHz, and its most significant bit is C1 and the frequency is fHu. The test liminator 9 is a circuit that generates all PWM waveforms. The operation is as follows: - Depending on whether the state of the output C6I C1l C21C of the binary counter 55 is 1-1-1i and 1eve1 or Low 1evel, the period of the inverter output is divided into 13 sections, and D and D are divided into 13 sections within each section.
The signals are rising and falling. ) Then, the rising edge of the line voltage between θ° and 30° I/verters is alternately synchronized with the rising edge of ff:D, and the rising edge of the line voltage between 0° and 30° In order to alternately synchronize with the rising edge of D, the phase voltages of 0° inverter and 30' inverter are started in synchronization with the rising edge of either D or 6 at valleys 1 and 3. By raising or lowering the
Control the line voltage between the converter and the 30° I/verter. 6th
Xo+YO+X in the figure. 1Y2O is the semiconductor switch shown in FIG. 1, and High level is the ON time. Uo + Vn + Uso +VSO in Figure 6 is the phase voltage in Figure 1, and Xov YO + Xso + Yso in Figure 6
are synchronized with each other. In this way, the semiconductor switch ff
: The phase voltage changes by #I operation.

Here, the pulse amplifier 10 operates the semiconductor switch. The discriminator 9 is the address kc of R (can be easily configured by using four JR units) (, L) M.
o, C1, C7, Cs, D, D) 1,0M data as X in Figure 6. = Yo, Xs. * Yso etc. may be used.

Here, P of an embodiment of the present invention P VV M system quotient j circuit
The WMfiJ degree K is 11.

However, in reality, the I)/A conversion circuits 53 and 54 or the comparison circuits 4 and 5vc have operational deviations, and the equation (8) does not hold. However, since both the line voltages of the ()0i7 inverter and the 306 inverter rise in synchronization with the rise of SL of D, and both fall in synchronization with the rise of D,
θ″′I/Inverter line voltage and 30°Inverter line +1J
The modulation degrees of the J voltages match, and their mutual phases are precisely 30 degrees apart.

Therefore, 2〇) holds true, and equation (3) also holds,
Equation (6) holds true. Therefore, one embodiment of the present invention P W
If the M feeding control circuit is used, the distortion rate can be lowered without increasing the size of the AC filter 2 shown in FIG. 1, which has the effect of making the inverter device inexpensive and compact.

FIG. 7 shows a modification of the invention. FIG. 8 is a time chart for District 7 1. The oscillation circuit 51 is the excavation circuit 1 in FIG.
Similarly, the binary counter/counter 52 is similar to the 212-base counter shown in FIG.
411JIII Di L)71 DB1 DOI D
In IOI Dll, count number is vertical axis, time is horizontal 111
If you take 111 K, as shown in Figure 8, Do”IJ++
becomes a digital sawtooth wave. The DC amplifier 33 is the fifth
It is similar to the DC amplifier shown in the figure. A/'D conversion circuit 7
7 converts the output of the DC amplifier 33 into a 1-bit digital input =
Convert to number.

The output is Ao, At, 4, from the least significant bit.
As.

A4. A6. As, A7. A+++ Ag,
A16. All.

The complement circuit 75 receives the outputs Ao to A, o of the A/D conversion circuit 77.
” AI and A.~A11 are expressed as shown in FIG. 8 when the vertical axis is the count number.
Generate D shown in the figure. Digital sawtooth wave Do
Du rises in synchronization with the intersection of -DBH rise and Ao"'-AIH, digital sawtooth wave Do -D.

D falls in synchronization with the intersection of the falling edge of Ao'' and A+I.

Comparison circuit 5 generates D shown in FIG. Digital sawtooth wave. -Dll rise and Ao”'-Al
In synchronization with the intersection of l, D goes up, digital sawtooth wave IJo~D, 1 falls and A. - D falls in synchronization with the intersection of All.

Therefore, the glue D in FIG. 7 and the glue D in FIG. 5 are equalized signals.

Note that lO in FIG. 1 is a pulse amplifier.

[Brief explanation of the drawing]

Fig. 1 is an inverter circuit diagram, Fig. 2 is a vector diagram of the inverter transformer shown in Fig. 1, Fig. 3 is a conventional PWM regulator circuit diagram, and Fig. 4 is a time chart of the P~'M regulator circuit in Fig. 3. , FIG. 5 is a PVLM control circuit diagram of one implementation of the present invention, Volume 6
The figure is an operation time chart of the PWM screaming circuit shown in Figure 5.
FIG. 7 is a circuit diagram of an example of the PWM control circuit shown in FIG. 5, and FIG. 8 is an operation time chart of the PWM 'dr134 circuit shown in FIG. $1 figure grass 2 eyes U. No. 30 8 Figure 4 IA5゜5th grid 1 j Nishiba〕71　L 5, Kaya 7 confinement crisis (t35'$ 8th ward

Claims (1)

[Claims] 1. An inverter that obtains an output approximating a sine wave by combining two sets of three-phase inverters with a phase difference of 30'', transistors, and attenuating harmonics with an AC filter consisting of a reactor and a capacitor. In the device, a circuit that generates a carrier wave of twelve times the inverter frequency;
a comparator that compares the fC DC voltage obtained by amplifying the difference between the set voltage and the output feedback voltage with the carrier wave, and a circuit that distributes the output of this comparator to the side slope I of the two sets of inverters. A PWM inverter device characterized by the following: