JPS6010949A - Serial transmission data advanced processing system - Google Patents

Serial transmission data advanced processing system

Info

Publication number
JPS6010949A
JPS6010949A JP58119026A JP11902683A JPS6010949A JP S6010949 A JPS6010949 A JP S6010949A JP 58119026 A JP58119026 A JP 58119026A JP 11902683 A JP11902683 A JP 11902683A JP S6010949 A JPS6010949 A JP S6010949A
Authority
JP
Japan
Prior art keywords
character
processing
data
bit
serial transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58119026A
Other languages
Japanese (ja)
Inventor
Toshiyuki Odakawa
小田川 敏之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58119026A priority Critical patent/JPS6010949A/en
Publication of JPS6010949A publication Critical patent/JPS6010949A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L13/00Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
    • H04L13/18Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00 of receivers

Abstract

PURPOSE:To attain a character processing control having a margin by executing the control relating to the character processing in advance when a data reaches a bit which can identify sufficiently what character the data is, among serial bits constituting a character to be transmitted. CONSTITUTION:When the 7th bit b7 of a character data 14 is received, a processing request is generated, then the processing request detection, the index processing processing 11'' of the character table, a loading processing of a character processing program (loading to a line processor memory)12'', running 13'' of character processing program are executed. As a result, a margin time T2 is increased than a conventional device and omitted words are decreased.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は通信制御装置またはデータ宅内装置等における
調歩同期方式の直列伝送データの受信に際しての先行制
御に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to advance control when receiving serially transmitted data in a start-stop synchronization system in a communication control device, a data home device, or the like.

(2)従来技術と問題点 第1図は調歩同期方式による直列伝送データを説明する
ための図であって、2はデータの波形、Lは一文字分の
データ長、3は同期回路の動作開始タイミング、4は情
報選択パルス、5は同期回路動作停止タイミング、6は
次の文字データ受信のだめの同期回路の動作開始タイミ
ングを示しており、STはスタートピット、b1〜b7
はそれぞれデータビット、Pはパリティピット、SPは
ストップビットを表わしている。
(2) Prior art and problems Figure 1 is a diagram for explaining serial transmission data using the start-stop synchronization method, where 2 is the data waveform, L is the data length of one character, and 3 is the start of operation of the synchronous circuit. 4 indicates the information selection pulse, 5 indicates the synchronous circuit operation stop timing, 6 indicates the synchronous circuit operation start timing for receiving the next character data, ST indicates the start pit, b1 to b7
are data bits, P is a parity pit, and SP is a stop bit.

第1図における文字は%OO101(11〃の7ビツト
からなシ偶数パリティの場合を示している・ 第2図は伝送線路上に文字データが連続して送られて来
る様子を表わした図で、7はデータの流れ、8〜10は
それぞれ文字データ、。
The characters in Figure 1 indicate the case of even parity of 7 bits of %OO101 (11). Figure 2 is a diagram showing how character data is continuously sent on the transmission line. , 7 is the data flow, and 8 to 10 are each character data.

11〜13はそれぞれ受信した文字に係る処理を表わし
ておυ、Lは第1図と同様に一文字分のデータ長である
11 to 13 each represent the processing related to the received character, and L is the data length of one character as in FIG.

第2図において文字8(STビットからSPビットまで
)を受信シ終ると、次に文字・の各ビットを受信してい
る間に、先に受信した文字8についての処理が行なわれ
る。すなわち、処理要求の検出と文字テーブルの索引処
理11、文字処理プログラムのローディング処理12、
文字処理プログ2ムの走行13が次々と実行される。
In FIG. 2, when character 8 (from the ST bit to the SP bit) is received, the previously received character 8 is processed while each bit of the character is being received. That is, processing request detection and character table index processing 11, character processing program loading processing 12,
Runs 13 of the character processing program 2 are executed one after another.

このような従来の処理方式においては、受信文字の各ビ
ットが全て正常に受信されたことが確認されてから、そ
の処理に入っているが1次に受信した文字(例えば第2
図の9)の処理要求が上る前に、その前に受信した文字
(この場合第2図の8)の処理が総て完了していないと
、該処理要求が受け付けられず、データの取シ込みが出
来ないため脱字を生ずる。そのため、回線単位にバッフ
ァを設けて一時的な負荷集中に備えたり、処理速度の速
いプロセッサを使う必要があるなどハードウェア量の増
大を招いたυ、経済性を損う問題点があった。
In such a conventional processing method, after confirming that all bits of a received character have been correctly received, processing begins, but the first received character (for example, the second
If the processing of all previously received characters (in this case, 8 in Figure 2) is not completed before the processing request 9) in the figure is sent, the processing request will not be accepted and the data will not be processed. Since it is not possible to include characters, omissions occur. As a result, it was necessary to provide a buffer for each line to prepare for temporary load concentration, and to use a processor with a high processing speed, which led to an increase in the amount of hardware and was detrimental to economic efficiency.

(3)発明の目的 本発明は上記従来の問題点に鑑み、ハードウェア量を増
加したり特に処理速度の速いプロセッサを使用すること
を要せずに余裕のある制御の可能な処理方式を提供する
ことを目的としている。
(3) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a processing method that allows for flexible control without increasing the amount of hardware or using a particularly fast processor. It is intended to.

(4)発明の構成 そしてこの目的は本発明によれば特許請求の範囲に記載
のとおり、調歩同期方式による直列伝送データの受信に
おいて、伝送すべき文字を構成する直列ビットの内、該
データが測知なる文字であるかを識別し得るに足るピッ
ト塩が到着したとき、以降到着する筈のビットおよび該
ビットを付加したときの該データが正常であることを想
定して、先行的に該文字の処理に係る制御を開始するこ
とを特徴とする直列伝送データ先行処理方式によシ達成
される。
(4) Structure and object of the invention According to the present invention, as described in the claims, in the reception of serial transmission data by the start-stop synchronization method, the data is When enough pit salt has arrived to identify whether the character is a ``sensor'' character, it is assumed that the bits that are expected to arrive later and the data when the bit is added are normal, and the data is detected in advance. This is achieved by a serial transmission data advance processing method characterized by starting control related to character processing.

(5)発明の実施例 ] 第5図は本発明の1実施例を説明するための図であって
、7は第2図と同様データの流れ、11′〜13′はそ
れぞれ従来の場合の受信した文字に係る処理、11“〜
15″はそれぞれ本発明による場合の受信した文字に係
る処理、14.15は文字データを表わしている。
(5) Embodiment of the invention] FIG. 5 is a diagram for explaining one embodiment of the present invention, where 7 is the same data flow as in FIG. Processing related to received characters, 11 “~
15'' represents processing related to received characters according to the present invention, and 14 and 15 represent character data.

第3図において、従来の方式では文字データ14を受信
したとき、そのストップビットspが到着してから処理
要求が出され、該処理要求の検出と文字テーブルの索引
処理11′、文字処理プログラムのローディング処理(
回線プロセッサのメモリへのローディング)12ζ文字
処理プログラムの走行13′等が実行されていた。本発
明の方式では文字データ14のb7ビツト目を受信した
とき、処理要求を出すことによシ、その後に受信される
パリティビットP1ストップビットSPを未確認のまま
先行的に文字データ14に係る処理11“〜13〃を実
行する。文字データはb1〜b7ピツトでそれが何の文
字であるかは識別出来るし、また一般にパリティエラー
やストップビットエに失敗して再処理をするための時間
的損失は無視し得る程度に少さい。
In FIG. 3, in the conventional method, when character data 14 is received, a processing request is issued after the stop bit SP arrives, and the processing request is detected, the character table indexing process 11', and the character processing program is executed. Loading process (
Loading into the memory of the line processor) 12ζ character processing program running 13', etc. were being executed. In the method of the present invention, when the b7th bit of character data 14 is received, by issuing a processing request, processing related to character data 14 can be performed in advance without checking the parity bit P1 stop bit SP that will be received subsequently. 11" to 13". Character data can be identified by the b1 to b7 pits, and generally there is no time required for reprocessing when a parity error or stop bit error occurs. The loss is negligible.

ある文字の処理プログラムの走行が終了してから、次の
文字の処理を開始しなければならないタイミングまでの
時間について従来の場合のT1(第3図参照)に比し本
発明の方式ではT2として表示したように大きくなる(
本例の場合は2ビツトの受信に要する時間だけ大きくな
る)。このT1またはT2なる時間は余裕時間であシ、
本発明ではこの時間が大きくとれるので受信中にエラー
が発生したり負荷が集中した場合等の時間調整能力が拡
大向上する。
Regarding the time from the end of running a processing program for a certain character to the timing at which processing for the next character must start, compared to T1 in the conventional case (see Fig. 3), in the method of the present invention, the time is T2. It will grow as shown (
In this example, the time required to receive 2 bits increases). This time T1 or T2 is a margin time,
In the present invention, since this time can be increased, the ability to adjust the time when an error occurs during reception or when loads are concentrated is expanded and improved.

文字のコード系によってはパリティビットが無く、最終
ビット(ビット7)がシ〃であるときには、核データが
メツセージであることを表示しているような場合もある
が、前記と全く同様に先行的に処理を開始することが可
能である。
Depending on the character code system, when there is no parity bit and the final bit (bit 7) is ``S'', it may indicate that the nuclear data is a message, but in the same way as above, there is no parity bit. It is possible to start processing immediately.

以上説明したように本発明の方式によれば、調歩同期方
式による直列伝送データの受信において、文字の処理に
係る制御を先行的に行なうことによシ、受信文字間の処
理時間間隔を大きく調整することが可能となるから、次
のデータの取シ込みが遅れて脱字を生じたシすることが
無くなる。またそのためにバッファを設けたシ、処理速
度の速いプロセッサを必要とすること無〈従来のハード
ウェアで容易に実現出来るから効果は大である。
As explained above, according to the method of the present invention, in the reception of serially transmitted data using the start-stop synchronization method, by performing control related to character processing in advance, the processing time interval between received characters can be greatly adjusted. This eliminates the possibility of omitted characters due to delays in importing the next data. Moreover, it does not require a buffer or a processor with a high processing speed (it can be easily realized using conventional hardware), so the effect is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は調歩同期方式による直列伝送データを説明する
ための図、第2図は伝送線路上に文字データが連続して
送られて来る様子を表わした図、第3図は本発明の1実
施例を説明するための図である。 2・・・データの波形、3・・・同期回路の動作開始タ
イミング、4・・・情報選択パルス、5・・・同期回路
動作停止タイミング、6・・・次の文字データ受信のた
めの同期回路の動作開始タイミング、7・・・データの
流れ、8.9.10・・・文字データ、11〜1!、1
1’〜13′、11“〜13“・・・受信した文字に係
る処理 第1回 第2回 第3図
Fig. 1 is a diagram for explaining serial transmission data using the start-stop synchronization method, Fig. 2 is a diagram showing how character data is continuously sent on a transmission line, and Fig. 3 is a diagram for explaining serial transmission data using the start-stop synchronization method. It is a figure for explaining an example. 2... Data waveform, 3... Synchronous circuit operation start timing, 4... Information selection pulse, 5... Synchronous circuit operation stop timing, 6... Synchronization for receiving next character data Circuit operation start timing, 7...Data flow, 8.9.10...Character data, 11-1! ,1
1' to 13', 11" to 13"... Processing related to received characters 1st 2nd 3rd figure

Claims (1)

【特許請求の範囲】[Claims] 調歩同期方式による直列伝送データの受信において、伝
送すべき文字を構成する直列ビットの内、該データが何
如なる文字であるかを識別し得るに足るビット迄が到着
したとき、以降到着する筈のビットおよび該ビットを付
加したときの該データが正常であることを想定して、先
行的に該文字の処理に係る制御を開始することを特徴と
する直列伝送データ先行処理方式。
When receiving serially transmitted data using the start-stop synchronization method, when enough bits have arrived to identify what kind of character the data is, among the serial bits that make up the character to be transmitted, A serial transmission data advance processing method characterized by starting control related to processing of the character in advance, assuming that the bit and the data when the bit is added are normal.
JP58119026A 1983-06-30 1983-06-30 Serial transmission data advanced processing system Pending JPS6010949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58119026A JPS6010949A (en) 1983-06-30 1983-06-30 Serial transmission data advanced processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58119026A JPS6010949A (en) 1983-06-30 1983-06-30 Serial transmission data advanced processing system

Publications (1)

Publication Number Publication Date
JPS6010949A true JPS6010949A (en) 1985-01-21

Family

ID=14751140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58119026A Pending JPS6010949A (en) 1983-06-30 1983-06-30 Serial transmission data advanced processing system

Country Status (1)

Country Link
JP (1) JPS6010949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58180159U (en) * 1982-05-25 1983-12-01 足立 宗三郎 Installation structure of cutting tape in packaging with palm-shaped seals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58180159U (en) * 1982-05-25 1983-12-01 足立 宗三郎 Installation structure of cutting tape in packaging with palm-shaped seals
JPS6143721Y2 (en) * 1982-05-25 1986-12-10

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